Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 14, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1) in view of Thomsen et. al. (U.S. Publication No 2014/0176250).
Regarding claim 1, Tang et. al. discloses a switched-capacitor current source (e.g. circuit 130 and 200)(Fig. 1 and 2), comprising: a first transistor (e.g. 233)(Fig. 2) having a source coupled to a power supply node (e.g. node connected between power source 130 and circuit 200)(Fig. 1) for a power supply voltage (e.g. 130);
Tang et. al. does not disclose a first switch coupled to a drain of the first transistor; a first switched-capacitor resistor including a first capacitor, the first switched-capacitor resistor being configured to couple a first plate of the first capacitor to the first switch to charge the first capacitor from the power supply node during a charging clock phase of a first clock signal, wherein a second plate of the first capacitor is coupled to ground during the charging clock phase; a second switch coupled to the drain of the first transistor; and a second switched-capacitor resistor including a second capacitor, the second switched- capacitor resistor being configured to couple a first plate of the second capacitor to the second switch to charge the second capacitor from the power supply node during a charging clock phase of a second clock signal, wherein a second plate of the second capacitor is coupled to ground during the charging clock phase.
However, Thomsen et. al. teaches a first switch (e.g. S5)(Fig. 1-4) coupled to a drain of the first transistor;
a first switched-capacitor resistor (e.g. S6/S5/S4/C2)(Fig. 1-4) including
a first capacitor (e.g. C2)(Fig. 1-4), the first switched-capacitor resistor being configured to couple a first plate (e.g. top of C2)(Fig. 1-4) of the first capacitor to the first switch to charge the first capacitor from the power supply node during a charging clock phase of a first clock signal (Para [0025], “FIGS. 1-4, which show selection of control switches at different periods of a clock cycle…. switch S5 of switched capacitor stage 110.sub.2 is closed such that capacitor C2 begins charging from a pre-charge state”), wherein
a second plate of the first capacitor is coupled to ground during the charging clock phase (e.g. C2 connected to ground)(Fig. 1-4);
a second switch (e.g. S2)(Fig. 1-4) coupled to the drain of the first transistor; and a second switched-capacitor resistor (e.g. S1/S2/S3/C1)(Fig. 1-4) including a second capacitor (e.g. C1)(Fig. 1-4), the second switched-capacitor resistor being configured to couple a first plate of the second capacitor to the second switch to charge the second capacitor from the power supply node during a charging clock phase of a second clock signal (Para [0028], “ a further portion of a clock cycle. As seen in FIG. 2, circuit 100 is the same as in FIG. 1, however note the different arrangement of the switches such that with switch S3 open in switched capacitor stage 110.sub.1 capacitor C1 begins charging to a pre-charge voltage”), wherein
a second plate of the second capacitor is coupled to ground during the charging clock phase (e.g. C1 connected to ground)(Fig. 1-4).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added the “first and second switched-capacitor resistor circuits” as taught by Thomsen et. al. into Tang’s et. al. “switched-capacitor current source” circuit in order to provide better transient control means and to prevent unwanted fluctuations in the circuit operation, thus increasing operational efficiencies.
Regarding claim 2, Tang et. al. discloses a diode-connected transistor (e.g. 230)(Fig. 2) having a source coupled to the power supply node (node connected between power source 130 and circuit 200)(Fig. 1) and a gate (e.g. gate of 230)(Fig. 2) coupled to a gate of the first transistor (e.g. gate of 233)(Fig. 2); a second transistor (e.g. 224)(Fig. 2) having a source coupled to ground (e.g. source of 224 connected to ground)(Fig. 2) and a drain coupled to a drain of the diode connected transistor (e.g. drain of 224 connected to 230)(Fig. 2); and a differential amplifier (e.g. 239)(Fig. 2) having an output terminal coupled to a gate of the second transistor (e.g. output of 239 connected to gate of 224)(Fig. 2).
Regarding claim 3, Tang et. al. discloses the differential amplifier includes a first input terminal for receiving a reference voltage (e.g. VBG input to 239 first terminal)(Fig. 2) and includes a second input terminal coupled to the output terminal (e.g. output of 239 goes back into 239 second terminal)(Fig. 2).
Regarding claim 4, Tang et. al. discloses the second input terminal is coupled to the output terminal through a coupling capacitor (e.g. 257)(Fig. 2).
Regarding claim 6, Tang et. al. explicitly discloses the first input terminal is a non-inverting input terminal, and wherein the second input terminal is an inverting input terminal (implied 239)(Fig. 2).
Regarding claim 14, Tang et. al. and Thomsen et. al. substantially teach the limitations as stated in claim 1. Thang et. al. and Thomsen et. al. further teach sourcing the current from a common node in a first and second switched-capacitor resistor to a reference voltage during a first and second phase of a clock signal (Thomsen et. al. Para [0003], “a first capacitor to pre-charge to a first voltage exceeding a first reference voltage by a first delay compensation voltage during a first portion of a clock period and thereafter to charge to a second voltage exceeding a second reference voltage by a second delay compensation voltage during a second portion of the clock period”).
Regarding claim 15, Tang et. al. discloses mirroring the current to form a bias current (e.g. IMC)(Fig. 2); and
biasing an external circuit (e.g. 203)(Fig. 1) with the bias current, wherein the bias current is substantially insensitive to a duty cycle of the clock signal. (Para [0023], “The MOSFET circuits 224, 227, 230, and 233, as well as the non-inverting charge amplifier 221 control the current, IMC, across the second on-chip resistor 209 by varying the voltage generated by the capacitor bank 212. The current, IMC, across the second on-chip resistor 209 is given by: IMC=2*VBG * Cmim/Tclk. Equation 1, where Cmim is the total capacitance of the capacitor bank 212 and Tclk is the clock period of Cmim”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1) and Thomsen et. al. (U.S. Publication No 2014/0176250) in further view of Zhou et. al. (U.S. Publication No 2025/0015811).
Regarding claim 5, although Tang et. al. and Thomsen et. al. disclose the limitations of claim 3. They do not teach a third switch coupled between the first switched-capacitor resistor and the second input terminal; and a fourth switch coupled between the second switched-capacitor resistor and the second input terminal.
However, Zhou et. al. teaches a third switch (e.g. M4)(Fig. 3) coupled between the first switched-capacitor resistor and the second input terminal (implied Fig. 3); and a fourth switch (e.g. M8)(Fig. 3) coupled between the second switched-capacitor resistor and the second input terminal (implied Fig. 3).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added the “third and fourth switch” as taught by Zhou et. al. into Tang’s et. al. and Thomsen’s et. al. “switched capacitor current source” circuit in order to provide better transient control means and to prevent unwanted fluctuations in the circuit operation, thus increasing operational efficiencies.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1) and Thomsen et. al. (U.S. Publication No 2014/0176250) in further view of Routledge et. al. (U.S. Publication No 2025/0266763).
Regarding claim 7, although Tang et. al. and Thomsen et. al. disclose the limitations of claim 1. They do not teach the first switch is configured to close during the charging clock phase of the first clock signal, and wherein the second switch is configured to close during the charging clock phase of the second clock signal.
However, Routledge et. al. teaches the first switch (e.g. 306a1)(Fig. 3A) is configured to close during the charging clock phase of the first clock signal (e.g. P1)(Fig. 3A), and wherein the second switch (e.g. 306b1)(Fig. 3A) is configured to close during the charging clock phase of the second clock signal (e.g. P2)(Fig. 3A).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added the “first and second switches are configured to close during charging phase of the first and second clock signal” as taught by Routledge et. al. into Tang’s et. al. and Thomsen’s et. al. “switched capacitor current source” circuit in order to provide better transient control means and to prevent unwanted fluctuations in the circuit operation, thus increasing operational efficiencies.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1) and Thomsen et. al. (U.S. Publication No 2014/0176250) in further view of Luo (U.S. Publication No 2005/0206546).
Regarding claim 8, although Tang et. al. and Thomsen et. al. disclose the limitations of claim 1. They do not teach a capacitance of the first capacitor equals a capacitance of the second capacitor.
However, Luo teaches a capacitance of the first capacitor equals a capacitance of the second capacitor. (Para [0025], “The capacitors 210, 212, 214, 216, 218, 220, 222 and 224 have capacitance values C.sub.1, C.sub.2, C.sub.3, C.sub.4, C.sub.5, C.sub.6, C.sub.7 and C.sub.8 respectively. The capacitance values C.sub.1, C.sub.2, C.sub.3, C.sub.4, C.sub.5, C.sub.6, C.sub.7 and C.sub.8 should each equal the same capacitance C”)
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added “a capacitance of the first capacitor equals a capacitance of the second capacitor” as taught by Luo into Tang’s et. al. and Thomsen’s et. al. “switched-capacitor current source” circuit because it provides for a reduction in component variance, which can increase operational efficiencies.
Regarding claim 9, although Tang et. al., Thomsen et. al., and Luo disclose the limitations of claim 8. They do not teach the capacitance of the first capacitor is proportional to a capacitance of an integrating capacitor in a continuous-time integration stage of an analog-to-digital converter.
Tang et. al. discloses the claimed invention except for capacitance of the first capacitor is proportional to a capacitance of an integrating capacitor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the first capacitor is proportional to a capacitance of an integrating capacitor, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the “switched-capacitor current source” circuit to include the features of a type of the first capacitor is proportional to a capacitance of an integrating capacitor because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1) and Thomsen et. al. (U.S. Publication No 2014/0176250) in further view of Aboueldahab (U.S. Patent No 10263514).
Regarding claim 12, although Tang et. al. and Thomsen et. al. disclose the limitations of claim 1. They do not teach the first clock signal and the second clock signal comprise a pair of complementary and non-overlapping clock signals.
However, Aboueldahab discloses the first clock signal and the second clock signal comprise a pair of complementary and non-overlapping clock signals. (Col 5, Lines 52-56, “Each switch 306a1-306a4, 306b1-306b4 is coupled to one of two clock phases, P1 or P2. FIG. 3B is a timing diagram 350 of a multi-phase clock signal having two phases for use in conjunction with the circuit shown in FIG. 3A; in general, the pulses of phases P1 and P2 should not overlap”)
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added “the first clock signal and the second clock signal comprise a pair of complementary and non-overlapping clock signals” as taught by Aboueldahab into Tang’s et. al. and Thomsen’s et. al. “switched-capacitor current source” circuit because it provides for a reduction in component variance, which can increase operational efficiencies.
9. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et. al. (U.S. Publication No 2017/0085986 A1), Thomsen et. al. (U.S. Publication No 2014/0176250), and Luo (U.S. Publication No 2005/0206546) in further view of Lee et. al. (U.S. Publication No 2018/0183456).
Regarding claim 13, although Tang et. al., Thomsen et. al., and Luo disclose the limitations of claim 9. They do not teach the analog-to-digital converter is configured to convert an audio signal.
However, Lee et. al. teaches the analog-to-digital converter is configured to convert an audio signal. (Para [0021], “when SAR ADC 200 is implemented in CMOS and/or when SAR ADC 200 is employed to convert audio data in an analog signal 261 into audio data in a corresponding digital signal including digital values 262”)
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally added the “the analog-to digital converter is configured to convert an audio signal” as taught by Lee et. al. into Tang’s et. al., Thomsen’s et. al., and Luo’s “switched-capacitor current source” circuit in order to provide a specific design choice, which can provide a reduction on component variance, thus increasing operational efficiencies.
Allowable Subject Matter
Claims 10-11 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggest “a tuning circuit including a variable tuning resistor configured to be charged by a mirrored version of a charging current conducted by the first transistor”. Claim 11 is indicated allowable, as it depends on claim 10.
Regarding claim 16, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggest “comparing the tuning voltage to the reference voltage to form a comparator output signal; adjusting a resistance of the variable tuning resistor according to a digital code that is responsive to comparator output signal; and adjusting a resistance of an input resistor in a continuous-time integration stage of an analog-to-digital converter responsive to the digital code”.
Claims 17-20 are allowed.
Regarding claim 17, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggest “a first shielding line adjacent the top plate of the first capacitor between the top plate and grounded signal nodes of the switched-capacitor current source, wherein the first shielding line is configured to be charged during the charging clock phase of the first clock signal”. Claims 18-20 are indicated allowable, as it depends on claim 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838