DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2024/0264863) in view of Suenaga et al. (U.S. PGPub No. 2015/0089115).
Claim 1
Yang (2024/0264863) teaches:
A computational storage device comprising:
a memory device configured to store therein a data unit group including a plurality of data units; and FIG. 1 and P. 0060 memory device 120
a controller having circuitry and disposed in the computational storage device, the controller configured to: FIG. 1 and P. 0060 memory controller 112
receive a computational operation request from a host device, the computational operation request including information of a start logical address of the data unit group and a size of each of the plurality of data units, P. 0173 operation identification codes SLS0, SLS1, and SLS2 may be reserved for the host processing instructions indicating SLS operations. The host may only table information, indices vector 1120 information, and vector size information, as input values, together with the operation identification code (OPCODE) to the memory device. The values corresponding to the code SLS2 may include a start address of the indices vector 1120 and a size (indices size) of the indices vector 1120 (e.g., a size corresponding to the number of elements included in the indices vector 1120).
calculate, based on the information, one or more logical addresses, to which a target data unit that is included in the data unit group has been allocated and is a target of a computational operation to be performed in response to the computational operation request, P. 0169 An indices vector 1120 may include, as element values, indices sequentially indicating rows, the targets of the SLS operation, in the data table 1130; P. 0179 PNM engine 1122 may determine row addresses corresponding to the indices (e.g., [2, 3, 5] in FIG. 11C) grouped based on the element values of the lengths vector 1110 from the indices vector 1120
calculate a start logical address and a start offset of the target data unit based on information, the start logical address being included in the one or more logical addresses, P. 0179 PNM engine 1122 may determine an address where, a row vector corresponding to an index indicated by a corresponding index value is positioned, from a start address of the data table 1130 based on the individual element values of the indices vector 1120
read, from the memory device, data corresponding to the one or more logical addresses, identify the target data unit in the read data, and P. 0108 when the host processing instruction is an SLS operation, each of the sub-processing instructions may include a read instruction; P. 0112 the PNM engine 311 may perform an operation by directly reading data (e.g., a value) for the operation from a memory block
wherein when the data unit group is a database table, the plurality of data units correspond to respective rows or columns included in the database table, and when the data unit group is an embedding table, the plurality of data units correspond to respective vectors included in the embedding table. P. 0076 embedding vectors are read from the memory blocks 220; P. 0077 a reduction operation may gather and add each embedding vector in an embedding table
Yang does not explicitly teach the calculated addresses being logical addresses.
Suenaga (2015/0089115) teaches:
calculate, based on a computational operation request from a host device, one or more logical addresses, to which a target data unit that is included in the data unit group has been allocated and is a target of a computational operation to be performed in response to the computational operation request, P. 0063-64 and FIG. 11 the host sends a write request for 8 logical sectors, starting from logical block address 7. The end logical block address is determined to be 14; P. 0117 read requests also include a start logical block address;
read, from the memory device, data corresponding to the one or more logical addresses, identify the target data unit in the read data, and P. 0065 host 30 first reads data in the area with physical block addresses 0 to 1 corresponding to logical block addresses 7-15, i.e., 16 logical blocks of data [read data], onto a memory. Then writes the data [target unit] requested to be written (i.e. logical block addresses 7-15) into the read data; P. 0117 host may also accept read requests specifying a read area [target unit] with a start logical block address and size, where reads are also aligned to standard units
transmit an operational result of the computational operation on the target data unit to the host device, P. 0092 control unit 130 notifies the host 300 of the completion of the requested write process
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Yang with the calculated addresses being logical addresses taught by Suenaga
The motivation being the performance degradation is invisible to the host (see Suenaga P. 0100)
The systems of Yang and Suenaga are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang with Suenaga to obtain the invention as recited in claims 1-11.
Claim 9
Suenaga (2015/0089115) teaches:
The computational storage device according to claim 1, wherein the controller is configured to: convert the logical address into a physical address, and control the memory device to output, to the controller, the read data from a memory region corresponding to the physical address. P. 0073 RAID management unit 120 manages the correspondence relation between physical block addresses and logical block addresses; P. 0074 disk processing control unit 130 accesses the respective storage media for performing reads and writes
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2024/0264863) in view of Suenaga et al. (U.S. PGPub No. 2015/0089115) in view of Nellayi et al. (U.S. PGPub No. 2018/0293161)
Claim 2
The systems of Yang and Suenaga do not explicitly teach the start offset corresponding to a number of bytes from the start location of the read data.
Nellayi (2018/0293161) teaches:
The computational storage device according to claim 1, wherein the start offset corresponds to a number of bytes from a foremost location of the read data, which corresponds to the start logical address of the target data unit, to a location at which the target data unit is started. P. 0024 the offset value is the number of bytes by which the device offset is to be shifted to align with the logical offset
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Yang and Suenaga with the start offset corresponding to a number of bytes from the start location of the read data taught by Nellayi
The motivation being differences in alignment can affect efficiency of capacity optimization techniques (see Nellayi P. 0012)
The systems of Yang, Suenaga and Nellayi are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang and Suenaga with Nellayi to obtain the invention as recited in claim 2.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2024/0264863) in view of Suenaga et al. (U.S. PGPub No. 2015/0089115) in view of Mayo et al. (U.S. PGPub No. 2020/0241784)
Claim 10
The systems of Yang and Suenaga do not explicitly teach an index cache storing indices of a plurality of data units, which is used to calculate the logical addresses.
Mayo (2020/0241784) teaches:
The computational storage device according to claim 1, wherein: the controller comprises an index cache for storing indices of the plurality of data units, and the controller is further configured to refer, when an index of the target data unit has already been stored in the index cache, to the index of the target data unit that has been stored in the index cache to calculate the one or more logical addresses. P. 0043 and FIG. 2 append a start partial chunk entry 130 including a length 232 "m" [start offset] for the sub-range of the start data chunk 120 represented by entry 202, to destination manifest 128 [index]; P. 0045 and FIG. 2 module 126 may append an end partial chunk entry 132, including a length 238 "n" [last offset] for the sub-range in the end data chunk 205, to the destination manifest 128; P. 0041 each entry includes an ID of the corresponding data chunk [analogous to a logical address]; P. 0022 the target manifest may be stored on the target deduplication domain; P. 0034 the target I/O request may include an identifier of the block, an offset between the target address and the block address and a size of the target address. The start address and end address of the target address may be obtained depending on the offset and the length
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Yang and Suenaga with an index cache storing indices of a plurality of data units, which is used to calculate the logical addresses taught by Mayo
The motivation being a match may be obtained without the need to send any chunk data (see Mayo P. 0023)
The systems of Yang and Suenaga and Mayo are analogous because they are from the "same field of endeavor" and from the same "problem solving area." Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang and Suenaga with Mayo to obtain the invention as recited in claim 10.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2024/0264863) in view of Suenaga et al. (U.S. PGPub No. 2015/0089115) in view of Desai et al. (U.S. PGPub No. 2020/0081830)
Claim 11
Yang (2024/0264863) teaches:
allocate, to another target data unit, the one or more logical addresses in response to a second subsequent computational operation request for adding the other target data unit to the data unit group. P. 0173 operation identification codes SLS0, SLS1, and SLS2 may be reserved for the host processing instructions indicating SLS operations
The systems of Yang and Suenaga do not explicitly teach modifying sequence numbers of data units when the target unit is deallocated.
Desai (2020/0081830) teaches:
The computational storage device according to claim 1, wherein the controller is further configured to: modify respective sequence numbers of data units subsequent to the target data unit among the plurality of data units and invalidate the target data unit, in response to a first subsequent computational operation request for removing the target data unit from the data unit group, and P. 0037 deallocate commands may specify an address in the trim range that is not aligned with a start of a cluster, each trim range has a logical block start address and a logical block end address; P. 0026 SSD system 100 maintains the deallocation address range and start and end addresses for every deallocate command, and the sequence position of the deallocate command in relation to the order of other received commands, as entries in the trim table 124
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Yang and Suenaga with modifying sequence numbers of data units when the target unit is deallocated taught by Desai
The motivation being coherence and determinism of the deallocation (See Desai P. 0044)
The systems of Yang and Suenaga and Desai are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang and Suenaga with Desai to obtain the invention as recited in claim 11.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2024/0264863) in view of Nellayi et al. (U.S. PGPub No. 2018/0293161)
Claim 18
Yang (2024/0264863) teaches:
A data processing system comprising:
a host device configured to transmit, to the computational storage device, a computational operation request for the data unit group, P. 0065 device controller 123 may process a host instruction received from a host; P. 0106 the host processing instruction is a sparse lengths sum (SLS) operation
the computational operation request including information of a start logical address of the data unit group and a size of each of a plurality of data units in the data unit group, FIG. 1 and P. 0060 memory device 120; P. 0173 operation identification codes SLS0, SLS1, and SLS2 may be reserved for the host processing instructions indicating SLS operations. The host may only table information, indices vector 1120 information, and vector size information, as input values, together with the operation identification code (OPCODE) to the memory device. The values corresponding to the code SLS2 may include a start address of the indices vector 1120 and a size (indices size) of the indices vector 1120 (e.g., a size corresponding to the number of elements included in the indices vector 1120)
wherein the computational storage device performs a computational operation on the data unit group in response to the computational operation request, and P. 0112 the PNM engine 311 may perform an operation by directly reading data (e.g., a value) for the operation from a memory block, and perform the operation corresponding to given instruction information
transmits an operation result of the computational operation to the host device, P. 0113 When the operation according to the host processing instruction is completed, the memory device 302 may transmit the entire operation result to the host 301
wherein when the data unit group is a database table, the plurality of data units correspond to respective rows or columns included in the database table, and when the data unit group is an embedding table, the plurality of data units correspond to respective vectors included in the embedding table. P. 0076 embedding vectors are read from the memory blocks 220; P. 0077 a reduction operation may gather and add each embedding vector in an embedding table
Yang does not explicitly teach allocating consecutive logical addresses to a data unit group.
Nellayi (2018/0293161) teaches:
a computational storage device configured to allocate consecutive logical addresses to a data unit group when storing therein the data unit group; and FIG. 1a and P. 0021 a free region [group] on the storage device 106; P. 0049 free regions are aligned in chunks [units]; P. 0033 receive a storage allocation request comprising a device offset for a free region [group] in the storage device, a logical offset of data to be stored [target unit], and a chunk size
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Yang with allocating consecutive logical addresses to a data unit group taught by Nellayi
The motivation being perform the alignment for different storage devices having different chunk sizes without having to implement a variable chunking model or variable sized file system block support (see Nellayi P. 0016)
The systems of Yang and Nellayi are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang with Nellayi to obtain the invention as recited in claims 18-20.
Claim 19
Nellayi (2018/0293161) teaches:
The data processing system according to claim 18, wherein the computational storage device is further configured to: determine a target data unit on which the computational operation is to be performed among a plurality of data units included in the data unit group, P. 0033 receive a storage allocation request comprising a device offset for a free region [group] in the storage device, a logical offset of data to be stored [target unit], and a chunk size; P. 0035 FS alignment module 104 can determine a device start address and a device end address [logical addresses] for the storage allocation request
determine one or more logical addresses, to which the target data unit has been allocated, and P. 0033-34 the FS alignment module 104 can determine a device start address for the storage allocation request, by offsetting the received device offset with an offset value [start offset]
Yang (2024/0264863) teaches:
obtain the target data unit by performing a read operation on one or more physical addresses mapped to the one or more logical addresses. P. 0108 when the host processing instruction is an SLS operation, each of the sub-processing instructions may include a read (e.g., READ) instruction, and the instruction generator 335 may repeatedly produce read instructions for the SLS operation
Claim 20
Nellayi (2018/0293161) teaches:
The data processing system according to claim 18, wherein the host device is further configured to designate a range of logical addresses to which the data unit group is allocable for the computational storage device. P. 0033 receive a storage allocation request comprising a device offset for a free region [group] in the storage device, a logical offset of data to be stored [target unit], and a chunk size; P. 0035 FS alignment module 104 can determine a device start address and a device end address [logical addresses] for the storage allocation request
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 3-8 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 3 recites the limitation “wherein the controller is further configured to calculate, when the target data unit is unaligned data, a last logical address and a last offset of the target data unit based on the information”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0135-160 and FIG. 9B]. Said limitations, in combination with the other recited limitations of claim 3, are not taught or suggested by a reasonable combination of the prior art of record.
The closest prior art of record includes Yang (2024/0264863), Nellayi (2018/0293161), Suenaga (2015/0089115), and Mayo (2020/0241784). None of the references teach calculating a last logical address when target data is from rows and columns of a table or vectors in an embedding table and is unaligned.
Claims 4-8 depend from claim 3, and are considered allowable for at least the same reasons as claim 3.
Claim 12 recites the limitation “receive a computational operation request from a host device, the computational operation request including information of a start logical address of the data unit group and a size of each of the plurality of data units,
calculate, based on the information a first logical address, to which a selected part of a target data unit included in the data unit group has been allocated, and an unaligned flag for the target data unit, calculate, when the target data unit is determined to be unaligned data according to the unaligned flag, a second logical address, to which a remaining part of the target data unit has been allocated, read, from the memory device, first read data corresponding to the first logical address and second read data corresponding to the second logical address,
obtain the target data unit from the first read data and the second read data, and transmit an operation result of a computational operation on the target data unit, in response to the computational operation request, to the external host device,
wherein, when the data unit group is an embedding table, the plurality of data units correspond to respective vectors included in the embedding table”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0135-160 and FIG. 9B]. Said limitations, in combination with the other recited limitations of claim 12, are not taught or suggested by a reasonable combination of the prior art of record.
The closest prior art of record includes Yang (2024/0264863), Nellayi (2018/0293161), Suenaga (2015/0089115), and Mayo (2020/0241784). None of the references teach calculating a start logical address from a data group start logical address received in a host request, when target data is from rows and columns of a table or vectors in an embedding table and is unaligned.
Claims 13-16 depend from claim 12, and are considered allowable for at least the same reasons as claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mosiolek et al. (U.S. PGPub No. 2017/0255565) teaches commands for moving a region, the command including a start and end address, size of the region, a set of addresses to access the region, and an offset.
Punniyamurthy et al. (U.S. PGPub No. 2025/0110899) teaches a first reduction operation being a direct memory access (DMA) packet that has a header that stores information such multiple starting addresses corresponding to a local memory of the processing element that stores the multiple particular embedding rows of the embedding table to use in the reduction operation, a data size of elements, such as a data size of an embedding row of the embedding table 312
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached on (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133