DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Amendment filed on 03/03/2026 regarding claims 1-23 is fully considered. Of the above claims, claims 1-2 and 5-8 have been amended, and claims 19-23 have been newly added.
Election/Restrictions
Claims 7-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventions II and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/03/2026.
Applicant’s election without traverse of invention I in the reply filed on 03/03/2026 is acknowledged.
Claim Objections
Claim 4 are objected to because of the following informalities:
Regarding claim 4, the examiner recommends reciting “at least two alternate plane transistors [including the at least one alternate plane transistor]”. This amendment is recommended in order to be consistent with the wording in claim 1 from which claim 4 depends from.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 19 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chadwick et al. (US 9,520,876 B1).
Regarding claim 1, Chadwick et al. teach a system for increasing the yield of manufactured integrated circuits (the present embodiment may allow for more use of back end of line portions of semiconductors, thereby reducing over crowdedness and power dissipation of electrical circuitry of front end of line portions in semiconductor devices; column 2, lines 51-64), each integrated circuit comprising:
a designed set of circuits implemented as front end of line manufactured circuit elements (the FEOL portion 201 can include one or more LPUs, i.e. a first LPU 205 and the second LPU 206; FIG. 2; column 6, lines 10-33), including at least one remedial front end of line circuit element that is configured to remediate operation of at least one of the front end of line manufactured circuit elements (the data can be stored in the latch 212 until the power grid 211 and the clock net 210 are activated; FIG. 2; column 6, lines 34-57);
at least one alternate plane transistor, the at least one alternate plane transistor operable to selectively activate or deactivate, post manufacture of the integrated circuit, the at least one remedial front end of line circuit element in accordance with a result of an execution performed on the integrated circuit (the electrical signal can trigger the power gate and the clock gate 209 to activate the power grid 211 and the clock net 210, respectively; FIG. 2; column 6, line 58 to column 7, line 8; the first LPU 205 is executed to output a signal via the enable wire 207).
Further regarding claim 1, Chadwick et al. do not teach the execution of the integrated circuit is a test.
Further regarding claim 1, it would have been obvious to one of ordinary skill in the art to subject the semiconductor 200 to a set of test data for the purpose of determining the type of data that would enable a transistor to activate the next logical processing unit.
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Chadwick et al. to subject the integrated circuit to a series of tests for the purpose of predetermining the type of data that would enable a transistor to activate the next logical processing unit.
Regarding claim 2, Chadwick et al. teach wherein the at least one remedial front end of line circuit element comprises a buffer to strengthen a signal at the at least one of the front end of line manufactured circuit elements (the latch 212 functions as a buffer register; FIG. 2).
Regarding claim 3, Chadwick et al. teach wherein the buffer is a clock buffer (an input of the latch 212 comes from the clock net 210; FIG. 2).
Regarding claim 19, Chadwick et al. teach wherein the at least one alternate plane transistor is operable to selectively activate or deactivate, post manufacture of the integrated circuit, the at least one remedial front end of line circuit element in accordance with the result of the test as indicated by a dynamic signal generated at the designed set of circuits (the signal generated in the enable wire 207 is dynamically transmitted by the first LPU 205 by performing first operation on data; FIG. 2).
Regarding claim 22, Chadwick et al. teach wherein the at least one remedial front end of line circuit element comprises a buffer to strengthen an output signal (the latch 212 functions as a buffer register; FIG. 2).
Regarding claim 23, Chadwick et al. teach wherein the at least one alternate plane transistor is a back end of line transistor or a middle of line transistor (the power gate and the clock gate 209 in the back end of line portion; FIG. 2).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chadwick et al. (US 9,520,876 B1) in view of Bucelot et al. (US 2014/0223210 A1).
Regarding claim 5, Chadwick et al. do not teach a programmable element to control the selective activation and deactivation of the at least one remedial front end of line circuit element.
Further regarding claim 5, Bucelot et al. teach a programmable element to control the selective activation and deactivation of at least one front end of line circuit element (the programmable buffer has a constant front end-of-line footprint over all programming and tunable steps that can be adjusted at the back end-of-line; [0043]; programmable sector buffer; FIG. 13A; [0075]) for the purpose of providing for a tunable latency and slew rate over a programming range.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a programmable element to control the selective activation and deactivation of the at least one remedial front end of line circuit element, as taught by Bucelot et al., into Chadwick et al. for the purpose of providing for a tunable latency and slew rate over a programming range.
Allowable Subject Matter
Claims 4, 6 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter of claim(s) 4 is the inclusion of “wherein the integrated circuit includes at least two remedial front end circuit elements and at least two alternate plane transistors and wherein a first one of the at least two alternate plane transistors is operable to selectively activate or deactivate a first one of the at least two remedial front end of line circuit elements to increase the speed of the rising edge of the clock signal through the buffer and a second one of the at least two alternate plane transistors is operable to selectively activate or deactivate a second one of the at least two remedial front end of line circuit elements to increase the speed of the falling edge of the clock signal through the buffer”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 4 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 6 is the inclusion of “wherein the redundant remedial front end of line circuit element further comprises an additional strengthening buffer for an input/output signal”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 6 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 20 is the inclusion of “wherein the at least one remedial front end of line circuit element comprises a clock buffer and the dynamic signal is provided by a clock management system including at least one of a phase locked loop and a delay lock loop”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 20 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 21 is the inclusion of “wherein the at least one remedial front end of line circuit element comprises a decoupling capacitor”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 21 allowable over the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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16 March 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853