Prosecution Insights
Last updated: July 17, 2026
Application No. 18/425,927

Verify Public Keys by Devices without Secrets for the Generation of Respective Private Keys

Final Rejection §102
Filed
Jan 29, 2024
Priority
Mar 21, 2023 — provisional 63/491,336
Examiner
ABEDIN, SHANTO
Art Unit
2494
Tech Center
2400 — Computer Networks
Assignee
Micron Technology Inc.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
569 granted / 652 resolved
+29.3% vs TC avg
Strong +23% interview lift
Without
With
+23.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
11 currently pending
Career history
662
Total Applications
across all art units

Statute-Specific Performance

§101
4.7%
-35.3% vs TC avg
§103
62.8%
+22.8% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 652 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This is in response to the communication filed on 04/21/2026. Claims 1-20 are pending in the application. Claims 2-10, 12-16 and 18-20 are objected. Claims 1, 11 and 17 are rejected. Response to Arguments Applicant’s arguments, see pages 3 and 4 of remarks, filed on 04/21/2026 with respect to the rejections under 35 U.S.C. 102 (a)(2) have been fully considered, and found persuasive. Previous 35 U.S.C. 102 (a)(2) type rejections of claims 12-15 and 18-19 have been withdrawn. Previous 35 U.S.C. 102 (a)(2) type rejections of claims 1, 11 and 17 are maintained for the following reasons: Regarding previous 35 USC 102 (a)(2) type rejections, applicant primarily argues that DOLIWA et al. reference fails to disclose “generating an asymmetric cryptographic key pair in a device in a way that enables an external system to verify the correctness of the public key in the key pair without the need to provide the external system with access to the private key in the key pair and/ or the secrets used in the generation of the private key” (See page 4 of remarks filed on 04/21/2026) In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., an external system to verify the correctness of the public key in the key pair without the need to provide the external system with access to the private key in the key pair and/ or the secrets used in the generation of the private key) are not recited in the independent claims 1, 11 and 17. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 11 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2019/0052464 A1 (hereinafter DOLIWA et al.) Regarding claim 1, DOLIWA et al. teaches a method, comprising: securing, in a computing device, a secret in a read-only memory (note para. [0012], [0017]: secure, non-volatile memory for storing secret key for key derivation); generating, by the computing device using the secret, a first key pair having a first public key and a first private key, wherein the first public key is obtainable from the first private key via a first operation (note para. [0012], [0017]: generating first key pair from shared secret); communicating, by the computing device over a computer network, with a system to obtain a component containing instructions executable in the computing device (note para. [0012], [0015]: storing key derivation/ generating product specific parameters (PSP), instructions/ firmware etc.); computing, by the computing device, an intermediate key using information about the component installed in the computing device (note para. [0015], [0021]: generating product specific parameters/ keys, intermediate values); combining, by the computing device, the intermediate key and the first private key via a second operation to generate a second private key in a second key pair having a second public key obtainable from the second private key via the first operation (note para. [0012], [0020] –[0022], [0028]: combining firmware signature verification key (FSK) with DH values to generate additional private keys; generating second/ additional public- private key pairs using intermediate Diffie-Hellman values) Regarding claim 11, DOLIWA et al teaches a computing device (note para. [0010], [0012]: IC manufacturing environment 10) comprising: a communication device (note para. [0012], [0014]: IoT devices in network); and a processor (note para, [0012] – [0013]: CPU/ processor in IC card) configured to: generate an intermediate key from inputs (note para. [0015], [0021]: generating product specific parameters/ keys, intermediate values); combine the intermediate key with a first private key to generate a second private key (note para. [0012], [0020] – [0022], [0028]: combining firmware signature verification key (FSK) with DH values to generate private keys); compute a second public key of the second private key (note para. [0012], [0020] – [0022], [0028]: generating second/ additional public- private key pairs using intermediate Diffie-Hellman values) Regarding claim 17, DOLIWA et al teaches a server system (note para. [0010], [0012]: IC manufacturing environment 10), comprising: a memory (note para. [0012], [0014]: secure memory) configured to store a component and a first public key of a computing device; a communication device (note para. [0012], [0014]: IoT devices in network); and a processor (note para, [0012] – [0013]: CPU/ processor in IC card) configured to: communicate, using the communication device, the component to the computing device to cause installation of the component in the computing device (note para. [0012], [0015]: storing key derivation/ generating product specific parameters (PSP), instructions/ firmware etc.), wherein the computing device is configured to compute a second key pair, including a second private key and a second public key, from a first private key associated with the first public key in a first key pair (note para. [0012], [0020] – [0022], [0028]: combining firmware signature verification key (FSK) with DH values to generate additional private keys; generating second/ additional public- private key pairs using intermediate Diffie-Hellman values); receive, from the computing device, the second public key (note para. [0021], [0028]) Allowable Subject Matter Claims 2-10, 12-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHANTO ABEDIN whose telephone number is 571-272-3551. The examiner can normally be reached on M-F from 8:30 AM to 6:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jung (Jay) Kim, can be reached on 571-272-3804. The RightFax number for faxing directly to the examiner is 571-273-3551. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /SHANTO ABEDIN/ Primary Examiner, Art Unit 2494
Read full office action

Prosecution Timeline

Jan 29, 2024
Application Filed
Nov 07, 2025
Response after Non-Final Action
Jan 21, 2026
Non-Final Rejection mailed — §102
Apr 21, 2026
Response Filed
Jun 29, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+23.3%)
3y 1m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 652 resolved cases by this examiner. Grant probability derived from career allowance rate.

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