DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Under Step 1 of the 2019 Revised Patent Subject Matter Eligibility Guidance, the claims are directed to a process (claim 1, a method) or a machine (claim 11, a system, claim 14), which are statutory categories.
However, evaluating claim 1, under Step 2A, Prong One, the claim is directed
to the judicial exception of an abstract idea using the grouping of a mathematical relationship/mental process. The limitations include:
determining a sheet resistance of a base layer of a bipolar junction transistor (BJT); estimating a quiescent current based on the sheet resistance of the base layer; and rejecting a power amplifier die based on the quiescent current not satisfying a threshold level.
The claim recites a mathematical concept because it recites determining a sheet resistance of a base layer of a bipolar junction transistor (BJT); estimating a quiescent current based on the sheet resistance of the base layer, and determining whether the estimated quiescent current satisfies a threshold. Estimating quiescent current from sheet resistance necessarily requires applying a mathematical relationship or correlation between those parameters, and comparing the estimated value to a threshold constitutes a mathematical evaluation. The claim also recites a mental process because, once the sheet resistance is known and the correlation is available, a person could mentally or with pencil and paper estimate the quiescent current, compare it to a threshold, and determine whether the die should be accepted or rejected.
Accordingly, the claim recites the abstract ideas of mathematical concepts and mental processes.
Next, Step 2A, Prong Two evaluates whether additional elements of the claim “integrate the abstract idea into a practical application” in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the exception. The claim does not recite additional elements that integrate the judicial exception into a practical application.
The recitation of a bipolar junction transistor (BJT), a base layer, and power amplifier die merely identifies the technological environment in which the mathematical analysis is performed. The claim does not recite any improvement to a transistor structure, semiconductor fabrication process, probe station, sheet resistance measurement technique, or any other technological process. Rather, the additional elements merely collect conventional manufacturing data (sheet resistance), apply a mathematical correlation to estimate another electrical parameter (quiescent current), compare the estimated value with a threshold, and use the result to make a quality-control decision. The final step of rejecting the power amplifier die merely applies the result of the abstract analysis in a conventional manufacturing workflow and constitutes insignificant post-solution activity. Thus, the claim does not improve the functioning of a computer, semiconductor device, measurement apparatus, or any other technology, but instead merely uses mathematical analysis to support a manufacturing decision.
Therefore, the claim is directed to an abstract idea.
At Step 2B, consideration is given to additional elements that may make the abstract idea significantly more. Under Step 2B, there are no additional elements that make the claim significantly more than the abstract idea.
The additional elements, considered individually and as an ordered combination, merely require determining a conventional electrical parameter (sheet resistance), applying a mathematical relationship to estimate quiescent current, comparing the estimate with a threshold, and rejecting a dies based on the comparison. These are well-understood, routine, and conventional activities in semiconductor manufacturing and quality control. The ordered combination likewise does not improve any underlying measurement technology or manufacturing equipment, but merely uses conventional data collection followed by mathematical analysis to support a conventional pass/fail manufacturing decision.
Accordingly, the additional elements do not transform the judicial exception into patent-eligible subject matter.
Therefore, claim 1 is directed to patent-ineligible subject matter under 35 U.S.C. § 101.
Dependent claims 2-10 do not render the claims patent eligible because the additional limitations merely further define the environment in which the abstract mathematical analysis is performed or add extra mathematical calculations and conventional semiconductor manufacturing activities. Specifically, performing the rejection during probe testing (claim 2), limiting the device to an HBT or GaAs HBT (claims 3-4), specifying that the estimated current is collector quiescent current (claim 5), determining resistance from measured voltage and current and normalizing the resistance by device geometry (claims 6-7), determining transistor beta from sheet resistance and using a linear relationship or linear regression (claims 8-9), and estimating quiescent current using a base-current resistor (claim 10) merely employing well-understood, routine and conventional semiconductor characterization techniques and additional mathematical relationships. These limitations do not improve the functioning of a computer, manufacturing equipment, or measurement technology, and therefore do not integrate the judicial exception into a practical application or provide an inventive concept sufficient to amount to significantly more than the abstract idea.
Claim 11 is rejected 35 USC § 101 for the same rationale as in claim 1.
The additional elements of “a processor” and “a memory” are recited at a high level of generality and are recited as performing generic computer functions routinely used in computer applications. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system (Alice Corp. Pty. Ltd. v. CLS Bank Int’l 573 U.S. __, 134 S. Ct. 2347, 110 U.S.P.Q.2d 1976 (2014)).
The limitations have been considered individually and as a whole and do not amount to significantly more than the abstract idea itself.
Dependent claims 12-19 do not render the claims patent eligible because the additional limitations merely further define the environment in which the abstract mathematical analysis is performed or add extra mathematical calculations and conventional semiconductor manufacturing activities. Specifically, performing the rejection during probe testing (claim 12), limiting the device to an HBT or GaAs HBT (claims 13-14), specifying that the estimated current is collector quiescent current (claim 15), determining resistance from measured voltage and current and normalizing the resistance by device geometry (claims 16-17), determining transistor beta from sheet resistance (claim 18), and estimating quiescent current using a base-current resistor (claim 19) merely employing well-understood, routine and conventional semiconductor characterization techniques and additional mathematical relationships. These limitations do not improve the functioning of a computer, manufacturing equipment, or measurement technology, and therefore do not integrate the judicial exception into a practical application or provide an inventive concept sufficient to amount to significantly more than the abstract idea.
Claim 20 is considered eligible under 35 USC § 101, because when considered
as a whole, it is directed to a specific semiconductor apparatus rather than to a judicial exception. Specifically, the claim recites a sheet resistance determination module including a packaging substrate, a power amplifier die implemented on the packaging substrate, a bipolar junction transistor (BJT), a voltage supply pad coupled to a first location of the transistor base, and a measurement pad coupled to a second location of the transistor base. These limitations define a particular structure arrangement of physical components configured to perform an electrical measurement on the transistor. Although the claim recites that the measurement pad is configured to measure a second voltage corresponding to the first voltage minus a resistance multiplied by a base current, this language merely describes the physical electrical relationship of the measured voltage within the claimed circuit and does not recite a mathematical calculation performed by a processor or mental process. Accordingly, the claim is not directed to an abstract idea under Step 2A, Prong One of the 2019 Revised Patent Subject Mater Eligibility Guidance. Instead, the claim is directed to a concrete semiconductor device having a specific arrangement of structural elements that performs a technological function within the field of semiconductor testing. Therefore, claim 20 is directed to patent-eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-18 are rejected under 35 U.S.C. 103 as being unpatentable
over Welser et al. (Pub. No. US 2002/0163014) (hereinafter Welser) in view of Mahon et al. (Pub. N. US 2019/0078941) (hereinafter Mahon) and further in view of Zampardi et al. (NPL: “Practical statistical simulation for efficient circuit design” (hereinafter Zampardi).
As per claims 1, 3-5, 11 and 13-15, Welser teaches a heterojunction bipolar transistor (HBT) including a base layer having a base sheet resistivity and teaches that the base layer is suitable for gallium arsenide (GaAs)-based HBT power amplifiers (see Abstract and ¶¶ [0002]-[0005]). Welser further teaches that transistor DC current gain (β) is correlated with base sheet resistance. Specifically, ¶ [0086] states that Fig. 16 compares dv current gain as a function of base sheet resistance”, demonstrating that transistor β is determined from a correlation with base sheet resistance. ¶ [0061] further provide measured examples of base sheet resistivity and corresponding DC current gain values thereby establishing the relationship between sheet resistance and transistor β.
However, Welser fails to explicitly disclose how the sheet resistance is determined.
Mahon, however, teaches determining sheet resistance by electrically measuring resistance of the HBT based structure. Specifically, ¶ [0049] teaches four-terminal Kelvin resistance measurement using separate current-force and voltage-sense terminals. ¶ [0052] teaches applying a probe current, measuring the resulting voltage, and determining resistance from the measured voltage and current, stating that “From the measured voltages VS and known value of applied current IP, a resistance value RS can be determined”. ¶ [0072] further teaches determining sheet resistance (Ohms/square) from the measured resistance. Thus, Mahon teaches determining the sheet resistance of the HBT based layer using voltage and current measurements as recited.
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to employ the Kelvin sheet-resistance measurement technique of Mahon in the HBT process characterization methodology of Welser because Mahon provides an accurate and manufacturable technique for determining the base-layer sheet resistance used by Welser to characterize transistor current gain, thereby enabling reliable extraction of the process parameter used for transistor characterization.
Neither Welser nor Mahon explicitly teaches estimating quiescent current based upon the measured sheet resistance.
Zampardi teaches statistical simulation of III-V HBT power amplifiers using process control monitor (PCM) parameters (see pages 287-290). Zampardi teaches that the base properties dominate transistor characteristics and explains that the base doping substantially affect both transistor DC current gain (β) and base sheet resistance (Rbsh) (see page 293). Zampardi further teaches that “β and Rbsh are linearly related to one another (slope = 1.06)” (see page 294), and further explains that “knowing Rb or β implies the other” (see page 295). Zampardi also teaches using these correlated process parameters in statistical models for power amplifiers, validating the models against production data, and demonstrating that “the simulation can quite reasonably track the Icq variations resulting from the controlled variations (see page 305). Zampradi further teaches that the methodology is directed toward improving manufacturing yield, refining process control monitors, determining acceptable material specifications, validating production, and eliminating unacceptable circuit topologies (see page 288).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to employ the statistical modeling methodology of Zampradi using the measured sheet resistance and correlated transistor β because Zampradi explicitly teaches that base sheet resistance and transistor β are correlated process-control parameters that are used to predict quiescent current (Icq) and evaluate power-amplifier performance variation for yield improvement and process validation, thereby enabling prediction of whether a power-amplifier die will satisfy predetermined quiescent-current specifications before subsequent manufacturing operations.
It would also have been obvious to reject, or otherwise classify as failing, a power-amplifier die whose predicted quiescent current does not satisfy the required specification because Zampradi teaches using process-control monitor data and predicted circuit performance to improve yield, establish acceptable material specifications, and eliminate unacceptable performance resulting from process variation, thereby avoiding further processing of dies predicted to fall outside acceptable quiescent-current limits and improving manufacturing yield and reducing production cost.
Regarding a processor and memory (claim 11) (see Zampardi, page 295, Figures 9.3, 9.4 and “database”).
As per claims 2 and 12, the combination of Welser, Mahon and Zampardi teaches the system as stated above. Mahon further teaches further teaches obtaining the sheet-resistance measurement while testing or qualifying semiconductor devices during manufacture (see ¶ [0068]) and Zampardi teaches using those manufacturing measurements for production validation, yield improvement, and prediction of power-amplifier performance (see pages 297 and 305).
As per claims 6 and 16, the combination of Welser, Mahon and Zampardi teaches the system as stated above. Mahon further teaches determining the sheet resistance of the HBT base layer using a four-terminal Kelvin measurement. Specifically, ¶ [0049] teaches separate current -force and voltage-sense contact terminals connected to resistive base structure for Kelvin resistance measurements. ¶ [0052] further teaches applying a probe current (IP), measuring the resulting voltage (VS), and determining the resistance therefrom, stating: “From the measured voltage VS and known value of applied current IP, a resistance value RS can be determined”. Thus, Mahon explicitly teaches providing current-supply and voltage-measurement terminals connected to the base layer, measuring the voltage drop and current, and determining resistance by dividing the measured voltage by the applied current, as recited in claim 6. The combination therefore discloses all the limitations of claim 6.
As per claims 7 and 17, the combination of Welser, Mahon and Zampardi teaches the system as stated above. Although Mahon does not explicitly state that the measured resistance is divided by the aspect ratio of the resistive base region, it would have been obvious to do so because sheet resistance is conventionally defined as the resistance of a thin film normalized by its value that accurately characterizes the base material irrespective of the dimensions of the test structure.
As per claims 8 and 18, the combination of Welser, Mahon and Zampardi teaches the system as stated above. The combination fails to explicitly teach wherein the estimating the quiescent current further comprises determining a transistor beta for the BJT based on a correlation between the transistor beta and the sheet resistance.
However, it would have been obvious to employ the β-to-sheet-resistance correlation of Welser in the statistical prediction methodology of Zampardi because Zampardi teaches that β and base sheet resistance are correlated process-control parameters used to predict power amplifier quiescent current, thereby enabling estimation of quiescent current from measured sheet resistance.
As per claim 9, the combination of Welser, Mahon and Zampardi teaches the system as stated above. The combination fails to explicitly teach determining the disclosed correlation using linear regression. However, it would have been obvious to determine the disclosed linear relationship using linear regression because linear regression is the standard statistical technique used to derive the equation of a linear relationship from measured process-control data, thereby the predictive correlation between transistor β and base sheet resistance for subsequent quiescent-current estimation.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Welser in
view of Mahon.
As per claim 20, Welser teaches a sheet resistance determination structure associated with a power amplifier die. Specifically, Welser teaches a gallium arsenide (GaAs)-based heterojunction bipolar transistor (HBT) power amplifier including a base layer whose sheet resistance is measured and correlated with transistor characteristics (Abstract; ¶¶ [0002]-[0005], [0061], [0086]). Since an HBT is a bipolar junction transistor (BJT), Welser teaches a power amplifier comprising a BJT implemented on a power amplifier die.
Welser, however, does not expressly disclose a voltage supply pad and a measurement pad configured for determining the sheet resistance of the transistor base.
Mahon teaches a four-terminal Kelvin measurement structure for determining the resistance and sheet resistance of the base layer of a bipolar transistor. Specifically, ¶ [0049] teaches sperate current-force terminals and voltage-sense terminals coupled to the resistive base region of the transistor. ¶ [0052] further teaches applying a probe current through one terminal pair, measuring the resulting voltage at another terminal pair, and determining the resistance therefrom, stating. “From the measured voltage VS and known value of applied current IP, a resistance value RS cam be determined.” ¶ [0072] further teaches determining the sheet resistance of the transistor base from the measured resistance. Accordingly, Mahon teaches a voltage supply pad coupled to a first location of the transistor base for applying a voltage and a measurement pad couple to a second location of the transistor base for measuring the resulting voltage.
Neither Welser nor Mahon expressly states that the voltage measured at the second location of the base is equal to the applied first voltage minus the product of the base resistance and the base current. However, it would have been obvious to one of ordinary skill in the art that the voltage measured at the second location of the resistive base region is equal to the voltage applied at the first location minus the voltage drop across the intervening base resistance because Ohm’s law dictates that the voltage drop across a resistive element is equal to the current flowing through the element multiplied by its resistance (V=IR), thereby allowing the second voltage at the measurement pad to correspond to the first voltage minus the product of the base resistance and the base current during sheet resistance measurement.
It would have been obvious to incorporate the Kelvin measurement structure of Mahon into the HBT power amplifier die of Welser because Mahon provides an accurate and well-established technique for measuring the resistance and sheet resistance of the transistor base, thereby enabling characterization of the HBT base layer for the power amplifier disclosed by the Welser.
Regarding the recitation of a packaging substrate, it would have been obvious the implement the power amplifier die of Welser on a conventional packaging substrate because semiconductor power amplifier dies are routinely mounted on package substrates to provide electrical interconnection, mechanical support, and thermal dissipation, thereby enabling normal packaging and operation of the power amplifier device.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable
over Welser in view of Mahon and further in view of Zampardi and Pennisi (NPL: “LOW-VOLTAGE CMOS CURRENT OPERATIONAL AMPLIFIER WITH CLASS AB INPUT STAGE”.
As per claims 10 and 19, the combination of Welser, Mahon and Zampardi teaches the system as stated above. The combination fails to explicitly teach that wherein the estimating the quiescent current further comprises dividing the sheet resistance with a resistor configured to provide a base current to the BJT.
However, Pennisi teaches that “the quiescent current of MI (M2) is accurately controlled by a resistance ratio and is given by (RB/R1)I1 (see page 1526, col. 2, first paragraph). It would have been obvious to estimate the collector quiescent current using the ratio of the measured base resistance (derived from the sheet resistance) and the bias resistor of the transistor because Pennisi teaches that quiescent current is accurately determined by a resistance ratio, IQ = (RB/R1)I1, while Welser and Zampardi teach that the base resistance (or sheet resistance) is correlated with transistor β and quiescent current, thereby providing a predictable technique for estimating the quiescent current of a power-amplifier transistor from measured base resistance and the bias resistor.
Prior art
The prior art made record and not relied upon is considered pertinent to applicant’s
disclosure:
Kim [‘323] discloses fabrication of a germanium tin (GeSn) based heterojunction bipolar transistor and/or light emitting transistor or transistor laser or light emitting device or laser for electronics and photonics is described herein. Where GeSn is used as the base material in a heterojunction transistor, the GeSn, GeSn quantum dot, GeSn quantum wire, and/or GeSn quantum dot material can be used as the active region of a light emitting transistor or transistor laser or light emitting device or laser. In one embodiment, a heterojunction bipolar transistor includes a GeSn base region.
Malik [‘’670] discloses a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an "H-shaped" dielectric (i.e., Si.sub.3N.sub.4/SiO.sub.- 2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si.sub.3N.sub.4 and/or SiO.sub.2, for reliable HBT emitter p-n junction passivation. Thus, the disclosed HBT process enables scaling of narrow emitter stripe widths down to sub-micron dimensions producing transistors with cut-off frequencies in the range of several hundred GigaHertz.
Contact information
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to MOHAMED CHARIOUI whose telephone number is (571)272-2213. The examiner can normally be reached Monday through Friday, from 9 am to 6 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Schechter can be reached on (571) 272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Mohamed Charioui
/MOHAMED CHARIOUI/Primary Examiner, Art Unit 2857
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