DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are acceptable for the purposes of examination.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 10-15 and 22 are objected to under 37 CFR 1.75(a) for failing to particularly point out and distinctly claim the subject matter which the applicant regards as his invention or discovery.
Claim 10 recites “based determining that the value”. This should be “based on determining that the value”.
In claim 10 line 4, the comma should be removed.
Dependent claims are objected to for the same reasons.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 4 and 12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 recites “decode the third instruction, including: set the value of the counter register to the specified value based on decoding the second instruction”. There does not appear to be support for decoding of the third instruction to include setting the value of the counter register to the specified value based on decoding the second instruction.
Claim 4 recites “decode the second instruction, including: treat the third instruction as a no operation”. There does not appear to be support for decoding of the second instruction to include treating the third instruction as a no operation.
Claim 12 recites “adjusting the value of the counter register includes incrementing the value of the counter register”. Claim 10 recites “setting a value in the counter register based on a count indicated by the first instruction”. There does not appear to be support for setting a value in the counter register based on a count indicated by the instruction and incrementing the value of the counter register. From paragraph 48, the counter is set to zero and incremented.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “execute service the interrupt”. It is not clear what this means. Examiner is interpreting as “service the interrupt”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer et al (6,237,089 B1, herein Moyer) and further in view of Magoshi (US 2003/0182541 A1).
Regarding Claim 1, Moyer teaches a processor comprising:
a decoder (Fig. 2 32), an interrupt controller communicatively coupled with the decoder (Fig. 2 46), and a counter (Fig. 2 48) communicatively coupled with the decoder and the interrupt controller (Fig. 2), wherein the decoder is configured to:
receive a first instruction that includes a counter field (Column 4 lines 59-63);
decode the first instruction (Fig 2);
and wherein the interrupt controller is configured to pause servicing interrupts (Column 4 lines 53-61, Column 5 lines 5-26).
Under the interpretation that a register is small storage inside a CPU, the counter in Fig. 2 of Moyer is a register. Alternatively, Moyer teaches storing data in a register (Fig. 2). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to store the counter value in a register. This would merely be the simple substitution of one known element for another, and the rationale may support a conclusion of obviousness (See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Though Moyer teaches a counter to determine how many instructions have been executed immediately subsequent to execution of the delay interrupt recognition instruction (Column 5 lines 22-27), Moyer does not explicitly teach setting a value in the counter register based on the count field and adjusting the value in the counter register based on decoding a second instruction. Moyer also does not explicitly teach that the interrupt controller pauses servicing interrupts while the value is different from a specified value.
Magoshi teaches using a counter to count the number of instructions following a particular instruction (Fig. 4). The counter is set to a value based on the number of instructions to skip and the counter decrements with each instruction until it reaches a specified value (Fig. 4).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the counter in Moyer by decrementing it as taught by Magoshi. This would result in setting a value in the counter register that indicates the number of instructions which is based on the count field and adjusting the value in the counter register based on decoding a second instruction. This would also result in the interrupt controller pausing servicing interrupts while the value is different from a specified value. This would merely be the simple substitution of one known element over another, and the rationale may support a conclusion of obviousness (See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding Claim 2, Moyer and Magoshi teach the processor of claim 1, wherein the decoder is configured to:
set the value in the counter register to be a non-zero quantity (Magoshi Paragraph 19, The combination teaches storing a non-zero value), wherein the specified value is zero (Magoshi Fig. 4, value of zero); and
decrement the value of the counter register with a subsequently decoded instruction (Magoshi Fig. 4, The combination would decrement the value with a subsequent decoded instruction).
Regarding Claim 5, Moyer and Magoshi teach the processor of claim 2, wherein the interrupt controller is configured to:
receive a first interrupt signal (Moyer Fig. 2);
determine that the value of the counter register is different than the specified value (Magoshi Fig. 4, The combination teaches the counter register being compared to the specified value); and
in response to determining that the value of the counter register is different than the specified value, pause servicing an interrupt indicated by the first interrupt signal (The combination results in the delaying recognition of interrupts thus pausing servicing of interrupts).
Regarding Claim 9, Moyer and Magoshi teach the processor of claim 1, wherein the first instruction is an instance of a machine code instruction within a machine instruction set (Moyer Fig. 3, IDLY4 is a machine code instruction), and wherein the counter register comprises a status register (The combination teaches a counter register. It is a status register as it indicates the status of interrupt/delay of interrupts).
Regarding Claim 21, Moyer and Magoshi teach the processor of claim 1, wherein the specified value is zero (Magoshi Fig. 4).
Claims 6, 10, 11, 13, 16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer, Magoshi and further in view of Gholami et al (US 6,629,252 B1, herein Gholami).
Regarding Claim 6, Moyer and Magoshi teach the processor of claim 5, wherein the interrupt controller is further configured to:
subsequent to determining that the value of the counter register is different than the specified value, determine that the value of the counter register matches the specified value (Magoshi Fig. 4).
Though the combination teaches pending interrupts (Moyer Column 6 lines 46-50), the combination thus far does not explicitly teach servicing the interrupt according to the first interrupt signal.
Gholami teaches servicing an interrupt using an interrupt service routine (Column 1 lines 36-50) and delaying the start of the interrupt service routine (Column 2 lines 30-31).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement servicing the pending interrupt using an interrupt service handler. One of ordinary skill in the art would be motivated to do so as this would allow operations, in response to the interrupt, to be performed.
Regarding Claim 10, Moyer teaches a method comprising:
fetching a first instruction (Fig. 2);
decoding the first instruction (Fig. 2);
a count indicated by the first instruction (Fig. 3);
instructing an interrupt controller to pause servicing interrupts (Column 4 lines 53-61, Column 5 lines 5-26).
Though Moyer teaches a counter to determine how many instructions have been executed immediately subsequent to execution of the delay interrupt recognition instruction (Column 5 lines 22-27), Moyer does not explicitly teach setting a value in a counter register based on the count, pausing servicing interrupts until the value of the counter register matches a specified value, adjusting the value of the counter register based on decoding a second instruction; receiving an interrupt signal while the value of the counter register is different from the specified value; and servicing an interrupt, corresponding to the interrupt signal, based on determining that the value of the counter register matches the specified value.
Magoshi teaches using a counter to count the number of instructions following a particular instruction (Fig. 4). The counter is set to a value based on the number of instructions to skip and the counter decrements with each instruction until it reaches a specified value (Fig. 4).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the counter in Moyer by decrementing it as taught by Magoshi. This would result in setting a value in the counter register based on the count and adjusting the value in the counter register based on decoding a second instruction. This would also result in the interrupt controller pausing servicing interrupts until the value of the counter register matches a specified value. This would also result in receiving an interrupt signal while the value of the counter register is different from the specified value. This would merely be the simple substitution of one known element over another, and the rationale may support a conclusion of obviousness (See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
The combination thus far does not explicitly teach servicing an interrupt, corresponding to the interrupt signal, based on determining that the value of the counter register matches the specified value.
Gholami teaches servicing an interrupt using an interrupt service routine (Column 1 lines 36-50) and delaying the start of the interrupt service routine (Column 2 lines 30-31).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement servicing the pending interrupt using an interrupt service handler. This would result in the aforementioned limitation. One of ordinary skill in the art would be motivated to do so as this would allow operations, in response to the interrupt, to be performed.
Regarding Claim 11, Moyer, Magoshi and Gholami teach the method of claim 10, further comprising:
decoding multiple subsequent instructions and adjusting the value of the counter register with each subsequent instruction decoded (Magoshi Fig. 4, The combination would decrement the value with subsequent decoded instructions)
Regarding Claim 13, Moyer, Magoshi and Gholami teach the method of claim 10, wherein servicing the interrupt based on determining that the value of the counter register matches the specified value comprises:
delaying servicing the interrupt;
while delaying servicing the interrupt, monitoring the counter register; and
servicing the interrupt in response to determining that the value of the counter register matches the specified value (Magoshi Fig. 4, The combination teaches the delaying and servicing when the counter matches the specified value).
Claim 16 is rejected for the same reasons as claim 10. Claim 16 further requires a non-transitory computer readable medium storing a computer program comprising sets of computer readable instructions for execution by a computer processor, wherein the computer program is such that, when the sets of computer readable instructions are executed by the processor, the processor is caused to perform the steps. The IDLY4 instruction and other Instructions are stored in memory thus the combination teaches this limitation.
Regarding Claim 22, Moyer, Magoshi and Gholami teach the method of claim 10, wherein the specified value is zero (Magoshi Fig. 4).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable Moyer and Magoshi as applied to claim 5 above, and further in view of Laurenti et al (US 6,658,578 B1, herein Laurenti).
Regarding Claim 7, Moyer and Magoshi teach the processor of claim 5, wherein the interrupt controller is further configured to:
subsequent to determining that the value of the counter register is different than the specified value, determine that the value of the counter register matches the specified value (Magoshi Fig. 4).
The combination thus far does not teach checking an interrupt enable flag in response to the first interrupt signal representing a maskable interrupt; and
executing an interrupt service routine in response to determining that the interrupt enable flag indicates that interrupts are enabled.
Laurenti teaches servicing a maskable interrupt with an interrupt service routine (Column 120 lines 21-24, Column 121 lines 21-39) only if the interrupt enable bit is set (Column 124 lines 35-44).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the servicing of maskable interrupts based on the interrupt enable bit being set. This would result in the aforementioned limitation. One of ordinary skill in the art would be motivated to do so as this would allow masking of certain interrupts and allow processing of functions in response to the interrupt.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Moyer and Magoshi as applied to claim 5 above, and further in view of Metcalf (US 8,327,187) and Laurenti.
Regarding Claim 8, Moyer and Magoshi teach the processor of claim 5, wherein the interrupt controller is further configured to:
subsequent to determining that the value of the counter register is different than the specified value, determine that the value of the counter register matches the specified value (Magoshi Fig. 4, the counter matches 0 subsequently); and
The combination thus far does not explicitly teach executing an interrupt service routine, regardless of a state of an interrupt enable flag, in response to the first interrupt signal representing a real-time interrupt.
Metcalf teaches locking out interrupts for read-modify-write operations (Column 30 lines 57-67).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to lock out all interrupts for read-modify-write operations. One of ordinary skill in the art would be motivated to do so as this would prevent deadlocks (Column 30 lines 57- Column 31 line 3).
The combination thus far does not explicitly teach executing an interrupt service routine, regardless of a state of an interrupt enable flag, in response to the first interrupt signal representing a real-time interrupt.
Laurenti teaches executing an interrupt service routine, regardless of a state of an interrupt enable flag, in response to a real-time interrupt (Column 120 lines 21-24, Column 124 lines 40-44).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the first interrupt as a real-time interrupt and executing of an interrupt service routine in response to real-time interrupt regardless of interrupt enable flag. One of ordinary skill in the art would be motivated to do so as this would allow handling of critical failures and also prevent disabling of such interrupts. An interrupt service routine would allow the handling of the interrupt by appropriate procedures.
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer, Magoshi and Gholami, and further in view of Metcalf.
Regarding Claim 14, Moyer, Magoshi and Gholami teach the method of claim 10.
The combination does not explicitly teach that the interrupt is a real- time interrupt.
Metcalf teaches locking out interrupts for read-modify-write operations, even non-maskable interrupts (Column 30 lines 57-67).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to lock out all interrupts including non-maskable interrupts. This would result in the aforementioned limitation.
One of ordinary skill in the art would be motivated to do so as this would prevent deadlocks (Metcalf Column 30 lines 57- Column 31 line 3).
Claim 18 is rejected for the same reasons as Claim 14.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer, Magoshi and Gholami, and further in view of Laurenti
Regarding Claim 15, Moyer, Magoshi and Gholami teach the method of claim 10.
The combination thus far does not explicitly teach that the interrupt comprises is a maskable interrupt, the method further comprising:
determining that interrupts are enabled; and
servicing the interrupt at least in part in response to determining that interrupts are enabled.
Laurenti teaches servicing a maskable interrupt with an interrupt service routine (Column 120 lines 21-24, Column 121 lines 21-39) only if the interrupt enable bit is set (Column 124 lines 35-44).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the servicing of maskable interrupts based on the interrupt enable bit being set. This would result in the aforementioned limitation. One of ordinary skill in the art would be motivated to do so as this would allow masking of certain interrupts and allow processing of functions in response to the interrupt.
Claim 17 is rejected for the same reasons as claim 15.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Moyer, Magoshi and Gholami as applied to claim 16 above, and further in view of Boles et al (US 6,985,986 A1, herein Boles).
Regarding Claim 19, Moyer, Magoshi and Gholami teach the non-transitory computer readable medium of claim 16 that the value in the counter register is non-zero and the specified value is zero (Magoshi Fig. 4).
The combination thus far does not explicitly teach that the medium further comprising computer readable instructions to cause the processor to: decode an instruction that specifies that the value of the counter register be set to zero; and set the count value of the counter register to zero in response to the instruction.
Boles teaches using a counter to disable interrupts and an instruction to cause the counter register to set the value to zero (Column 6 lines 53-62).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an instruction to set the value of the counter to zero. One of ordinary skill in the art would be motivated to do so terminate the interrupt disable as needed and also to subsequently set to another value.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Moyer, Magoshi and Gholami as applied to claim 16 above, and further in view of Official Notice.
Regarding Claim 20, Moyer, Magoshi and Gholami teach the non-transitory computer readable medium of claim 16, wherein the specified value is non-zero (Magoshi Paragraph 19, 20; In other words, the counter would increment to a non-zero value), the medium further comprising computer readable instructions to cause the processor to:
decode subsequent instructions and increment the value of the counter register with a subsequent instruction decoded (The combination teaches the incrementing with a subsequent instruction).
The combination thus far does not explicitly teach that the value in the counter register is zero.
Examiner takes official notice that counter can start counting from zero.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the counter to start counting from zero. This would result in the value in the counter being zero. This would merely be the simple substitution of one known element for another and the rationale may support a conclusion of obviousness (See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Response to Arguments
The Applicant’s arguments, filed 4/2/2026, have been fully considered.
The Applicant’s argument, on page 8, that the claims comply with the written description requirement, is not persuasive (See rejections above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jyoti Mehta whose telephone number is (571)270-3995. The examiner can normally be reached on Monday-Friday 8 am-4 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571) 272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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