DETAILED ACTION
This Office Action is in response to Amendment filed on 28 January 2026.
Claims 1, 3-9, 11, and 13-20 are pending. Claims 2, 10, and 12 are canceled. The pending claims have been considered and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 11, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 10, 15, and 16 of U.S. Patent No. 10,235,229 in view of Lesartre et al, U.S. Patent App. Pub. 2016/0147620, hereinafter referred to as “Lesartre” and in view of Lee, “U.S. Patent App. Pub. 2016/0179617, hereinafter referred to as “Lee”.
Claims 1-3, 10, 15, 16 of ‘229 contain every element of claim 1, 11, and 20 of the instant application except for “a storage device that provides persistent storage” and “the second rehabilitative action on the storage device that avoids relocating data from the storage device”.
Although claim 20 of the instant application is directed to a computer program product claim, and claims 1-3 of ‘229 are directed toa method claim, a computer program product claim is merely an alternative embodiment of a method claim.
Claim 1 of the instant application maps to claims 1-3 of ‘229.
Claim 11 of the instant application maps to claims 10, 15, and 16 of ‘229.
Claim 20 of the instant application maps to claims 1-3 of ‘229.
Lesartre discloses data storage that includes persistent main memory (See Lesartre, paragraph 0008). Lesartre discloses the persistent main memory can be DRAM with battery backup or other times of non-volatile RAM (See Lesartre, paragraph 0014).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage devices of ‘229 with the persistent main memory of Lesartre. This would have been obvious to do because new architectures take advantage of using persistent memory devices that provide densities like flash memory and access times like DRAM memories (See Lesartre, paragraph 0011).
Lee discloses a method for operation of a semiconductor memory (See Lee, paragraph 0020). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes (See Lee, paragraphs 0020 and 0098). Lee discloses when the second ECC decoding is success the data is provided to the host, thus being read from the memory and not relocated (See Lee, paragraph 0097).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage device of ‘229 with the second higher level ECC decoding that does not relocate the data of Lee. This would have been obvious to do because the second ECC can improve the reliability of the data read (See Lee, paragraph 0003).
Claims 1, 11, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 9, and 14 of U.S. Patent No. 10,963,326 in view of Lesartre et al, U.S. Patent App. Pub. 2016/0147620, hereinafter referred to as “Lesartre” and in view of Lee, “U.S. Patent App. Pub. 2016/0179617, hereinafter referred to as “Lee”.
Claims 1, 2, 9, 14, and 15 of ‘326 contain every element of claim 1, 11, and 20 of the instant application except for “a storage device that provides persistent storage” and “the second rehabilitative action on the storage device that avoids relocating data from the storage device”.
Although claim 20 of the instant application is directed to a computer program product claim, and claims 1-3 of ‘326 are directed to a method claim, a computer program product claim is merely an alternative embodiment of a method claim.
Claim 1 of the instant application maps to claims 1-2 of ‘326.
Claim 11 of the instant application maps to claims 9 and 14 of ‘326.
Claim 20 of the instant application maps to claims 1-2 of ‘326.
Lesartre discloses data storage that includes persistent main memory (See Lesartre, paragraph 0008). Lesartre discloses the persistent main memory can be DRAM with battery backup or other times of non-volatile RAM (See Lesartre, paragraph 0014).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage devices of ‘326 with the persistent main memory of Lesartre. This would have been obvious to do because new architectures take advantage of using persistent memory devices that provide densities like flash memory and access times like DRAM memories (See Lesartre, paragraph 0011).
Lee discloses a method for operation of a semiconductor memory (See Lee, paragraph 0020). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes (See Lee, paragraphs 0020 and 0098). Lee discloses when the second ECC decoding is success the data is provided to the host, thus being read from the memory and not relocated (See Lee, paragraph 0097).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage device of ‘326 with the second higher level ECC decoding that does not relocate the data of Lee. This would have been obvious to do because the second ECC can improve the reliability of the data read (See Lee, paragraph 0003).
Claims 1, 3-8, 11, 13-18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 5, 9, 10-11, 15, and 17 of U.S. Patent No. 11,449,375 in view of Lesartre et al, U.S. Patent App. Pub. 2016/0147620, hereinafter referred to as “Lesartre” and in view of Lee, “U.S. Patent App. Pub. 2016/0179617, hereinafter referred to as “Lee”.
Claims 1, 2, 4, 5, 9, 10-11, 15, and 17 of ‘375 contain every element of claim 1, 3-8, 11, 13-18, and 20 of the instant application except for “a storage device that provides persistent storage” and “the second rehabilitative action on the storage device that avoids relocating data from the storage device”.
Although claim 5 of the instant application is directed to a method claim, and claims 10-11 of ‘375 are directed to an apparatus claim, a method claim is merely an alternative embodiment of an apparatus claim. Although claims 13-14, 18 of the instant application is directed to an apparatus claim, and claims 1-2, 5, 9 of ‘375 are directed to a method claim, an apparatus claim is merely an alternative embodiment of a method claim. Although claim 20 of the instant application is directed to a computer program product claim, and claim 1 of ‘375 is directed to a method claim, a computer program product claim is merely an alternative embodiment of a method claim.
Claim 1 of the instant application maps to claims 1 of ‘375.
Claim 3 of the instant application maps to claim 2 of ‘375.
Claim 4 of the instant application maps to claim 5 of ‘375.
Claim 5 of the instant application maps to claim 10-11 of ‘375.
Claim 6 of the instant application maps to claim 4 of ‘375.
Claim 7 of the instant application maps to claim 1 of ‘375.
Claim 8 of the instant application maps to claim 9 of ‘375.
Claim 11 of the instant application maps to claim 10 of ‘375.
Claim 13 of the instant application maps to claims 1-2 of ‘375.
Claim 14 of the instant application maps to claims 1 and 5 of ‘375.
Claim 15 of the instant application maps to claim 11 of ‘375.
Claim 16 of the instant application maps to claim 15 and 17 of ‘375.
Claim 17 of the instant application maps to claim 10 of ‘375.
Claim 18 of the instant application maps to claim 1 and 9 of ‘375.
Claim 20 of the instant application maps to claim 1 of ‘375.
Lesartre discloses data storage that includes persistent main memory (See Lesartre, paragraph 0008). Lesartre discloses the persistent main memory can be DRAM with battery backup or other times of non-volatile RAM (See Lesartre, paragraph 0014).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage devices of ‘375 with the persistent main memory of Lesartre. This would have been obvious to do because new architectures take advantage of using persistent memory devices that provide densities like flash memory and access times like DRAM memories (See Lesartre, paragraph 0011).
Lee discloses a method for operation of a semiconductor memory (See Lee, paragraph 0020). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes (See Lee, paragraphs 0020 and 0098). Lee discloses when the second ECC decoding is success the data is provided to the host, thus being read from the memory and not relocated (See Lee, paragraph 0097).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage device of ‘375 with the second higher level ECC decoding that does not relocate the data of Lee. This would have been obvious to do because the second ECC can improve the reliability of the data read (See Lee, paragraph 0003).
Claims 1, 3-9, 11, 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-9, 11, 13-20 of U.S. Patent No. 11,914,455 in view of Lesartre et al, U.S. Patent App. Pub. 2016/0147620, hereinafter referred to as “Lesartre” and in view of Lee, “U.S. Patent App. Pub. 2016/0179617, hereinafter referred to as “Lee”.
Claims 1, 3-9, 11, 13-20 of ‘455 contain every element of claims 1, 3-9, 11, 13-20 of the instant application except for “a storage device that provides persistent storage” and “the second rehabilitative action on the storage device that avoids relocating data from the storage device”.
Claims 1, 3-9, 11, 13-20 of the instant application map respectively to claims 1, 3-9, 11, 13-20 of ‘455.
Lesartre discloses data storage that includes persistent main memory (See Lesartre, paragraph 0008). Lesartre discloses the persistent main memory can be DRAM with battery backup or other times of non-volatile RAM (See Lesartre, paragraph 0014).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage devices of ‘455 with the persistent main memory of Lesartre. This would have been obvious to do because new architectures take advantage of using persistent memory devices that provide densities like flash memory and access times like DRAM memories (See Lesartre, paragraph 0011).
Lee discloses a method for operation of a semiconductor memory (See Lee, paragraph 0020). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes (See Lee, paragraphs 0020 and 0098). Lee discloses when the second ECC decoding is success the data is provided to the host, thus being read from the memory and not relocated (See Lee, paragraph 0097).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the storage device of ‘455 with the second higher level ECC decoding that does not relocate the data of Lee. This would have been obvious to do because the second ECC can improve the reliability of the data read (See Lee, paragraph 0003).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 7-9, 11, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pathirane et al., U.S. Patent App. Pub. 2015/0355962, hereinafter referred to as “Pathirane” in view of Lesartre et al, U.S. Patent App. Pub. 2016/0147620, hereinafter referred to as “Lesartre” and in view of Lee, “U.S. Patent App. Pub. 2016/0179617, hereinafter referred to as “Lee”.
Referring to claim 1, Pathirane discloses a method (See Pathirane, paragraph 0015). - A method comprising:
Pathirane discloses a memory (See Pathirane, paragraph 0004). Pathirane discloses the memory has detected errors (See Pathirane, paragraph 0023). Pathirane discloses the use of error codes to attempt to correct an error (See Pathirane, paragraph 0024). Pathirane discloses retrying access to the memory and once again detecting the correctable error, the same error having been failed to be corrected by the previous ECC (See Pathirane, Fig. 2, paragraph 0027). - determining whether operations of a storage device are outside expected operating parameters after executing a first rehabilitative action for the storage device;
Pathirane discloses determining if the previous error correction failing to correct the error (See Pathirane, Fig. 2, item 30; paragraphs 0027-00028). - in response to determining that the operations are outside the expected operating parameters,
Pathirane does not disclose “that provides persistent storage” and “identifying a second rehabilitative action; and initiating execution of the second rehabilitative action on the storage device that avoids relocating data from the storage device, wherein the storage device continues operations after execution of the second rehabilitative action.”
Lesartre discloses data storage that includes persistent main memory (See Lesartre, paragraph 0008). Lesartre discloses the persistent main memory can be DRAM with battery backup or other times of non-volatile RAM (See Lesartre, paragraph 0014).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the memory with ECC of Pathirane with the persistent main memory of Lesartre. This would have been obvious to do because new architectures take advantage of using persistent memory devices that provide densities like flash memory and access times like DRAM memories (See Lesartre, paragraph 0011).
Lee discloses a method for operation of a semiconductor memory (See Lee, paragraph 0020). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses when the first ECC fails performing a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes (See Lee, Fig. 4, paragraphs 0020 and 0098). Lee discloses when the second ECC decoding is success the data is provided to the host, thus being read from the memory and not relocated (See Lee, paragraph 0097).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the memory with ECC of Pathirane with the second higher level ECC decoding that does not relocate the data of Lee. This would have been obvious to do because the second ECC can improve the reliability of the data read (See Lee, paragraph 0003).
Referring 5, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) including Lee discloses changing the read voltage index for the read group during the second ECC decoding, thus updating data for in regards to the second ECC performed (See Lee, paragraph 0098). - method of claim 1, further comprising: based on initiating execution of the second rehabilitative action, updating information identifying rehabilitative actions performed on the storage device.
Referring to claim 7, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) including Pathirane discloses retrying access and determining if an error exists after the ECC correction is made (See Pathirane, Fig. 2, items 24, 26, and 28; paragraph 0027). - The method of claim 1, wherein determining whether the operations of the storage device are outside the expected operating parameters further comprises: profiling performance of the storage device responsive to completion of the first rehabilitative action.
Referring to claim 8, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) including Pathirane discloses detecting the error a second time indicating a potential hard error, thus the first attempt to correct it failed, the first attempt being a first rehabilitative action (See Pathirane, Fig. 2, items 22 and 28; paragraph 0027). - The method of claim 1, further comprising: determining whether an error has occurred that cannot be corrected by the first rehabilitative action; and
Pathirane discloses determining if the previous error correction failing to correct the error (See Pathirane, Fig. 2, item 30; paragraphs 0027-00028). Lee discloses detecting an error in the memory device and performing a first ECC, and generating a failure signal when the first ECC fails (See Lee, paragraphs 0020-0065). Lee discloses a second ECC decoding, performed in response the first ECC failing, that also includes changing read voltages multiples times along with the ECC decodes (See Lee, Fig. 4, paragraphs 0020 and 0098). - responsive to determining that the error has occurred, selecting the second rehabilitative action.
Referring to claim 9, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) including Lee discloses when the first ECC fails performing a second ECC decoding that also includes changing read voltages multiples times along with the ECC decodes, thus the multiple readings with different voltages further increase latency for the read (See Lee, paragraphs 0020 and 0098). - The method of claim 1, wherein the second rehabilitative action causes greater disruption to operations of the storage device than the first rehabilitative action.
Claims 11, 15, 17, 18 and 19 are rejected for similar reasons as claims 1, 5, 7, 8 and 9, respectively, see above rejections. Additionally, Pathirane discloses an apparatus with a processor executing program instructions stored in a memory (See Pathirane, paragraph 0023).
Claim 20 is rejected for similar reasons as claim 1, see above rejection. Additionally, Pathirane discloses a memory storing instructions for executing by a processor (See Pathirane, paragraph 0023).
Claim(s) 3, 6, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pathirane, Lesartre, and Lee as applied to claims 1 and 11 above, and further in view of Brooker et al., U.S. Patent 2014/0214447, hereinafter referred to as “Brooker”.
Referring to claim 3, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) except for The method of claim 1 further comprising: determining that the storage device is operating outside of a defined range of the expected operating parameters after the second rehabilitative action has been executed; and designating the storage device for replacement. However, Pathirane does disclose the use of replacing part memory with a buffer (See Pathirane, paragraph 0024).
Brooker discloses performing rehabilitation operations of a drive, i.e. a storage device (See Brooker, paragraphs 0010 and 0013). Brooker discloses a sliding scale of health and drive maybe determined less healthy and thus more rehabilitation operations than was previously performed on the drive (See Brooker, paragraphs 0048 and 0059). Brooker discloses a determining a level of rehabilitation that includes a higher number of different rehabilitation operations and if appropriate action is needed, decommissioning storage space and moving the data (See Brooker, paragraphs 0013, 0055, and 0059).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the error correction of memory with multiple corrective actions of Pathirane, Lesartre, and Lee with rehabilitation operations of Brooker. This would have been obvious to do because once it has been determined that a drive has failed, data can be protected from loss by being moved to healthier storage (See Brooker, paragraphs 0014 and 0049).
Referring to claim 6, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) except for The method of claim 1, wherein determining whether the operations of the storage device are outside the expected operating parameters further comprises: profiling input/output ('I/O') performance on the storage device. However, Pathirane does disclose retrying access to determining if the error still exists after the initial ECC correction (See Pathirane, paragraph 0027).
Brooker discloses performing rehabilitation operations of a drive, i.e. a storage device (See Brooker, paragraphs 0010 and 0013). Brooker discloses operational information including read and/or write latencies (See Brooker, paragraph 0017).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the error correction of memory with multiple corrective actions of Pathirane, Lesartre, and Lee with rehabilitation operations of Brooker. This would have been obvious to do because data such as read and write latencies can be used to detect drive failure (See Brooker, paragraph 0017).
24. Claims 13 and 16 are rejected for similar reasons as claims 3 and 6, respectively, see above rejections.
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pathirane, Lesartre, and Lee as applied to claims 1 and 11 above, and further in view of Rosich et al., U.S. Patent 5,574,855, hereinafter referred to as “Rosich”.
Referring to claim 4, Pathirane, Lesartre, and Lee disclose all the limitations (See rejection of claim 1) except for The method of claim 1, further comprising: injecting errors into the storage device; and determining whether the storage device can recover from the errors. However, Pathirane does disclose correcting errors and determining if the corrected errors were actually corrected (See Pathirane, Fig. 27, paragraph 0027).
Rosich discloses testing a storage system with error injection (See Rosich, Col. 1, lines 1-9 and Col. 3, lines 55-58). Rosich discloses testing to see if correctable errors are correctly reconstructed (See Rosich, Col. 2, lines 17-21).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the error correction of memory with multiple corrective actions of Pathirane, Lesartre, and Lee with the error injection of Rosich. This would have been obvious to do because it ensures that the array management functions correctly (See Rosich, Col. 2, lines 17-21).
Claim 14 is rejected for similar reasons as claim 4, see above rejection.
Response to Arguments
Applicant’s arguments, see pages 9-10 of remarks, filed 28 January 2026, with respect to the rejection(s) of claim(s) 1,3-9,11 and 13-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new found prior art, see above rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D MANOSKEY whose telephone number is (571)272-3648. The examiner can normally be reached M-F 7:30am to 3:30pm.
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/JOSEPH D MANOSKEY/Primary Examiner, Art Unit 2113 April 17, 2026
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