DETAILED ACTION
This is the initial Office action based on the preliminary amendment submitted on February 19, 2024.
Claims 1-11 and 13-21 are pending.
Claims 1-11 are currently amended.
Claim 12 is canceled.
Claims 13-21 are added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1-6, 8-11, 13-17, 19, and 20 are objected to because of the following informalities:
Claims 1, 3, 5, 11, 14, 16, and 20 recite “the identifier.” It should read -- the identifier of the program source code --.
Claims 2 and 13 recite “the second quantity.” It should read -- the second quantity of cache misses corresponding to the executable instruction --.
Claims 3, 4, 14, and 15 recite “the prefetch distance.” It should read -- the prefetch distance of the first source code --.
Claim 4 recites “the single loop time value.” It should read -- the single loop time value of the first loop --.
Claims 5 and 16 recite “the CFG.” It should read -- the CFG of the first loop --.
Claims 5 and 16 recite “the third quantity.” It should read -- the third quantity of cache misses of the function --.
Claims 6 and 17 recite “the single loop time value.” It should read -- the single loop time value of the first loop --.
Claims 8 and 19 recite “the structures.” It should read -- the plurality of structures --.
Claims 9 and 20 recite “the order of the members.” It should read -- the order of the members in the structure --.
Claims 9 and 20 recite “the quantities of cache misses.” It should read -- the quantities of the cache misses of the members --.
Claim 10 recites “the quantities of the cache misses.” It should read -- the quantities of the cache misses of the members --.
Claim 14 contains a typographical error: “wherein the first condition comprises comprising” should read -- wherein the first condition comprises --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 16 recite the limitation “the CFG of the second loop.” There is insufficient antecedent basis for this limitation in the claims. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “a CFG of the second loop” for the purpose of further examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,933,643 (hereinafter “Holler”) (cited in the IDS submitted on 01/06/2025) in view of US 2002/0073398 (hereinafter “Tinker”) and US 2021/0019128 (hereinafter “Arai”).
[Examiner’s Remarks: In order for a reference to be proper for use in an obviousness rejection under 35 U.S.C. 103, the reference must be analogous art to the claimed invention. In re Bigio, 381 F.3d 1320, 1325, 72 USPQ2d 1209, 1212 (Fed. Cir. 2004). A reference is analogous art to the claimed invention if: (1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); or (2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention).
Note that the claimed invention is generally directed to a compilation optimization method for program source code (specification, paragraph [0002]). As for the “same field of endeavor” test, Holler is generally directed to improving prefetching performances in a computer system (Holler, col. 1 lines 8 and 9). And Tinker is generally directed to modifying compiled executable files to add additional functionality (Tinker, paragraph [0001]). As for the “reasonably pertinent” test, Arai is generally directed to performing loop fission on an application program to be executed in a target machine, thereby reducing cache misses occurring in the target machine (Arai, paragraph [0029]). Thus, Holler, Tinker, and Arai are all analogous art to the claimed invention (even if they address different problems or are not in the same field of endeavor as the claimed invention). See MPEP § 2141.01(a)(I).]
As per Claim 1, Holler discloses:
A method (col. 1 lines 8 and 9, “[…] method for improving prefetching performances in a computer system.”) comprising:
compiling program source code to obtain an executable program, wherein the executable program comprises an executable instruction (Figure 1; col. 3 lines 28-34,“There is shown in FIG. 1 system 10 for optimizing code, such as program source code 11, which code is passed through compiler and optimizer 12A to produce executable code 13A. Compiler and optimizer 12A in the normal mode would operate on code using CC PROGRAM.C (shown in FIG. 3A) to produce executable code 31, which would look similar to the code steps 301-306 shown in FIG. 3B [wherein the executable program comprises an executable instruction] (emphasis added).”);
running a first executable file, wherein the first executable file comprises the executable program (col. 3 lines 44-47, “Once executable code 13A is produced by the compiler and optimizer 12A, it is run on sample data 14 and as the executable code is being run, a special tool called a sampling oriented profiler 15, is watching the executable code run (emphasis added).”); and
compiling the program source code based on [a] first configuration information to obtain a second executable file (col. 3 lines 51-53, “Returning now to FIG. 1, profiler 15 watches the executable code and creates information file 50, which records the relative timings of various instructions [{a} first configuration information].” and lines 60-64, “This information file 50 contains a snapshot of what the program looks like as it is running and shows which operations take the most time to run. This data snapshot is then read by the compiler and optimizer 12B to produce revised executable code 13B (emphasis added).”).
Holler discloses “wherein a first executable file comprises an executable program,” but Holler does not explicitly disclose:
wherein the first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between the program source code and the executable instruction; and
obtaining first configuration information based on the debugging information.
However, Tinker discloses:
wherein a first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between program source code and an executable instruction (paragraph [0004], “[…] application programs known as debuggers were developed to provide additional control over execution of executable files. A debugger loads executable code into memory and then controls execution of the executable code. For example, the debugger can execute a single executable code instruction at a time. Alternately, the debugger can execute the executable code continuously until a break point designated within the debugger is reached. Such debuggers can also use additional information stored in an executable code file during the compiling and linking steps to reconstruct and display the source code lines that correspond to the instructions in the executable code [wherein a first executable file comprises debugging information]. The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions [wherein the debugging information comprises a correspondence between program source code and an executable instruction]. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”); and
obtaining first configuration information based on the debugging information (paragraph [0004], “The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line [obtaining first configuration information based on the debugging information]. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”).
As pointed out hereinabove, Holler and Tinker are both analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tinker into the teaching of Holler to include “wherein the first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between the program source code and the executable instruction; and obtaining first configuration information based on the debugging information.” The modification would be obvious because one of ordinary skill in the art would be motivated to load executable code into memory and then control execution of the executable code (Tinker, paragraph [0004]).
The combination of Holler and Tinker discloses “obtaining first configuration information based on debugging information,” but the combination of Holler and Tinker does not explicitly disclose:
collecting a hardware cache event based on running the first executable file; and
obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier.
However, Arai discloses:
collecting a hardware cache event based on running a first executable file (paragraph [0033], “The main memory 12 is a hardware device such as a dynamic random access memory (DRAM) that stores an application program 15 to be executed in the computation core 13 [based on running a first executable file].”; paragraph [0038], “The number of times that cache misses including the compulsory miss and the replacement miss occurs from the start to the end of the execution of the application program 15 is called the number of cache misses.”; paragraph [0068]1, “Each computing machinery 21 generates the profile information 17 including […] the number of cache misses in the corresponding set identifier s. The profile information 17 can be generated fast by the computing machineries 21 individually performing computations in parallel in such a manner [collecting a hardware cache event based on running a first executable file] (emphasis added).”); and
[1Examiner’s Remarks: Note that the Applicant’s specification expressly states that “[…] the hardware cache event may include a cache hit event and a cache miss event” (page 14, paragraph [0068]). Thus, under the broadest reasonable interpretation (BRI), the plain meaning of the limitation “a hardware cache event” includes a cache hit event and a cache miss event, which is consistent with the specification. Thus, the limitation “a hardware cache event,” given its plain meaning consistent with the specification, is mapped to Arai’s cache miss. See MPEP § 2173.01(I).]
obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier (paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel [obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier] (emphasis added).”).
As pointed out hereinabove, Arai is an analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Arai into the combined teachings of Holler and Tinker to include “collecting a hardware cache event based on running the first executable file; and obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier.” The modification would be obvious because one of ordinary skill in the art would be motivated to reduce a number of memory reference instructions included in one loop (Arai, paragraph [0039]).
As per Claim 2, the rejection of Claim 1 is incorporated; and the combination of Holler and Tinker discloses “based on debugging information,” but the combination of Holler and Tinker does not explicitly disclose:
parsing the hardware cache event to obtain a second quantity of cache misses corresponding to the executable instruction; and
determining, based on the second quantity and the debugging information, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain the first configuration information.
However, Arai discloses:
parsing a hardware cache event to obtain a second quantity of cache misses corresponding to an executable instruction (paragraph [0033], “The main memory 12 is a hardware device such as a dynamic random access memory (DRAM) that stores an application program 15 to be executed in the computation core 13.”; paragraph [0038], “The number of times that cache misses including the compulsory miss and the replacement miss occurs from the start to the end of the execution of the application program 15 is called the number of cache misses.”; paragraph [0068], “Each computing machinery 21 generates the profile information 17 including […] the number of cache misses in the corresponding set identifier s. The profile information 17 can be generated fast by the computing machineries 21 individually performing computations in parallel in such a manner (emphasis added).”); and
determining, based on the second quantity, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain a first configuration information (paragraph [0056], “[…] two statements selected from among the statements S1, S2, and S3 are expressed by the ordered pair, and the ordered pair is associated with both the number of cache hits and the number of cache misses. The ordered pair is a pair including a first component that is the statement to be executed first and a second component that is the statement to be executed second when an output program 18 after loop fission is executed. Although there are such pairs, here, a pair having the execution result, when executed in the loop, identical to that in the application program 15 is defined as the ordered pair.”; paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel (emphasis added).”).
As pointed out hereinabove, Arai is an analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Arai into the combined teachings of Holler and Tinker to include “parsing the hardware cache event to obtain a second quantity of cache misses corresponding to the executable instruction; and determining, based on the second quantity and the debugging information, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain the first configuration information.” The modification would be obvious because one of ordinary skill in the art would be motivated to reduce a number of memory reference instructions included in one loop (Arai, paragraph [0039]).
Claims 11 and 13 are device claims corresponding to the method claims hereinabove (Claims 1 and 2, respectively). Therefore, Claims 11 and 13 are rejected for the same reasons set forth in the rejections of Claims 1 and 2, respectively.
Claim 21 is a computer program product claim corresponding to the method claim hereinabove (Claim 1). Therefore, Claim 21 is rejected for the same reason set forth in the rejection of Claim 1.
Allowable Subject Matter
Claims 3-10 and 14-20 are objected to as being dependent upon a rejected base claim under 35 U.S.C. 103, but would be allowable over the cited prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and overcome any corresponding objections and/or rejections set forth hereinabove.
Conclusion
The prior art made of record and not relied upon is considered pertinent to the Applicant’s disclosure. They are as follows:
US 2010/0088688 (hereinafter “Edwards”) discloses optimizing an executable program to improve instruction cache hit rate when executed on a processor.
US 2014/0281232 (hereinafter “Hagersten”) discloses inserting prefetches into software applications or programs.
US 6,314,431 (hereinafter “Gornish”) discloses improving performance of instruction pre-fetching on computer systems.
US 10,481,813 (hereinafter “Ugale”) discloses extending cache operational lifetime.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Qing Chen whose telephone number is 571-270-1071. The Examiner can normally be reached on Monday through Friday from 9:00 AM to 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, the Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Qing Chen/
Primary Examiner, Art Unit 2191