DETAILED ACTION
This Office action is in response to the amendment submitted on April 10, 2026.
Claims 1-11 and 13-21 are pending.
Claims 1-6, 8-11, 13-17, and 19-21 are currently amended.
Claim 12 is canceled.
The objection to the title of the invention is withdrawn in view of the Applicant’s amendments to the title of the invention.
The objections to Claims 1, 2, 4-6, 8-11, 13-17, 19, and 20 are withdrawn in view of the Applicant’s amendments to the claims. However, the Applicant has failed to address an objection to Claim 3. Accordingly, this objection is maintained and further explained hereinafter.
The 35 U.S.C. § 112(b) rejections of Claims 5 and 16 are withdrawn in view of the Applicant’s amendments to the claims.
In the interest of facilitating compact prosecution, the Examiner kindly asks the Applicant’s representative to authorize Internet communications with the Examiner by submitting Form PTO/SB/439 using Patent Center.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 recites “the prefetch distance.” It should read -- the prefetch distance of the first source code --.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,933,643 (hereinafter “Holler”) (cited in the IDS submitted on 01/06/2025) in view of US 2002/0073398 (hereinafter “Tinker”) and US 2021/0019128 (hereinafter “Arai”).
[Examiner’s Remarks: In order for a reference to be proper for use in an obviousness rejection under 35 U.S.C. 103, the reference must be analogous art to the claimed invention. In re Bigio, 381 F.3d 1320, 1325, 72 USPQ2d 1209, 1212 (Fed. Cir. 2004). A reference is analogous art to the claimed invention if: (1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); or (2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention).
Note that the claimed invention is generally directed to a compilation optimization method for program source code (specification, paragraph [0002]). As for the “same field of endeavor” test, Holler is generally directed to improving prefetching performances in a computer system (Holler, col. 1 lines 8 and 9). And Tinker is generally directed to modifying compiled executable files to add additional functionality (Tinker, paragraph [0001]). As for the “reasonably pertinent” test, Arai is generally directed to performing loop fission on an application program to be executed in a target machine, thereby reducing cache misses occurring in the target machine (Arai, paragraph [0029]). Thus, Holler, Tinker, and Arai are all analogous art to the claimed invention (even if they address different problems or are not in the same field of endeavor as the claimed invention). See MPEP § 2141.01(a)(I).]
As per Claim 1, Holler discloses:
A method (col. 1 lines 8 and 9, “[…] method for improving prefetching performances in a computer system.”) comprising:
compiling program source code to obtain an executable program, wherein the executable program comprises an executable instruction (Figure 1; col. 3 lines 28-34,“There is shown in FIG. 1 system 10 for optimizing code, such as program source code 11, which code is passed through compiler and optimizer 12A to produce executable code 13A. Compiler and optimizer 12A in the normal mode would operate on code using CC PROGRAM.C (shown in FIG. 3A) to produce executable code 31, which would look similar to the code steps 301-306 shown in FIG. 3B [wherein the executable program comprises an executable instruction] (emphasis added).”);
running a first executable file, wherein the first executable file comprises the executable program (col. 3 lines 44-47, “Once executable code 13A is produced by the compiler and optimizer 12A, it is run on sample data 14 and as the executable code is being run, a special tool called a sampling oriented profiler 15, is watching the executable code run (emphasis added).”); and
compiling the program source code based on [a] first configuration information to obtain a second executable file (col. 3 lines 51-53, “Returning now to FIG. 1, profiler 15 watches the executable code and creates information file 50, which records the relative timings of various instructions [{a} first configuration information].” and lines 60-64, “This information file 50 contains a snapshot of what the program looks like as it is running and shows which operations take the most time to run. This data snapshot is then read by the compiler and optimizer 12B to produce revised executable code 13B (emphasis added).”).
Holler discloses “wherein a first executable file comprises an executable program,” but Holler does not explicitly disclose:
wherein the first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between the program source code and the executable instruction; and
obtaining first configuration information based on the debugging information.
However, Tinker discloses:
wherein a first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between program source code and an executable instruction (paragraph [0004], “[…] application programs known as debuggers were developed to provide additional control over execution of executable files. A debugger loads executable code into memory and then controls execution of the executable code. For example, the debugger can execute a single executable code instruction at a time. Alternately, the debugger can execute the executable code continuously until a break point designated within the debugger is reached. Such debuggers can also use additional information stored in an executable code file during the compiling and linking steps to reconstruct and display the source code lines that correspond to the instructions in the executable code [wherein a first executable file comprises debugging information]. The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions [wherein the debugging information comprises a correspondence between program source code and an executable instruction]. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”); and
obtaining first configuration information based on the debugging information (paragraph [0004], “The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line [obtaining first configuration information based on the debugging information]. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”).
As pointed out hereinabove, Holler and Tinker are both analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tinker into the teaching of Holler to include “wherein the first executable file comprises debugging information, and wherein the debugging information comprises a correspondence between the program source code and the executable instruction; and obtaining first configuration information based on the debugging information.” The modification would be obvious because one of ordinary skill in the art would be motivated to load executable code into memory and then control execution of the executable code (Tinker, paragraph [0004]).
The combination of Holler and Tinker discloses “obtaining first configuration information based on debugging information,” but the combination of Holler and Tinker does not explicitly disclose:
collecting a hardware cache event based on running the first executable file; and
obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code.
However, Arai discloses:
collecting a hardware cache event based on running a first executable file (paragraph [0033], “The main memory 12 is a hardware device such as a dynamic random access memory (DRAM) that stores an application program 15 to be executed in the computation core 13 [based on running a first executable file].”; paragraph [0038], “The number of times that cache misses including the compulsory miss and the replacement miss occurs from the start to the end of the execution of the application program 15 is called the number of cache misses.”; paragraph [0068]1, “Each computing machinery 21 generates the profile information 17 including […] the number of cache misses in the corresponding set identifier s. The profile information 17 can be generated fast by the computing machineries 21 individually performing computations in parallel in such a manner [collecting a hardware cache event based on running a first executable file] (emphasis added).”); and
[1Examiner’s Remarks: Note that the Applicant’s specification expressly states that “[…] the hardware cache event may include a cache hit event and a cache miss event” (page 14, paragraph [0068]). Thus, under the broadest reasonable interpretation (BRI), the plain meaning of the limitation “a hardware cache event” includes a cache hit event and a cache miss event, which is consistent with the specification. Thus, the limitation “a hardware cache event,” given its plain meaning consistent with the specification, is mapped to Arai’s cache miss. See MPEP § 2173.01(I).]
obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code (paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel [obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code] (emphasis added).”).
As pointed out hereinabove, Arai is an analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Arai into the combined teachings of Holler and Tinker to include “collecting a hardware cache event based on running the first executable file; and obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code.” The modification would be obvious because one of ordinary skill in the art would be motivated to reduce a number of memory reference instructions included in one loop (Arai, paragraph [0039]).
As per Claim 2, the rejection of Claim 1 is incorporated; and the combination of Holler and Tinker discloses “based on debugging information,” but the combination of Holler and Tinker does not explicitly disclose:
parsing the hardware cache event to obtain a second quantity of cache misses corresponding to the executable instruction; and
determining, based on the second quantity of cache misses corresponding to the executable instruction and the debugging information, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain the first configuration information.
However, Arai discloses:
parsing a hardware cache event to obtain a second quantity of cache misses corresponding to an executable instruction (paragraph [0033], “The main memory 12 is a hardware device such as a dynamic random access memory (DRAM) that stores an application program 15 to be executed in the computation core 13.”; paragraph [0038], “The number of times that cache misses including the compulsory miss and the replacement miss occurs from the start to the end of the execution of the application program 15 is called the number of cache misses.”; paragraph [0068], “Each computing machinery 21 generates the profile information 17 including […] the number of cache misses in the corresponding set identifier s. The profile information 17 can be generated fast by the computing machineries 21 individually performing computations in parallel in such a manner (emphasis added).”); and
determining, based on the second quantity of cache misses corresponding to the executable instruction, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain a first configuration information (paragraph [0056], “[…] two statements selected from among the statements S1, S2, and S3 are expressed by the ordered pair, and the ordered pair is associated with both the number of cache hits and the number of cache misses. The ordered pair is a pair including a first component that is the statement to be executed first and a second component that is the statement to be executed second when an output program 18 after loop fission is executed. Although there are such pairs, here, a pair having the execution result, when executed in the loop, identical to that in the application program 15 is defined as the ordered pair.”; paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel (emphasis added).”).
As pointed out hereinabove, Arai is an analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Arai into the combined teachings of Holler and Tinker to include “parsing the hardware cache event to obtain a second quantity of cache misses corresponding to the executable instruction; and determining, based on the second quantity of cache misses corresponding to the executable instruction and the debugging information, a third quantity of cache misses corresponding to source code associated with the executable instruction to obtain the first configuration information.” The modification would be obvious because one of ordinary skill in the art would be motivated to reduce a number of memory reference instructions included in one loop (Arai, paragraph [0039]).
Claims 11 and 13 are device claims corresponding to the method claims hereinabove (Claims 1 and 2, respectively). Therefore, Claims 11 and 13 are rejected for the same reasons set forth in the rejections of Claims 1 and 2, respectively.
Claim 21 is a computer program product claim corresponding to the method claim hereinabove (Claim 1). Therefore, Claim 21 is rejected for the same reason set forth in the rejection of Claim 1.
Allowable Subject Matter
Claims 3-10 and 14-20 are objected to as being dependent upon a rejected base claim under 35 U.S.C. 103, but would be allowable over the cited prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and overcome any corresponding objections and/or rejections set forth hereinabove.
Response to Arguments
Applicant’s arguments submitted on April 10, 2026 have been fully considered, but they are not persuasive.
In the Remarks, the Applicant argues:
In rejecting independent claim 1, the Examiner asserts that Holler discloses compiling program source code based on first configuration information. See Office Action, p. 6. The Examiner maps Holler’s information file 50 to the configuration information of claim 1. While Holler creates an information file based on watching the executable code run, Holler does not create an information file that includes an identifier of the program source code and a quantity of cache misses:
[…]
As shown above, Holler’s profiler 15 watches the executable code as it runs and creates information file 50, which records the relative timings of various instructions. Holler’s information file 50 contains a snapshot of what the executable code looks like as it is running and shows which operations take the most time to run. Holler’s compiler and optimizer 12B produces revised executable code 13B based on the information file 50. While Holler creates an information file based on watching the executable code run, Holler does not create an information file that includes an identifier of the program source code and a quantity of cache misses, as claimed in claim 1 - this is in direct contrast to what is claimed in claim 1. Further, Holler does not disclose that the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code. Therefore, claims 1, 11, and 21 are allowable over Holler.
(See Remarks – pages 15 and 16, emphasis in original.)
Examiner’s response:
Examiner disagrees. Applicant’s arguments are not persuasive for at least the following reasons:
First, in response to the Applicant’s arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Second, with respect to the Applicant’s assertion that “Holler does not disclose that the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code,” the Examiner respectfully submits that the combination of Holler and Tinker discloses “obtaining first configuration information based on […] the debugging information,” but the combination of Holler and Tinker does not explicitly disclose “collecting a hardware cache event based on running the first executable file” and “obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier.” Examiner relies upon Arai for its specific teachings of “collecting a hardware cache event based on running a first executable file” and “obtaining first configuration information based on the hardware cache event, wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code.” Thus, the Applicant’s argument regarding “Holler does not disclose that the first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code” is, at best, moot.
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1, 2, 11, 13, and 21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
Tinker and Arai do not overcome the deficiencies in Holler. Tinker’s paragraph 4 was cited for obtaining configuration information based on debugging information, See id. p. 7, and Arai’s paragraphs 105 and 106 were cited for obtaining configuration information based on hardware cache event. Tinker obtains values of variables and expressions while executing executable files, but nowhere does Tinker disclose that a first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code. Further, Arai discloses a counting unit that counts the number of cache misses and the number of cache hits when a loop is executed in an application program. Arai, ¶ 105. Further, Arai discloses a plurality of computing machineries that correspond to a set identifier. Arai, ¶ 106. However, the computing machineries are cache memory that correspond to the set identifier -- this Arai disclosure is in contrast to claim 1 that claims the identifier is of the program source code. Therefore, Arai does not disclose an identifier of a program source code but an identifier of cache memory. Further, Arai does not disclose configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code. Therefore, claims 1, 11, and 21 are allowable over Holler, Tinker and Arai, and the Applicant respectfully requests withdrawal of the 35 U.S.C. § 103 rejection of claims 1, 2, 11, 13, and 21.
(See Remarks – pages 16 and 17, emphasis in original.)
Examiner’s response:
Examiner disagrees. Applicant’s arguments are not persuasive for at least the following reasons:
First, with respect to the Applicant’s assertion that “nowhere does Tinker disclose that a first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code,” the Examiner respectfully submits that the Examiner relies upon Arai for its specific teaching of “wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code.” Thus, the Applicant’s argument regarding “nowhere does Tinker disclose that a first configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code” is, at best, moot.
Second, with respect to the Applicant’s assertion that “Arai does not disclose configuration information comprises an identifier of the program source code and a first quantity of cache misses corresponding to the identifier of the program source code,” the Examiner respectfully submits that Arai discloses “wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code” (Figure 3; paragraph [0055], “[…] profile information 17 is generated based on the application program 15. The profile information 17 includes the number of cache hits and the number of cache misses that are expected when the program in which only two of the statements S1, S2, and S3 are written in the loop 15a [an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code] is executed in the target machine 10 (emphasis added).”; paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel [wherein the first configuration information comprises an identifier of program source code and a first quantity of cache misses corresponding to the identifier of the program source code] (emphasis added).”). Note that Arai discloses that the profile information includes the number of cache misses that are expected when the program in which only two of the statements S1, S2, and S3 are written in the loop. Thus, one of ordinary skill in the art would readily comprehend that Arai’s Figure 3 depicts the S1, S2, and S3 identifiers for the source code statements in the loop and therefore, the S1, S2, and S3 identifiers can be reasonably interpreted as the claimed “an identifier of program source code.”
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1, 2, 11, 13, and 21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
Second, claims 1, 2, 11, 13, and 21 are allowable over the combination of Holler, Tinker, and Arai because the combination of Holler, Tinker, and Arai fails to disclose obtaining first configuration information based on a hardware cache event and debugging information. In rejecting independent claim 1, the Examiner admits that Holler does not disclose obtaining first configuration information based on debugging information. See Office Action, p. 6. Instead, the Examiner asserts that Tinker’s paragraph 4 discloses this limitation. See id., p. 6-7. While Tinker obtains values of variables and expressions while executing executable files, Tinker does not obtain information based on a hardware cache event while executing the executable file:
[…]
As shown above, Tinker uses a debugger to control execution of executable files, and loads executable code into memory and then controls execution of the executable code. Tinker’s debugger displays source code during the execution of the executable code by setting a breakpoint at a particular point in the source code. When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions While Tinker obtains values of variables and expressions while executing executable files, Tinker does not obtain information based on a hardware cache event while executing the executable file. Further, Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information. Therefore, claims 1, 11, and 21 are allowable over Holler and Tinker.
(See Remarks – pages 17 and 18, emphasis in original.)
Examiner’s response:
Examiner disagrees. Applicant’s arguments are not persuasive for at least the following reasons:
First, in response to the Applicant’s arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Second, with respect to the Applicant’s assertion that “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information,” the Examiner respectfully submits that Holler does not explicitly disclose “obtaining first configuration information based on the hardware cache event and the debugging information.” Examiner relies upon Tinker for its specific teaching of “obtaining first configuration information based on the debugging information” and Arai for its specific teaching of “obtaining first configuration information based on the hardware cache event.” Thus, the Applicant’s argument regarding “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information” is, at best, moot.
Third, with respect to the Applicant’s assertion that “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information,” the Examiner further submits that Tinker discloses “obtaining first configuration information based on the debugging information” (paragraph [0004], “The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line [obtaining first configuration information based on the debugging information]. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”). And Arai discloses “obtaining first configuration information based on the hardware cache event” (paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3) [obtaining first configuration information based on the hardware cache event] (emphasis added).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel [obtaining first configuration information based on the hardware cache event] (emphasis added).”).
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1, 2, 11, 13, and 21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
Arai does not overcome the deficiencies in Holler. Arai’s paragraphs 33 and 38 were cited for obtaining configuration information based on hardware cache event, See id. p. 8. While Arai obtains cache misses while executing an application program, Arai does not obtain information based on a hardware cache event and debugging information while executing the application program:
[…]
As shown above, Arai executes an application program in a computation core. Arai obtains a number of times that cache misses including the compulsory miss and a replacement miss occurs from the start to the end of the execution of the application program. While Arai obtains cache misses while executing the application program, Arai does not obtain information based on a hardware cache event and debugging information while executing the executable file— Arai instead only obtains cache misses while failing to consider debugging information. Further, Arai does not disclose obtain first configuration information based on a hardware cache event and debugging information. Therefore, claims 1, 11, and 21 are allowable over Holler, Tinker and Arai, and the Applicant respectfully requests withdrawal of the 35 U.S.C. § 103 rejection of claims 1, 2, 11, 13, and 21.
(See Remarks – pages 18 and 19, emphasis in original.)
Examiner’s response:
Examiner disagrees. Applicant’s arguments are not persuasive for at least the following reasons:
First, in response to the Applicant’s arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Second, with respect to the Applicant’s assertion that “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information,” the Examiner respectfully submits that Holler does not explicitly disclose “obtaining first configuration information based on the hardware cache event and the debugging information.” Examiner relies upon Tinker for its specific teaching of “obtaining first configuration information based on the debugging information” and Arai for its specific teaching of “obtaining first configuration information based on the hardware cache event.” Thus, the Applicant’s argument regarding “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information” is, at best, moot.
Third, with respect to the Applicant’s assertion that “Tinker does not disclose obtaining first configuration information based on a hardware cache event and debugging information,” the Examiner further submits that Tinker discloses “obtaining first configuration information based on the debugging information” (paragraph [0004], “The display of the source code facilitates control by the software developer of the execution of the executable code (e.g., setting a breakpoint at a particular point in the source code). When execution of the executable code is stopped, a user can interact with the debugger to view current values of variables and expressions. In addition, some debuggers allow a user to view the effects of temporarily modifying a source code line [obtaining first configuration information based on the debugging information]. Nonetheless, although such debuggers can assist with locating errors in executable compiled code, recompiling and linking is needed to fix errors that are located (emphasis added).”). And Arai discloses “obtaining first configuration information based on the hardware cache event” (paragraph [0105], “The counting unit 53 counts the number of cache misses […] that are expected when the loop is executed for each ordered pair of the statements included in the application program 15, and writes the results in the profile information 17 (see FIG. 3) [obtaining first configuration information based on the hardware cache event] (emphasis added).”; paragraph [0106], “When a plurality of the computing machineries 21 each corresponding to the set identifier s as illustrated in FIG. 4 is used, the counting unit 53 is implemented in each of these computing machineries 21. In this case, each counting unit 53 counts the number of cache misses […] in the set identifiers of its own device in parallel [obtaining first configuration information based on the hardware cache event] (emphasis added).”).
Fourth, with respect to the Applicant’s assertion that “Arai does not obtain information based on a hardware cache event and debugging information while executing the application program,” the Examiner respectfully submits that the Applicant’s argument is not commensurate in scope with the claim language. The claims do not recite the particular limitation of “obtaining first configuration information based on the hardware cache event and the debugging information while executing the application program (emphasis added).” The claims only require “obtaining first configuration information based on the hardware cache event and the debugging information.” Applicant is reminded that in order for such limitations to be considered, the claims are required to explicitly recite such limitations, otherwise broadest reasonable interpretations of the broadly claimed limitations are deemed to be proper.
Fifth, with respect to the Applicant’s assertion that “Arai instead only obtains cache misses while failing to consider debugging information,” the Examiner respectfully submits that the Applicant’s argument is not commensurate in scope with the claim language. The claims recite only the limitation of “obtaining first configuration information based on the hardware cache event and the debugging information” with no further clarification on the relationship between the recited “the hardware cache event” and “the debugging information” as intended by the Applicant. The claims do not explicitly require that the debugging information must be considered when obtaining the cache misses. Thus, as the claims are interpreted as broadly as their terms reasonably allow (see MPEP § 2111.01(I)), the interpretation of a broad limitation of “obtaining first configuration information based on the hardware cache event and the debugging information” by one of ordinary skill in the art as without having any defined relationships between the recited “the hardware cache event” and “the debugging information” is considered to be reasonable by its plain meaning.
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1, 2, 11, 13, and 21 are proper and therefore, maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Qing Chen whose telephone number is 571-270-1071. The Examiner can normally be reached on Monday through Friday from 9:00 AM to 5:00 PM ET.
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Qing Chen/
Primary Examiner, Art Unit 2191
Prosecution Insights