DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kusaka (JP 2021-028131), cited in the IDS dated 4/4/24. Reference will be made to the applicant provided translation.
Regarding claims 1, 21, and 22, Kusaka discloses a non-transitory computer-readable medium storing a program that is executable by a printing apparatus, a data transferring method executed in a printing apparatus, and a printing apparatus comprising:
a main control circuit (see paras 15-17, chip controller 8 is a main control circuit);
a sub-control circuit group connected to the main control circuit in series, the sub-control circuit group being configured to transfer data from the main control circuit downstream (see para 16, sub-control circuit chips 61-64 are connected to chip controller 8 in series/daisy chain and are configured to transfer data from the chip controller 8 to the downstream chips 61-64); and
a head group configured to be driven by the sub-control circuit group based on the data (see para 14, each chip 61-64 contain one nozzle row composed of 256 nozzles 611 that make up a head group),
wherein:
the sub-control circuit group includes a first sub-control circuit connected to the main control circuit, and a second sub-control circuit positioned downstream of the first sub-control circuit (see paras 14 and 16, sub-control circuit chips 61-64 are connected to chip controller 8 in series/daisy chain, chip controller 8 is connected to chip 61, which is connected to chip 62, so on and so forth);
the main control circuit is configured to reserve a main communication address space in the main control circuit (see paras 15, 17, and 29, chip controller 8 utilizes a DRAM 20);
the first sub-control circuit is configured to reserve a first sub-communication address space in the first sub-control circuit (see paras 16 and 22-23, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip);
the first sub-control circuit includes a first sub-memory (see paras 26-27 and 35, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip); and
the first sub-control circuit is configured to:
in a case that the data is written into a first main communication address space,
write the data written into the first main communication address space into the first sub-memory, the first main communication address space being reserved in the main communication address space and being correlated with the first sub-memory (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20, the stored data can be a data reading command, heater control command, or a data through command); and
in a case that the data is written into a second main communication address space reserved in the main communication address space, write the data written into the second main communication address space into the first sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30).
Regarding claim 2, Kusaka further discloses wherein:
the second sub-control circuit includes a second sub-memory (see paras 26-27 and 35, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip); and
in a case that the data is written into the second main communication address space correlated with the second sub-memory, the second sub-control circuit is configured to write the data written into the second main communication address space into the second sub-memory via the first sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 that is then passed to chip 62 from DRAM 20 based on data selectors A29 and A30).
Regarding claim 3, Kusaka further discloses wherein:
the sub-control circuit group includes a third sub-control circuit positioned downstream of the second sub-control circuit (see paras 14 and 16, sub-control circuit chips 61-64 are connected to chip controller 8 in series/daisy chain, chip controller 8 is connected to chip 61, which is connected to chip 62, so on and so forth, chip 63 would be the third sub-control circuit);
the second sub-control circuit is configured to reserve a second sub-communication address space in the second sub-control circuit (see paras 16 and 22-23, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip); and
in a case that the data is written into the third main communication address space reserved in the main communication address space, the second sub-control circuit is configured to write the data written into the third main communication address space into the second sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 that is then passed to chip 62 from DRAM 20 based on data selectors A29 and A30).
Regarding claim 4, Kusaka further discloses wherein:
the third sub-control circuit includes a third sub-memory (see paras 26-27 and 35, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip); and
in a case that the data is written into the third main communication address space correlated with the third sub-memory, the third sub-control circuit is configured to write the data written into the third main communication address space into the third sub-memory via the second sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 that is then passed to chip 62 that is then passed to chip 63 based on data selectors A29 and A30).
Regarding claim 5, Kusaka further discloses wherein:
the first sub-communication address space includes a first sub-receiving address space and a first sub-transmitting address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
the first sub-control circuit is configured to:
in a case that the data is written into the second main communication address space, write the data written into the second main communication address space into the first receiving space and the first transmitting space, the first receiving space being reserved in the first sub-receiving address space and being correlated with the second main communication address space, the first transmitting space being reserved in the first sub-transmitting address space and being correlated with the first receiving space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
in a case that the data is written into the third main communication address space, write the data written into the third main communication address space into a second receiving space and the second transmitting space, the second receiving space being reserved in the first sub-receiving address space and being correlated with the third main communication address space, the second transmitting space being reserved in the first sub-transmitting address space and being correlated with the second receiving space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 6, Kusaka further discloses wherein:
the second sub-communication address space includes a second sub-receiving address space and a second sub-transmitting address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
in a case that the data is written into the third main communication address space, the second sub-control circuit is configured to write the data written into the third main communication address space into the third receiving space and the third transmitting space, the third receiving space being reserved in the second sub-receiving address space and being correlated with the third main communication address space, the third transmitting space being reserved in the second sub-transmitting address space and being correlated with the third receiving space (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 7, Kusaka further discloses wherein:
the main control circuit includes a main memory (see para 17, chip controller 8 includes DRAM 20); and
the first sub-control circuit is configured to:
perform a writing into a first main memory area by performing a writing into the first sub-communication address space, the first main memory area being reserved in the main memory and being correlated with the first sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30); and
perform a reading out from the first main memory area by performing a reading out from the first sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chip 61 from DRAM 20 based on data selectors A29 and A30).
Regarding claim 8, Kusaka further discloses wherein:
the main control circuit includes a common memory correlated with or to be correlated with the first sub-control circuit and the second sub-control circuit (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30); and
the first sub-control circuit is configured to:
perform a writing into the common memory by performing a writing into the first sub-communication address space correlated with the common memory (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30); and
perform a reading out from the common memory by performing a reading out from the first sub-communication address space correlated with the common memory (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30).
Regarding claim 9, Kusaka further discloses wherein:
the first sub-control circuit includes a first sub-register (see paras 24-27, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip);
data to be written into the first main communication address space includes data different from data to be written into the first sub-memory (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
the first sub-control circuit is configured to write the data different from the data to be written into the first sub-memory into the first sub-register correlated with the first main communication address space (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 10, Kusaka further discloses wherein:
the second sub-control circuit includes a second sub-register (see paras 24-27, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip);
data to be written into the second main communication address space includes data different from data to be written into the second sub-memory (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
the second sub-control circuit is configured to write the data different from the data to be written into the second sub-memory into the second sub-register correlated with the second main communication address space (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 11, Kusaka further discloses wherein:
the third sub-control circuit includes a third sub-register (see paras 24-27, each chip 61-64 has a buffer memory for storing data to be processed or transmitted to the next chip);
data to be written into the third main communication address space includes data different from data to be written into the third sub-memory (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
the third sub-control circuit is configured to write the data different from the data to be written into the third sub-memory into the third sub-register correlated with the third main communication address space (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 12, Kusaka further discloses wherein:
the main control circuit includes a common register correlated with or to be correlated with the first sub-control circuit and the second sub-control circuit (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30); and
the first sub-control circuit is configured to:
perform a writing into the common register by performing a writing into the first sub-communication address space correlated with the common register (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
perform a reading out from the common register by performing a reading out from the first sub-communication address space correlated with the common register (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 13, Kusaka further discloses wherein:
the second sub-control circuit is configured to reserve a second sub-communication address space in the second sub-control circuit (see paras 14 and 16, chips 61-64 store data transmitted from chip controller 8); and
the second sub-control circuit is configured to:
perform a writing into the common register by performing a writing into the second sub-communication address space correlated with the first sub-communication address space (see paras 22-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
perform a reading out from the common register by performing a reading out from the second sub-communication address space correlated with the first sub-communication address space (see chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 14, Kusaka further discloses wherein:
the sub-control circuit group includes a third sub-control circuit positioned downstream of the second sub-control circuit (see paras 14 and 16, chips 61-64 store data transmitted from chip controller 8);
the third sub-control circuit is configured to reserve a third sub-communication address space in the third sub-control circuit (see paras 14 and 16, chips 61-64 store data transmitted from chip controller 8); and
the third sub-control circuit is configured to:
perform a writing into the common register correlated with the third sub-control circuit by performing a writing into the third sub-communication address space correlated with the second sub-communication address space (see chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
perform a reading out from the common register correlated with the third sub-control circuit by performing a reading out from the third sub-communication address space correlated with the second sub-communication address space (see chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 15, Kusaka further discloses wherein:
the head group includes a first head configured to be driven by the first sub-control circuit and a second head configured to be driven by the second sub-control circuit (see paras 14-17, each chip 61-64 contain one nozzle row composed of 256 nozzles 611 that make up a head group); and
the main control circuit is configured to:
write a first image data indicating an image to be formed by driving of the first head into the first main communication address space (see paras 25-39, chip controller 8 transmits image forming data to chips 61-64 for ejection of ink to form an image); and
write a second image data indicating an image to be formed by driving of the second head into the second main communication address space (see paras 25-39, chip controller 8 transmits image forming data to chips 61-64 for ejection of ink to form an image).
Regarding claim 16, Kusaka further discloses wherein:
the head group includes a third head configured to be driven by the third sub-control circuit (see each chip 61-64 contain one nozzle row composed of 256 nozzles 611 that make up a head group); and
the main control circuit is configured to write a third image data indicating an image to be formed by driving of the third head into the third main communication address space (see paras 25-39, chip controller 8 transmits image forming data to chips 61-64 for ejection of ink to form an image).
Regarding claim 17, Kusaka further discloses, wherein the first sub-control circuit is configured to read out, from the first sub-communication address space, a common parameter common to the first sub-control circuit, the second sub-control circuit, and the third sub-control circuit, or an individual parameter specific to the first sub-control circuit (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 18, Kusaka further discloses wherein the first sub-control circuit is configured to:
determine whether or not an address assignment to the first sub-communication address space has been completed (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
in a case that the address assignment to the first sub-communication address space has been determined to be completed, read out the common parameter or the individual parameter from the first sub-communication address space (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 19, Kusaka further discloses wherein:
the sub-control circuit group includes a third sub-control circuit positioned downstream of the second sub-control circuit (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command); and
the main control circuit is configured to write a parameter common to the first sub- control circuit, the second sub-control circuit, and the third sub-control circuit into the common memory (see paras 16, 22-27, and 39, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Regarding claim 20, Kusaka further discloses wherein the first sub-control circuit is configured to perform a writing into the common register by writing data indicating occurrence of an abnormal situation into the first sub-communication address space (see paras 24-27, chip controller 8 writes data to chips 61-64 from DRAM 20 based on data selectors A29 and A30, the stored data can be a data reading command, heater control command, or a data through command).
Conclusion
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/MARK R MILIA/ Primary Examiner, Art Unit 2681
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