DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9, 10 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by [Nishimura (Fig. 1); 2009/0289930].
Regarding claims 1 and 18, Nishimura discloses an amplifier network comprising a first folded double cascode stage (MN1, MN2) configured to receive a differential input signal (In+, In-) at a first pair of input transistors (MN1, MN2) and generate a first drive signal (the input signal of the transistor MP10), a second folded double cascode stage (MP1, MP2) configured to receive the differential input signal (In+, In-) at a second pair of input transistors (MP1, MP2) and generate a second drive signal (the input signal of the transistor MN10), an output stage (112) including a PMOS common source output transistor (MP10) configured to receive the first drive signal (the input signal of the transistor MP10) at its gate (gate terminal of MP10), and an NOMS common source output transistor (MN10) configured to receive the second drive signal (the input signal of the transistor MN10) at its gate (gate terminal of MN10) and the PMOS common source output transistor (MP10) and the NOMS common source output transistor (MN10) being jointly configured to generate an output signal (Out) based on the first drive signal (the input signal of the transistor MP10) and the second drive signal (the input signal of the transistor MN10).
Regarding claims 2 and 19, Nishimura further comprising at least one biasing stage (MP3, MP4, MN3, MN4) configured to apply bias voltages (BP1, BN1) to one or more transistors (MN1, MN2, MP1, MP2) of each of the first folded double cascode stage (MN1, MN2) and the second folded double cascode stage (MP1, MP2).
Regarding claim 3, wherein the at least one biasing stage (MP3, MP4, MN3, MN4) is configured to receive at least one proportional to PTAT current feed from a delta V BE circuit (BP2, BN2).
Regarding claim 5, Nishimura further comprising an equal number (4) of gain stages (MP4-MP7, MN4-MN7) for positive and negative output signals.
Regarding claims 6 and 20, wherein the output stage (112) further comprises a translinear class AB regulating loop.
Regarding claim 7, wherein the translinear class AB regulating loop (112) comprises a translinear harmonic mean regulating loop.
Regarding claim 9, wherein the first drive signal (the input signal of the transistor MP10) and the second drive signal (the input signal of the transistor MN10) comprise double cascaded current mirror loads (MP4-MP7, MN4-MN7).
Regarding claim 10, wherein the first drive signal (the input signal of the transistor MP10) and the output signal (Out) comprise a first (N1) and second (N2) high impedance node respectively of a first path (In+, MN2, MP7, N1, MP10, Out) and the first (N1) and second (N2) nodes having higher impedance than any other nodes in the first path (In+, MN2, MP7, N1, MP10, Out), and the second drive signal (the input signal of the transistor MN10) and the output signal (Out) comprise a first (N1) and second (N2) high impedance node respectively of a second path (In+, MP2, MN7, N2, MN10, Out) and the first (N1) and second (N2) nodes having higher impedance than any other nodes in the second path (In+, MP2, MN7, N2, MN10, Out).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over [Nishimura (Fig. 1); 2009/0289930].
The limitations recited in the claims are obvious based on the intend use of the invention.
Allowable Subject Matter
Claims 4, 8, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
4,797,631 teaches a double folded cascode input stage with the push pull output stage.
7,315,210 also teaches a double folded cascode input stage with the push pull output stage.
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/HENRY CHOE/ Primary Examiner, Art Unit 2843
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