Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments are moot in view of the new ground of rejections stated below.
35 U.S.C 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 14-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li(US 2019/0235612), Ajanovic(WO 03019394) and Shanbhogue(US 9,652,388).
As to claim 1, Li teaches an apparatus configured for a Root Complex (RC)(Figure 15, PCIE RC) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, Memory); and
one or more processors(Figure 15, Cores) configured to:
generate a PCIe Vendor Defined Message (VDM) message for an Endpoint (EP) of the PCIe system(para [0042] SoC host 502 includes a system a PCIe root complex (RC) 512 and a PCIe root port 514. Host application layer 510 includes a VDM generator 518, and a VDM receiver 520. [0029] FIG. 2 shows a table specifying aspects of Vendor Defined Messages, which use the header format shown in FIG. 3. As defined in PCIe 4.0 section 2.2.8.6, [0030] The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. [0031] If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message. [0033] Bytes 12 through 15 are available for vendor definition.).
Li does not explicitly teach but Ajanovic teaches an in-band PCIe message from root complex to end points(para [0038] – [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li and Ajanovic since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Ajanovic are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Ajanovic’s in-band messages in Li would have improved messaging performance of modified messaging system of Li(Ajanovic, para [0038] - [0040]).
Li and Ajanovic do not explicitly teach but Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Ajanovic and Shanbhogue since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li, Ajanovic and Shanbhogue are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Shanbhogue’s error field in Li would alert an error.
As to claim 2, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an interrupt trigger for the EP of the PCIe system (para [0040]).
As to claim 3, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an indication of a fatal error at the RC of the PCIe system (para [0039]).
As to claim 4, 15, and 19, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a reset status at the RC (para [0076]).
As to claims 5 and 20, Ajanovic teaches: The apparatus of claim 4, wherein the PCIe VDM message comprises a notification that the RC of the PCIe system is resetting (para [00114] & [00116]).
As to claim 6, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a status of at least one data path (para [0070] & [0087]).
As to claim 7, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a buffer status (para [00117] & [00119]).
As of claim 14, Li teaches: An apparatus configured for an Endpoint (EP)(Figure 15, 1502) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, FAR); and
one or more processors(Figure 15, 1556) configured to:
generate a PCIe Vendor Defined Message (VDM) message for a RC (Root Complex) of the PCIe system(para [0043], PCIe endpoint device 504 includes a PCIe port 524 and a device application layer 526. Device application layer 526 includes a VDM receiver 536 and a VDM generator 538).
Li does not explicitly teach but Ajanovic teaches: wherein the PCIe VDM message comprises information on an error at another EP, having been communicated from the other EP to the EP via a PCIe link. (para [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li and Ajanovic since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Ajanovic are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Ajanovic’s communicating error messages in Li would have improved messaging performance of modified messaging system of Li (Ajanovic, para [0039]).
Li and Ajanovic do not explicitly teach but Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Ajanovic and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Shanbhogue are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Shanbhogue’s error field in Li and Ajanovic would alert an error via VDM.
As to claim 16, Li teaches: An apparatus configured for a Root Complex (RC) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory; and
one or more processors configured to:
process a PCIe Vendor Defined Message (VDM) message from an Endpoint (EP) of the PCIe system, the first PCIe VDM message being received over a PCIe link, and using implicit routing or Route-by-ID, wherein when Route-by-ID is used, the VDM message includes a destination identifier (para [0042] SoC host 502 includes a system a PCIe root complex (RC) 512 and a PCIe root port 514. Host application layer 510 includes a VDM generator 518, and a VDM receiver 520. [0029] FIG. 2 shows a table specifying aspects of Vendor Defined Messages, which use the header format shown in FIG. 3. As defined in PCIe 4.0 section 2.2.8.6, [0030] The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. [0031] If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message. [0033] Bytes 12 through 15 are available for vendor definition.).
Li does not explicitly teach but Ajanovic teaches:
relay, via a PCIe link, a second PCIe VDM message received from another EP to the EP, wherein the PCIe VDM message comprises at least one of: a data path status at the EP, a reset status at the EP, or a buffer status at the EP. (para [0015] and [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li and Ajanovic since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Ajanovic are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Ajanovic’s in-band messages in Li would have improved messaging performance of modified messaging system of Li(Ajanovic, para [0038] - [0040]).
Li and Ajanovic do not explicitly teaches but Shanbhogue teaches using vendor defined portion field in a VDM(Column 9, Lines 15-16, 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Ajanovic and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li, Ajanovic and Shanbhogue are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Shanbhogue’s field in Li and Ajanovic would alert of status via VDM.
As to claim 18, Li teaches: A method for a Root Complex (RC) of a Peripheral Component Interconnect express (PCIe) system, comprising:
generating a PCIe Vendor Defined Message (VDM) message for an EP (Endpoint) of the PCIe system to be sent via a PCIe link and using implicit routing or Routing-by-ID, (para [0042] SoC host 502 includes a system a PCIe root complex (RC) 512 and a PCIe root port 514. Host application layer 510 includes a VDM generator 518, and a VDM receiver 520. [0029] FIG. 2 shows a table specifying aspects of Vendor Defined Messages, which use the header format shown in FIG. 3. As defined in PCIe 4.0 section 2.2.8.6, [0030] The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. [0031] If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message. [0033] Bytes 12 through 15 are available for vendor definition.).
Li does not explicitly teaches but Ajanovic teaches wherein the PCIe VDM message comprises information on an error at the RC and optionally including a dying gasp indication (para [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li and Ajanovic since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Ajanovic are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Ajanovic’s communicating error messages in Li would have improved messaging performance of modified messaging system of Li (Ajanovic, para [0039]).
Li and Ajanovic do not explicitly teaches but Shanbhogue teaches using vendor defined portion field in a VDM(Column 9, Lines 15-16, 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Ajanovic and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li, Ajanovic and Shanbhogue are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Shanbhogue’s field in Li and Ajanovic would alert of status via VDM.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Li(US 2019/0235612) and Ajanovic(WO 03019394).
As to claim 8, Li teaches an apparatus configured for an Endpoint (EP)(Figure 15, 1502) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, FAR); and
one or more processors(Figure 15, 1556) configured to:
process a first PCIe Vendor Defined Message (VDM) message from a RC (Root Complex) of the PCIe system and a second PCIe VDM message from another EP of the PCIe system, the first PCIe VDM message being received over a PCIe link(para [0043], PCIe endpoint device 504 includes a PCIe port 524 and a device application layer 526. Device application layer 526 includes a VDM receiver 536 and a VDM generator 538).
Li does not explicitly teaches but Ajanovic teaches a second VDM PCIe VDM message from another EP pf the PCIe system and relay the second PCIe VDM message received from the other EP to the EP. (Ajanovic, para [0015] and [0020], “each of the elements 102, 104, 108 and 110 are communicatively coupled to at least one other element through a communication link 112 supporting one or more EGIO communication channel(s) via the EGIO interface 106.”; “In the EGIO architecture disclosed herein, switches selectively couple end-points within and between EGIO hierarchies and/or domains. According to one example implementation, an EGIO switch 108 has at least one upstream port (i.e., directed towards the root complex 104), and at least one downstream port. According to one implementation, a switch 108 distinguishes one port (i.e., a port of an interface or the interface 106 itself) which is closest to the root complex as the upstream port, while all other port(s) are downstream ports. According to one implementation, switches 108 appear to configuration software (e.g., legacy configuration software) as a PCI-to-PCI bridge, and use PCI bridge mechanisms for routing transactions.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li and Ajanovic since both are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts because both Li and Ajanovic are directed to PCIe link messaging from Root Complex to End Points. A person of ordinary skill in the art would have recognized the use of Ajanovic’s relaying messages from EP to EP in Li would have improved performance of the modified messaging system of Li (Ajanovic, para [0015] and [0020])
As to claim 9, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an interrupt trigger for the EP of the PCIe system (para [0040]).
As to claim 10, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a reset status at the RC (para [0076]).
As to claim 11, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an indication of a fatal error at the RC of the PCIe system (para [0039]).
As to claim 12, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a status of at least one data path (para [0070] & [0087]).
As to claim 13, Ajanovic teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a buffer status (para [00117] & [00119]).
Conclusion
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/NIMESH G PATEL/Primary Examiner, Art Unit 2176