Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
35 U.S.C 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li(US 2019/0235612), Haraden (US 2009/0292960) and Shanbhogue(US 9,652,388).
As to claim 1, Li teaches an apparatus configured for a Root Complex (RC)(Figure 15, PCIE RC) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, Memory); and
one or more processors(Figure 15, Cores) configured to:
generate an in-band PCIe Vendor Defined Message (VDM) message for an Endpoint (EP) of the PCIe system(para [0042] SoC host 502 includes a system a PCIe root complex (RC) 512 and a PCIe root port 514. Host application layer 510 includes a VDM generator 518, and a VDM receiver 520. [0029] FIG. 2 shows a table specifying aspects of Vendor Defined Messages, which use the header format shown in FIG. 3. As defined in PCIe 4.0 section 2.2.8.6, [0030] The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. [0031] If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. VDM messages inherently are in-band).
Li does not specifically teach the VDM message comprise information on an error at the RC and information on a reset status of the RC included in in vendor defined portion of a VDM header occupying bytes 12-15 of the VDM header
However, Li teaches in [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message and in [0033] Bytes 12 through 15 are available for vendor definition.
Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
Haraden teaches a system uses available undefined space in which additional transaction information that uniquely identifies a PCI transaction in error, and what caused the error. This additional information requires no additional system resources or bandwidth as it us unused reserved bytes of the PCIE standard message(Paragraph 27, An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error(Paragraph 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Haraden and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts to have a VDM message comprise information on an error at the RC and information on a reset status of the RC included in in a vendor defined portion of a VDM header occupying bytes 12-15 of the VDM header because they are directed to PCIe link messaging between Root Complex to End Points so that error information and reset status of components can be communicated without wasting additional bandwidth as it using unused reserved bytes of the PCIE standard VDM message.
As to claim 2, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an interrupt trigger for the EP of the PCIe system (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 3, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an indication of a fatal error at the RC of the PCIe system (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 4, 15, and 19, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a reset status at the RC (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claims 5 and 20, Haraden teaches: The apparatus of claim 4, wherein the PCIe VDM message comprises a notification that the RC of the PCIe system is resetting (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 6, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a status of at least one data path (para [23] The advanced error reporting (AER) registers 122 could include, for example, registers such as: an uncorrectable error status register, an uncorrectable error mask register, an uncorrectable error severity register, a correctable error status register, a correctable error mask register, an advanced error capabilities and control register).
As to claim 7, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a buffer status (para [23] The advanced error reporting (AER) registers 122 could include, for example, registers such as: an uncorrectable error status register, an uncorrectable error mask register, an uncorrectable error severity register, a correctable error status register, a correctable error mask register, an advanced error capabilities and control register).
As to claim 8, Li teaches an apparatus configured for an Endpoint (EP)(Figure 15, 1502) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, FAR); and
one or more processors(Figure 15, 1556) configured to:
process a first PCIe Vendor Defined Message (VDM) message from a RC (Root Complex) of the PCIe system, the first PCIe VDM message being received over a PCIe link(para [0043], PCIe endpoint device 504 includes a PCIe port 524 and a device application layer 526. Device application layer 526 includes a VDM receiver 536 and a VDM generator 538).
Li does not explicitly teach a second VDM PCIe VDM message from another EP pf the PCIe system and relay the second PCIe VDM message received from the other EP to the EP, wherein the first PCIe VDM message comprises information on a status of the RC in a vendor defined portion of a VDM header.
However, Li teaches in [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message and in [0033] Bytes 12 through 15 are available for vendor definition.
Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
Haraden teaches a system uses available undefined space in which additional transaction information that uniquely identifies a PCI transaction in error, and what caused the error. This additional information requires no additional system resources or bandwidth as it us unused reserved bytes of the PCIE standard message(Paragraph 27, An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error(Paragraph 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Haraden and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts to have a second VDM PCIe VDM message from another EP pf the PCIe system and relay the second PCIe VDM message received from the other EP to the EP, wherein the first PCIe VDM message comprises information on a status of the RC in a vendor defined portion of a VDM header because they are directed to PCIe link messaging between Root Complex to End Points so that error information and reset status of components can be communicated without wasting additional bandwidth as it using unused reserved bytes of the PCIE standard VDM message.
As to claim 9, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an interrupt trigger for the EP of the PCIe system (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 10, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a reset status at the RC (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 11, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises an indication of a fatal error at the RC of the PCIe system (para [0025], An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error).
As to claim 12, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a status of at least one data path (para [23] The advanced error reporting (AER) registers 122 could include, for example, registers such as: an uncorrectable error status register, an uncorrectable error mask register, an uncorrectable error severity register, a correctable error status register, a correctable error mask register, an advanced error capabilities and control register).
As to claim 13, Haraden teaches: The apparatus of claim 1, wherein the PCIe VDM message comprises information on a buffer status (para [23] The advanced error reporting (AER) registers 122 could include, for example, registers such as: an uncorrectable error status register, an uncorrectable error mask register, an uncorrectable error severity register, a correctable error status register, a correctable error mask register, an advanced error capabilities and control register).
As of claim 14, Li teaches: An apparatus configured for an Endpoint (EP)(Figure 15, 1502) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory(Figure 15, FAR); and
one or more processors(Figure 15, 1556) configured to:
generate a PCIe Vendor Defined Message (VDM) message for a RC (Root Complex) of the PCIe system(para [0043], PCIe endpoint device 504 includes a PCIe port 524 and a device application layer 526. Device application layer 526 includes a VDM receiver 536 and a VDM generator 538).
Li does not explicitly teach wherein the PCIe VDM message comprises information on an error at another EP, the error information being included in a vendor-defined portion of a VDM header occupying bytes 12-15 of the VDM header and having been communicated from the other EP to the EP via a PCIe link prior to the generation of the PCIe message.
However, Li teaches in [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message and in [0033] Bytes 12 through 15 are available for vendor definition.
Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
Haraden teaches a system uses available undefined space in which additional transaction information that uniquely identifies a PCI transaction in error, and what caused the error. This additional information requires no additional system resources or bandwidth as it us unused reserved bytes of the PCIE standard message(Paragraph 27, An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error(Paragraph 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Haraden and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts to have the PCIe VDM message comprises information on an error at another EP, the error information being included in a vendor-defined portion of a VDM header occupying bytes 12-15 of the VDM header and having been communicated from the other EP to the EP via a PCIe link prior to the generation of the PCIe message because they are directed to PCIe link messaging between Root Complex to End Points so that error information and reset status of components can be communicated without wasting additional bandwidth as it using unused reserved bytes of the PCIE standard VDM message.
As to claim 16, Li teaches: An apparatus configured for a Root Complex (RC) of a Peripheral Component Interconnect express (PCIe) system, comprising:
a memory; and
one or more processors configured to:
process a PCIe Vendor Defined Message (VDM) message from an Endpoint (EP) of the PCIe system, the first PCIe VDM message being received over a PCIe link, and using implicit routing or Route-by-ID, wherein when Route-by-ID is used, the VDM message includes a destination identifier (para [0042] SoC host 502 includes a system a PCIe root complex (RC) 512 and a PCIe root port 514. Host application layer 510 includes a VDM generator 518, and a VDM receiver 520. [0029] FIG. 2 shows a table specifying aspects of Vendor Defined Messages, which use the header format shown in FIG. 3. As defined in PCIe 4.0 section 2.2.8.6, [0030] The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. [0031] If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message. [0033] Bytes 12 through 15 are available for vendor definition.).
Li does not explicitly teach relay, via a PCIe link, a second PCIe VDM message received from another EP to the EP, wherein the second PCIe VDM message comprises, in a vendor defined portion of a VDM header occupying bytes 12-15 of the VDM header, at least one of: a data path status at the EP, a reset status at the EP, or a buffer status at the EP.
However, Li teaches in [0032] Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG®, of the vendor defining the Message and in [0033] Bytes 12 through 15 are available for vendor definition.
Shanbhogue teaches an error present field in a VDM(Column 9, Lines 15-16, 30).
Haraden teaches a system uses available undefined space in which additional transaction information that uniquely identifies a PCI transaction in error, and what caused the error. This additional information requires no additional system resources or bandwidth as it us unused reserved bytes of the PCIE standard message(Paragraph 27, An indication of which transaction caused the error is stored in a secondary location 124. An error message packet that includes the error data and the indication of which transaction caused the error is assembled and is transmitted to the root complex 110. Based on the data in the error message packet, the root complex 110 will take a preselected action, such as sending a vendor-defined message from the root complex 110 to the endpoint 120. In response, the endpoint 120 could be configured to take such actions as resetting an error information, re-executing a previous operation, or causing a fatal error(Paragraph 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li, Haraden and Shanbhogue since they are directed to the same field of endeavor, thus analogous arts. One would be motivated to combine these prior arts relay, via a PCIe link, a second PCIe VDM message received from another EP to the EP, wherein the second PCIe VDM message comprises, in a vendor defined portion of a VDM header occupying bytes 12-15 of the VDM header, at least one of: a data path status at the EP, a reset status at the EP, or a buffer status at the EP because they are directed to PCIe link messaging between Root Complex to End Points so that error information and reset status of components can be communicated without wasting additional bandwidth as it using unused reserved bytes of the PCIE standard VDM message.
Allowable Subject Matter
Claims 18-20 are allowed.
Response to Arguments
Applicant’s arguments have been considered. However, clams 1-16 remain rejected due to the new ground of rejections, necessitated by the amendments to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15.
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/NIMESH G PATEL/Primary Examiner, Art Unit 2176
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