DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
10/23/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 04/17/2026. Claims
1-8 and 10-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,3-8,11,13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu et al. (US 20140297919 A1) in view of Busaba et al. (US 9507628 B1) and further in view of Veal et al. (US 20190050341 A1) hereinafter Nachimuthu and Busaba and Veal.
Regarding claim 1, Nachimuthu teaches A device comprising: A cache media; a storage media; a communication interface; and at least one control circuit configured to: (“FIG. 1 shows a memory hierarchy including a set of internal processor caches 120, "near memory" acting as a far memory cache 121, which may include both internal cache(s) 106 and external caches 107-109, and "far memory" 122”) (paragraph [0049] line 2-3)
(“far memory 122 may be placed on a memory bus and may communicate directly with a memory controller that, in turn, communicates directly with the processor 100”) (paragraph [0070] line 3-4) (i.e. Fig 1 illustrates processor 100 comprises cashes 120, near memory 121, far memory 122 with a memory bus to communicate with controller)
receive, using the communication interface, a first memory access request to access a portion of the storage media; receive, using the communication interface, a second memory access request to access the portion of the storage media; access, based on the first memory access request, the portion of the storage media; (“In response to a memory access request, the MSC controller 124 may determine (depending on the mode of operation specified in the range registers 336) whether the request can be serviced from the NM acting as cache for FM 150B or whether the request must be sent to the NVRAM controller 332, which may then service the request from the far memory (FM) portion 151B of the NVRAM 142”) (paragraph [0102] line 4-7)
(“In the illustrated embodiment, the MSC controller 124 includes a set of range registers 336 which specify the mode of operation in use for the NM acting as a far memory cache 150B (e.g., write-back caching mode, near memory bypass mode, etc, described above). In the illustrated embodiment, DRAM 144 is used as the memory technology for the NM acting as cache for far memory 150B”) (paragraph [0102] line 1-4)
(i.e. Fig 3 illustrates in response to a memory access request the controller 124 may determine upon depending on the mode of operation whether the request can be serviced from the cache for FM 150B or whether the request must be sent to the NVRAM controller 332 to service request from far memory (FM) portion 151B of the NVRAM 142 where mode of operation may include write-back caching mode, near memory bypass mode etc. In other words, access requests can be in different operation mode from cache portion or directly to far memory portion)
and access, based on the second memory access request, a portion of the cache media. (“When acting in near memory direct access mode, all or portions of the near memory as system memory 151A are directly visible to software and form part of the SPA space”) (paragraph [0092] line 1-2) (i.e. Fig 3 illustrates when acting in near memory direct access mode all or portions of the near memory as system memory 151A or cache are directly visible to software for access request)
Nachimuthu teaches access method for cache memory and storage device.
However, Nachimuthu does not explicitly teach memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
On the other hand, Busaba which also relates to access method for cache
memory and storage device teaches memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
(see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations based on memory access protocol 104)
Both Nachimuthu and Busaba relate to access method for memory
and storage device. Nachimuthu teaches access method for cache memory and storage
device. Also, Nachimuthu does not teach memory access based on protocol. On
the other hand, Busaba teaches access method for cache memory and storage
device and teach memory access request 102 is directed to two or more memory locations based on memory access protocol 104. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu with Busaba to specify teaches access method for cache memory and storage device and memory access request 102 is directed to two or more memory locations based on memory access protocol 104 providing memory protocols for various environments, including virtual memory environments and hardware TM environments provide enhanced performance of the applicable computer system as mentioned in col 1, line 26-30.
Nachimuthu in view of Busaba teaches access method for cache memory and storage device above. However, Nachimuthu – Busaba combination does not explicitly teach wherein the storage access protocol is configured to access the portion of the storage media in relatively larger addressable units, and the memory access protocol is configured to access data of the portion of the storage media in relatively smaller addressable units using the portion of the cache media.
On the other hand, Veal which also relates to access method for cache
memory and storage device teaches wherein the storage access protocol is configured to access (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
the portion of the storage media in relatively larger addressable units, and (See Fig 10 paragraph [0044], illustrates SSD 103 may include block-addressed media 105 which maybe NAND based storage media. In other words, storage media is larger addressable unit)
the memory access protocol is configured to access data of (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
the portion of the storage media in relatively smaller addressable units using the portion of the cache media (See Fig 10 paragraph [0045], illustrates write buffer 109 may have byte granularity for write access. In other words, cache buffer maybe smaller addressable unit)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu with Busaba for the reasons set forth above. In addition, Nachimuthu, Busaba and Veal are considered analogous
arts, because they all relate to access method for cache memory and storage device.
Nachimuthu – Busaba combination teaches access method for cache memory and
storage device based on memory access protocol. On the other hand, Veal teaches access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu - Busaba combination with Veal to specify access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access providing improvement in I/O performance as mentioned in paragraph [0034].
Regarding claim 3, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 1, wherein the at least one control circuit is configured to write at least a portion of the portion of the cache media to the portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 1, wherein the at least one control circuit is configured to write at least a portion of the portion of the cache media to the portion of the storage media. (“the MSC controller 512 notices that the data is not current in PCM far memory 530 and will thus retrieve it from near memory 518 and send it to the PCM controller 521. The PCM controller 521 looks up the PDA for the system memory address and then writes the data to the PCM far memory 530”) (paragraph [0158] line 5-7) (i.e. Fig 5A illustrates when MSC controller 512 notices that the data is not current in PCM far memory 530 and then will thus retrieve it from near memory 518 and send it to the PCM controller 521 which then writes the data to the PCM far memory 530. In other words, data from near memory or a portion of cache is written to a portion of far memory storage)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 1, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to:
receive, using the communication interface, a storage access request to access a second portion of the storage media; and access, based on the storage access request, the second portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 1, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to:
receive, using the communication interface, a storage access request to access a second portion of the storage media; and access, based on the storage access request, the second portion of the storage media. (“the I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states, such as secure data, encryption keys, platform configuration information and the like. In one embodiment, these system persistent states are stored in a TMP NVRAM 173 and accessed via NVRAM controller 332”) (paragraph [0158] line 5-7) (i.e. Fig 3 illustrates I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states which is stored in TMP NVRAM 173. In other words, TPM NVRAM which is another portion of NVRAM storage is accessed by TPM control)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 4.
Regarding claim 5, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 4. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 4, wherein the at least one control circuit is configured to: receive the first memory access request using the memory access protocol and receive the storage access request using the storage access protocol.
On the other hand, Busaba which also relates to access method for cache memory and storage device teaches The device of claim 4, wherein the at least one control circuit is configured to: receive the first memory access request using the memory access protocol and receive the storage access request using the storage access protocol. (see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations when received based on memory access protocol 104)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 5.
Regarding claim 6, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 4. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 4, wherein the at least one control circuit is configured to: operate the portion of the cache media and the first portion of the storage media as a first logical device; and operate the second portion of the storage media as a second logical device
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 4, wherein the at least one control circuit is configured to: operate the portion of the cache media and the first portion of the storage media as a first logical device; and operate the second portion of the storage media as a second logical device. (“a notebook computer is configured with a near memory and a PCMS device which performs the role of both a far memory and a mass storage device (i.e., which is logically partitioned to perform these roles as shown in FIG. 3)”) (paragraph [0082] line 1-4) (i.e. Fig 3 illustrates PCMS device which performs the role of both a far memory and a mass storage device can be logically partitioned to perform different roles)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 6.
Regarding claim 7, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 1, wherein the at least one control circuit is configured to: receive, using the communication interface, a storage access request to access the portion of the storage media; and access, based on the storage access request, the portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 1, wherein the at least one control circuit is configured to: receive, using the communication interface, a storage access request to access the portion of the storage media; and access, based on the storage access request, the portion of the storage media. (“the I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states, such as secure data, encryption keys, platform configuration information and the like. In one embodiment, these system persistent states are stored in a TMP NVRAM 173 and accessed via NVRAM controller 332”) (paragraph [0158] line 5-7) (i.e. Fig 3 illustrates I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states which is stored in TMP NVRAM 173. In other words, TPM NVRAM which is another portion of NVRAM storage is accessed by TPM control)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 7.
Regarding claim 8, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 7. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 7, wherein the at least one control circuit is configured to: receive the first memory access request using the memory access protocol and receive the storage access request using the storage access protocol.
On the other hand, Busaba which also relates to access method for cache memory and storage device teaches The device of claim 7, wherein the at least one control circuit is configured to: receive the first memory access request using the memory access protocol and receive the storage access request using the storage access protocol. (see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations when received based on memory access protocol 104)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 11, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 1, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to write at least a portion of the portion of the cache media to a second portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 1, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to write at least a portion of the portion of the cache media to a second portion of the storage media. (“the MSC controller 512 notices that the data is not current in PCM far memory 530 and will thus retrieve it from near memory 518 and send it to the PCM controller 521. The PCM controller 521 looks up the PDA for the system memory address and then writes the data to the PCM far memory 530”) (paragraph [0158] line 5-7) (i.e. Fig 5A illustrates MSC controller 512 notices that the data is not current in PCM far memory 530 and will thus retrieve it from near memory 518 or cache and send it to the PCM controller 521 of far memory or storage where it write data in far memory 530. In other words, controller is configured to send and write data from near memory or cache to far memory or storage)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 1 is equally applicable to claim 11.
Regarding claim 13, Nachimuthu teaches A device comprising: a memory media; a storage media; a communication interface; and at least one control circuit configured to: (“FIG. 1 shows a memory hierarchy including a set of internal processor caches 120, "near memory" acting as a far memory cache 121, which may include both internal cache(s) 106 and external caches 107-109, and "far memory" 122”) (paragraph [0049] line 2-3)
(“far memory 122 may be placed on a memory bus and may communicate directly with a memory controller that, in turn, communicates directly with the processor 100”) (paragraph [0070] line 3-4) (i.e. Fig 1 illustrates processor 100 comprises cashes 120, near memory 121, far memory 122 with a memory bus to communicate with controller)
receive, using the communication interface, a memory access request to access a portion of the memory media; access, based on the memory access request, the portion of the storage media; and write the portion of the memory media to a portion of the storage media. (“In response to a memory access request, the MSC controller 124 may determine (depending on the mode of operation specified in the range registers 336) whether the request can be serviced from the NM acting as cache for FM 150B or whether the request must be sent to the NVRAM controller 332, which may then service the request from the far memory (FM) portion 151B of the NVRAM 142”) (paragraph [0102] line 4-7)
(“In the illustrated embodiment, the MSC controller 124 includes a set of range registers 336 which specify the mode of operation in use for the NM acting as a far memory cache 150B (e.g., write-back caching mode, near memory bypass mode, etc, described above). In the illustrated embodiment, DRAM 144 is used as the memory technology for the NM acting as cache for far memory 150B”) (paragraph [0102] line 1-4)
(i.e. Fig 3 illustrates in response to a memory access request the controller 124 may determine upon depending on the mode of operation whether the request can be serviced from the cache for FM 150B or whether the request must be sent to the NVRAM controller 332 to service request from far memory (FM) portion 151B of the NVRAM 142 where mode of operation may include write-back caching mode, near memory bypass mode etc. In other words, access requests can be in different operation mode from cache portion or directly to far memory portion)
Nachimuthu teaches access method for cache memory and storage device.
However, Nachimuthu does not explicitly teach memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
wherein the communication interface is configured to handle requests based on the memory access protocol and requests based on a storage access protocol
On the other hand, Busaba which also relates to access method for cache
memory and storage device teaches memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
(see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations based on memory access protocol 104)
wherein the communication interface is configured to handle requests based on the memory access protocol and requests based on a storage access protocol (see Fig 9, col 7 line 53-60, illustrates computer system 900 operates over a communication fabric 902 along with I/O interface 914 for passing data or control information, in other words communication interface is configured to handle data and control requests from processor to storage device using access protocol)
Both Nachimuthu and Busaba relate to access method for memory
and storage device. Nachimuthu teaches access method for cache memory and storage
device. Also, Nachimuthu does not teach memory access based on protocol. On
the other hand, Busaba teaches access method for cache memory and storage
device and teach memory access request 102 is directed to two or more memory locations based on memory access protocol 104 and computer system 900 operates over a communication fabric 902 along with I/O interface 914 for passing data or control information, in other words communication interface is configured to handle data and control requests from processor to storage device using access protocol. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu with Busaba to specify teaches access method for cache memory and storage device and memory access request 102 is directed to two or more memory locations based on memory access protocol 104 and computer system 900 operates over a communication fabric 902 along with I/O interface 914 for passing data or control information, in other words communication interface is configured to handle data and control requests from processor to storage device using access protocol providing memory protocols for various environments, including virtual memory environments and hardware TM environments provide enhanced performance of the applicable computer system as mentioned in col 1, line 26-30.
Nachimuthu in view of Busaba teaches access method for cache memory and storage device above. However, Nachimuthu – Busaba combination does not explicitly teach wherein the storage access protocol is configured to access a portion of the storage media in relatively larger addressable units, and the memory access protocol is configured to access data of the portion of the storage media in relatively smaller addressable units using the portion of the memory media
On the other hand, Veal which also relates to access method for cache
memory and storage device teaches wherein the storage access protocol is configured to access (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
a portion of the storage media in relatively larger addressable units, and (See Fig 10 paragraph [0044], illustrates SSD 103 may include block-addressed media 105 which maybe NAND based storage media. In other words, storage media is larger addressable unit)
the memory access protocol is configured to access data of (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
the portion of the storage media in relatively smaller addressable units using the portion of the cache media (See Fig 10 paragraph [0045], illustrates write buffer 109 may have byte granularity for write access. In other words, cache buffer maybe smaller addressable unit)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu with Busaba for the reasons set forth above. In addition, Nachimuthu, Busaba and Veal are considered analogous
arts, because they all relate to access method for cache memory and storage device.
Nachimuthu – Busaba combination teaches access method for cache memory and
storage device based on memory access protocol. On the other hand, Veal teaches access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu - Busaba combination with Veal to specify access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access providing improvement in I/O performance as mentioned in paragraph [0034].
Regarding claim 14, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 13. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 13, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to: receive, using the communication interface, a storage access request to access a second portion of the storage media; and access, based on the storage access request, the second portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 13, wherein: the portion of the storage media is a first portion of the storage media; and the at least one control circuit is configured to: receive, using the communication interface, a storage access request to access a second portion of the storage media; and access, based on the storage access request, the second portion of the storage media. (“the I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states, such as secure data, encryption keys, platform configuration information and the like. In one embodiment, these system persistent states are stored in a TMP NVRAM 173 and accessed via NVRAM controller 332”) (paragraph [0158] line 5-7) (i.e. Fig 3 illustrates I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states which is stored in TMP NVRAM 173. In other words, TPM NVRAM which is another portion of NVRAM storage is accessed by TPM control)
Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 13. However, Nachimuthu - Busaba - Veal combination does not explicitly teach memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
On the other hand, Busaba which also relates to access method for cache
memory and storage device teaches memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
(see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations based on memory access protocol 104)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 13 is equally applicable to claim 14.
Regarding claim 15, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 14. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 14, wherein the at least one control circuit is configured to: operate the portion of the memory media and the first portion of the storage media as a first logical device; and operate the second portion of the storage media as a second logical device
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 14, wherein the at least one control circuit is configured to: operate the portion of the memory media and the first portion of the storage media as a first logical device; and operate the second portion of the storage media as a second logical device. (“a notebook computer is configured with a near memory and a PCMS device which performs the role of both a far memory and a mass storage device (i.e., which is logically partitioned to perform these roles as shown in FIG. 3)”) (paragraph [0082] line 1-4) (i.e. Fig 3 illustrates PCMS device which performs the role of both a far memory and a mass storage device can be logically partitioned to perform different roles)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 13 is equally applicable to claim 15.
Regarding claim 16, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 14. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 14, wherein: the portion of the memory media is a first portion of the memory media; and the at least one control circuit is configured to access, based on the storage access request, a second portion of the memory media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 14, wherein: the portion of the memory media is a first portion of the memory media; and the at least one control circuit is configured to access, based on the storage access request, a second portion of the memory media. (“the I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states, such as secure data, encryption keys, platform configuration information and the like. In one embodiment, these system persistent states are stored in a TMP NVRAM 173 and accessed via NVRAM controller 332”) (paragraph [0158] line 5-7) (i.e. Fig 3 illustrates I/O subsystem 115 is coupled to a TPM control 334 to control access to system persistent states which is stored in TMP NVRAM 173. In other words, TPM NVRAM which is another portion of NVRAM storage is accessed by TPM control)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 13 is equally applicable to claim 16.
Regarding claim 17, Nachimuthu teaches A device comprising: media comprising cache media and storage media; a communication interface; and at least one control circuit configured to: (“FIG. 1 shows a memory hierarchy including a set of internal processor caches 120, "near memory" acting as a far memory cache 121, which may include both internal cache(s) 106 and external caches 107-109, and "far memory" 122”) (paragraph [0049] line 2-3)
(“far memory 122 may be placed on a memory bus and may communicate directly with a memory controller that, in turn, communicates directly with the processor 100”) (paragraph [0070] line 3-4) (i.e. Fig 1 illustrates processor 100 comprises cashes 120, near memory 121, far memory 122 with a memory bus to communicate with controller)
receive, using the communication interface, a first memory access request; access, based on the first memory access request, a first portion of the media; receive, using the communication interface, a first storage access request; access, based on the first storage access request, a second portion of the media; receive, using the communication interface, a second memory access request; receive, using the communication interface, a second storage access request; (“In response to a memory access request, the MSC controller 124 may determine (depending on the mode of operation specified in the range registers 336) whether the request can be serviced from the NM acting as cache for FM 150B or whether the request must be sent to the NVRAM controller 332, which may then service the request from the far memory (FM) portion 151B of the NVRAM 142”) (paragraph [0102] line 4-7)
(“In the illustrated embodiment, the MSC controller 124 includes a set of range registers 336 which specify the mode of operation in use for the NM acting as a far memory cache 150B (e.g., write-back caching mode, near memory bypass mode, etc, described above). In the illustrated embodiment, DRAM 144 is used as the memory technology for the NM acting as cache for far memory 150B”) (paragraph [0102] line 1-4)
(i.e. Fig 3 illustrates in response to a memory access request the controller 124 may determine upon depending on the mode of operation whether the request can be serviced from the cache for FM 150B or whether the request must be sent to the NVRAM controller 332 to service request from far memory (FM) portion 151B of the NVRAM 142 where mode of operation may include write-back caching mode, near memory bypass mode etc. In other words, access requests can be in different operation mode from cache portion or directly to far memory portion)
access, based on the second memory access request, a third portion of the media; and access, based on the second storage access request, the third portion of the media. (“I/O subsystem 115 further decodes the address to determine whether the address points to NVRAM mass storage 152A, BIOS NVRAM 172, or other non-storage or storage I/P devices. If this address points to NVRAM mass storage 152A or BIOS NVRAM 172, I/O subsystem 115 forwards the request to NVRAM controller 332”) (paragraph [0104] line 12-15) (i.e. Fig 3 illustrates I/O subsystem 115 further decodes the address to determine whether the address points to NVRAM mass storage 152A, BIOS NVRAM 172 and if the address points to BIOS NVRAM 172 a portion of mass storage 152A, I/O subsystem 115 forwards the request to NVRAM controller 332. In other words, if address points to a third portion of mass storage, access request is forwarded and executed to third portion)
Nachimuthu teaches access method for cache memory and storage device.
However, Nachimuthu does not explicitly teach memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
On the other hand, Busaba which also relates to access method for cache
memory and storage device teaches memory access request based on a storage access protocol
memory access request being associated with the storage access protocol
(see Fig 2, col 2 line 43-53, illustrates memory access request 102 is directed to two or more memory locations based on memory access protocol 104)
Both Nachimuthu and Busaba relate to access method for memory
and storage device. Nachimuthu teaches access method for cache memory and storage
device. Also, Nachimuthu does not teach memory access based on protocol. On
the other hand, Busaba teaches access method for cache memory and storage
device and teach memory access request 102 is directed to two or more memory locations based on memory access protocol 104. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu with Busaba to specify teaches access method for cache memory and storage device and memory access request 102 is directed to two or more memory locations based on memory access protocol 104 providing memory protocols for various environments, including virtual memory environments and hardware TM environments provide enhanced performance of the applicable computer system as mentioned in col 1, line 26-30.
Nachimuthu in view of Busaba teaches access method for cache memory and storage device above. However, Nachimuthu – Busaba combination does not explicitly teach wherein the storage access protocol is configured to access a portion of the storage media in relatively larger addressable units, and the memory access protocol is configured to access data of the portion of the storage media in relatively smaller addressable units using the portion of the memory media
On the other hand, Veal which also relates to access method for cache
memory and storage device teaches wherein the storage access protocol is configured to access (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
a portion of the storage media in relatively larger addressable units, and (See Fig 10 paragraph [0044], illustrates SSD 103 may include block-addressed media 105 which maybe NAND based storage media. In other words, storage media is larger addressable unit)
the memory access protocol is configured to access data of (See Fig 6 paragraph [0034], illustrates NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media)
the portion of the storage media in relatively smaller addressable units using the portion of the cache media (See Fig 10 paragraph [0045], illustrates write buffer 109 may have byte granularity for write access. In other words, cache buffer maybe smaller addressable unit)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu with Busaba for the reasons set forth above. In addition, Nachimuthu, Busaba and Veal are considered analogous
arts, because they all relate to access method for cache memory and storage device.
Nachimuthu – Busaba combination teaches access method for cache memory and
storage device based on memory access protocol. On the other hand, Veal teaches access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu - Busaba combination with Veal to specify access method for cache memory and storage device and NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media and SSD 103 may include block-addressed media 105 which maybe NAND based storage media and write buffer 109 may have byte granularity for write access providing improvement in I/O performance as mentioned in paragraph [0034].
Regarding claim 18, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 17. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 17, wherein: the first portion of the media comprises a portion of the cache media; and the at least one control circuit is configured to write data from the portion of the cache media to a portion of the storage media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 17, wherein: the first portion of the media comprises a portion of the cache media; and the at least one control circuit is configured to write data from the portion of the cache media to a portion of the storage media. (“the MSC controller 512 notices that the data is not current in PCM far memory 530 and will thus retrieve it from near memory 518 and send it to the PCM controller 521. The PCM controller 521 looks up the PDA for the system memory address and then writes the data to the PCM far memory 530”) (paragraph [0158] line 5-7) (i.e. Fig 5A illustrates MSC controller 512 notices that the data is not current in PCM far memory 530 and will thus retrieve it from near memory 518 or cache and send it to the PCM controller 521 of far memory or storage where it write data in far memory 530. In other words, controller is configured to send and write data from near memory or cache to far memory or storage)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 17 is equally applicable to claim 18.
Regarding claim 20, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 17. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 17, wherein the at least one control circuit is configured to access, based on the first storage access request, a portion of the cache media
On the other hand, Nachimuthu which also relates to access method for cache
memory and storage device teaches The device of claim 17, wherein the at least one control circuit is configured to access, based on the first storage access request, a portion of the cache media. (“When acting in near memory direct access mode, all or portions of the near memory as system memory 151A are directly visible to software and form part of the SPA space”) (paragraph [0092] line 1-2) (i.e. Fig 3 illustrates when acting in near memory direct access mode all or portions of the near memory as system memory 151A or cache are directly visible to software for access request)
The same motivation that was utilized for combining Nachimuthu – Busaba
combination with Veal as set forth in claim 17 is equally applicable to claim 20.
Claim(s) 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu in view of Busaba and further in view of Veal and further in view of Benhanokh et al. (US 20210216459 A1) hereinafter Benhanokh.
Regarding claim 2, Nachimuthu teaches The device of claim 1, wherein: the portion of the cache media comprises a first cache; and the at least one control circuit is configured to access, based on the first memory access request, the portion of the storage media by:
reading data from the portion of the storage media; storing the data in a second cache; and (“Upon receiving the requested data from the PCM far memory 530, the PCM controller 521 will return the requested data to the MSC controller 512 which will store the data in the MSC near memory 518 and also send the data to the requesting CPU core 501”) (paragraph [0157] line 7-9) (i.e. Fig 5A illustrates upon receiving the requested data from the PCM far memory 530 the PCM controller 521 will return the requested data to the MSC controller 512 which will store the data in the MSC near memory 518 also known as cache)
Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach loading at least a portion of the data from the second cache.
On the other hand, Benhanokh which also relates to access method for cache memory and storage device teaches loading at least a portion of the data from the second cache. (“If it is determined that the data portion is in the cache, then in a step 1208 a metadata response may be sent back to the host system that includes the state and location of the data portion, as well as the data portion itself”) (paragraph [0163] line 5-8) (i.e. Fig 12 illustrates in step 1208 if it is determined that the data portion is in the cache, then a metadata response may be sent back to the host system that includes the state and location of the data portion as well as the data portion itself. In other words, a portion of data maybe loading to host when it is determined that data portion is in the cache)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu – Busaba combination with Veal for the reasons set forth in claim 1 above. In addition, Nachimuthu, Busaba, Veal and Benhanokh are considered analogous arts, because they all relate to access method for cache memory and storage device. Nachimuthu – Busaba - Veal combination teaches access method for cache memory and storage device based on memory access protocol. Also, Nachimuthu - Busaba - Veal combination does not teach portion of data maybe loading to host when it is determined that data portion is in the cache. On the other hand, Benhanokh teaches access method for cache memory and storage device and teach portion of data maybe loading to host when it is determined that data portion is in the cache. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu - Busaba - Veal combination with Benhanokh to specify teaches access method for cache memory and storage device and teach portion of data maybe loading to host when it is determined that data portion is in the cache providing a method that includes receiving an instruction to read metadata for a data portion in association with a read request made by a host application to read the data portion from the storage system as mentioned in paragraph [0004].
Regarding claim 19, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 17. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 17, wherein the at least one control circuit is configured to map the first portion of the media to the second portion of the media.
On the other hand, Benhanokh which also relates to access method for cache memory and storage device teaches The device of claim 17, wherein the at least one control circuit is configured to map the first portion of the media to the second portion of the media. (“Device mapping logic 718 may be configured to map logical addresses of logical storage devices to locations (i.e., physical addresses) within physical storage devices using, e.g., any one or more of tables 762, 772, 772′ and 782, 750”) (paragraph [0113] line 1-2) (i.e. Fig 7 illustrates Device mapping logic 718 may be configured to map logical addresses of logical storage devices to locations within physical storage devices using one of tables)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu – Busaba combination with Veal for the reasons set forth in claim 1 above. In addition, Nachimuthu, Busaba, Veal and Benhanokh are considered analogous arts, because they all relate to access method for cache memory and storage device. Nachimuthu – Busaba - Veal combination teaches access method for cache memory and storage device based on memory access protocol. Also, Nachimuthu - Busaba - Veal combination does not teach portion of data maybe loading to host when it is determined that data portion is in the cache. On the other hand, Benhanokh teaches access method for cache memory and storage device and Device mapping logic circuit may be configured to map logical addresses of logical storage devices to locations within physical storage devices. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu - Busaba - Veal combination with Benhanokh to specify access method for cache memory and storage device and Device mapping logic circuit may be configured to map logical addresses of logical storage devices to locations within physical storage devices providing a method that includes receiving an instruction to read metadata for a data portion in association with a read request made by a host application to read the data portion from the storage system as mentioned in paragraph [0004].
Claim(s) 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu in view of Busaba and further in view of Veal and further in view of HORWICH et al. (US 20210374080 A1) hereinafter HORWICH.
Regarding claim 10, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 7. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 7, wherein the at least one control circuit is configured to perform a coherency operation associated with the portion of the storage media.
On the other hand, HORWICH which also relates to access method for cache memory and storage device teaches The device of claim 7, wherein the at least one control circuit is configured to perform a coherency operation associated with the portion of the storage media. (“In addition to the NVMe protocol, CMX device 100 also provides additional coherency mechanisms and allows the SDM software to include additional extensions (or hints) in host NVMe submissions. In some embodiments, the SDM software 201 initiates data transfers into and out of the NVM 140 by writing submissions into one or more submission queues in a controller memory buffer (CMB) on the CMX device 100”) (paragraph [0082] line 6-10) (i.e. Fig 1 illustrates CMX device 100 also provides additional coherency mechanisms for data transfers into and out of the NVM 140 by writing submissions queues in a controller memory buffer (CMB) on the CMX device 100. In other words, NVM controller performs coherency between host and NVM storage)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu – Busaba combination with Veal for the reasons set forth in claim 1 above. In addition, Nachimuthu, Busaba, Veal and HORWICH are considered analogous arts, because they all relate to access method for cache memory and storage device. Nachimuthu – Busaba - Veal combination teaches access method for cache memory and storage device based on memory access protocol. Also, Nachimuthu - Busaba - Veal combination does not teach portion of data maybe loading to host when it is determined that data portion is in the cache. On the other hand, HORWICH teaches access method for cache memory and storage device and NVM controller performs coherency between host and NVM storage. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu – Busaba - Veal combination with HORWICH to specify access method for cache memory and storage device and NVM controller performs coherency between host and NVM storage providing the performance of data processing systems as mentioned in paragraph [0003].
Regarding claim 12, Nachimuthu in view of Busaba and further in view of Veal teaches access method for cache memory and storage device in claim 1. However, Nachimuthu - Busaba - Veal combination does not explicitly teach The device of claim 1, wherein the at least one control circuit comprises work logic configured to: receive a command; and perform, based on the command, a data movement operation or an operation associated with the portion of the cache media.
On the other hand, HORWICH which also relates to access method for cache memory and storage device teaches The device of claim 1, wherein the at least one control circuit comprises work logic configured to: receive a command; and perform, based on the command, a data movement operation or an operation associated with the portion of the cache media. (“control logic (e.g., logic circuitry) 125 coupled to the bus interface 122 and configurable to control communication of commands (or requests) and data between the CPU and local memory 130, and between local memory 130 and NVM 140”) (paragraph [0073] line 5-7) (i.e. Fig 1 illustrates control logic 125 coupled to the bus interface 122 and configurable to control communication of commands and data between the CPU and local memory 130 and between local memory 130 and NVM 140. In other words, control logic is configured to control command communication and data movement between local memory or cache and storage)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Nachimuthu – Busaba combination with Veal for the reasons set forth in claim 1 above. In addition, Nachimuthu, Busaba, Veal and HORWICH are considered analogous arts, because they all relate to access method for cache memory and storage device. Nachimuthu – Busaba - Veal combination teaches access method for cache memory and storage device based on memory access protocol. Also, Nachimuthu - Busaba - Veal combination does not teach portion of data maybe loading to host when it is determined that data portion is in the cache. On the other hand, HORWICH teaches access method for cache memory and storage device and control logic is configured to control command communication and data movement between local memory or cache and storage. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Nachimuthu – Busaba - Veal combination with HORWICH to specify access method for cache memory and storage device and control logic is configured to control command communication and data movement between local memory or cache and storage providing the performance of data processing systems as mentioned in paragraph [0003].
Response to Arguments
Applicant’s arguments filed on 04/17/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1, 13 and 17 mapping by primary reference Nachimuthu and secondary reference Busaba in page 10 of the response: even if Nachimuthu and Busaba are combined, the resulting system would at most provide protocol-based labeling or routing of requests, but would not yield the claimed arrangement in which protocol selection defines fundamentally different access granularities and access mechanisms-namely, coarse-grained access to storage media versus fine-grained, cache- mediated access to data of that same storage media. The cited combination therefore fails to teach or suggest the amended limitation.
In summary, applicant argued that primary reference Nachimuthu and secondary reference Busaba do not teach amended limitation different access granularities to storage and cache memory. The amendment necessitates adding secondary reference Veal. For further clarification examiner cites portion from Veal. Also, for applicant’s understanding examiner would like to explain the teachings of Veal and examiner’s interpretation in more detail here. See Fig 6 paragraph [0034], Veal teaches NVMe command protocol is used to move or access data between cache memory buffer CMB and storage media. Also See Fig 10 paragraph [0044], Veal teaches SSD 103 may include block-addressed media 105 which maybe NAND based storage media. In other words, storage media is larger addressable unit. Also See Fig 10 paragraph [0045], Veal teaches write buffer 109 may have byte granularity for write access. In other words, cache buffer maybe smaller addressable unit. The cited portion from Veal clearly teaches storage media is larger addressable unit and cache buffer maybe smaller addressable unit. Thus, the rejection of claims 1, 13 and 17 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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