Prosecution Insights
Last updated: July 17, 2026
Application No. 18/427,959

ENHANCED CURRENT LIMITING TECHNIQUES

Non-Final OA §103
Filed
Jan 31, 2024
Examiner
PATEL, NIMESH G
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Qualcomm Incorporated
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
560 granted / 726 resolved
+22.1% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
15 currently pending
Career history
746
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
66.1%
+26.1% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 726 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5-10, 12-14 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han(US 2020/0159306) and Meunier(US 2022/0253358). Regarding claim 1, Han discloses an apparatus for power control, comprising: a system on chip (SoC) having a plurality of processing units(Figure 8, AP 840, CP 860), wherein the plurality of processing units are coupled to respective voltage supply paths, the voltage supply paths including a plurality of power supply circuits(Figure 8, Voltage paths including power supply circuits 830, 850 supplying power to processors 840, 860); voltage detection circuits coupled to the voltage supply paths and configured to detect voltages at the voltage supply paths(Paragraph 161, each of the one or more power sensors 811 to 818 may sense the voltage value input into each of the sub PMICs 830, 850, 870, and 890); and a controller configured to control a power consumption of one or more of the plurality of processing units based on at least one of the detected voltages and an output current or voltage of a regulator(Paragraphs 161, 164, Each of the one or more power sensors 811 to 818 may calculate the sensed current value or voltage value and determine a power value input into each of the sub PMICs 830, 850, 870, and 890. The control circuit 821 may generate the first signal according to a result of the comparison. For example, when the sum of the power values input into the sub PMICs 830, 850, 870, and 890 is greater than the threshold power value, the control circuit 821 may generate the first signal for limiting at least some functions of the hardware 840, 860, 880, and 895). Han does not specifically disclose a regulator configured to generate a regulated voltage provided to inputs of the power supply circuits. However, Meunier disclose a regulator(Figure 1, Primary PMIC 105) configured to generate a regulated voltage(Figure1, Vpre) provided to inputs of the power supply circuits(Figure 1, Secondary PMIC 110, 112). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the to combine the teachings of Han and Meunier to have a regulator configured to generate a regulated voltage provided to inputs of the power supply circuits. The motivation to do so would be to provide a more stable voltage. Regarding claim 2, Han discloses apparatus of claim 1, wherein the voltage detection circuits are configured to detect the voltages at inputs of the plurality of power supply circuits(Paragraph 161, Each of the one or more power sensors 811 to 818 may calculate the sensed current value or voltage value and determine a power value input into each of the sub PMICs 830, 850, 870, and 890). Regarding claim 3, Han discloses apparatus of claim 2, wherein the plurality of power supply circuits are parts of power management integrated circuits (PMICs) (Paragraph 161, Each of the one or more power sensors 811 to 818 may calculate the sensed current value or voltage value and determine a power value input into each of the sub PMICs 830, 850, 870, and 890). Regarding claim 5, Han discloses apparatus of claim 1, wherein the controller is configured to control the power consumption of one or more of the plurality of processing units based on the detected voltages(Paragraphs 161, 164, Each of the one or more power sensors 811 to 818 may calculate the sensed current value or voltage value and determine a power value input into each of the sub PMICs 830, 850, 870, and 890. The control circuit 821 may generate the first signal according to a result of the comparison. For example, when the sum of the power values input into the sub PMICs 830, 850, 870, and 890 is greater than the threshold power value, the control circuit 821 may generate the first signal for limiting at least some functions of the hardware 840, 860, 880, and 895). Regarding claim 6, Han discloses apparatus of claim 1, wherein, to control the power consumption, the controller is configured to reduce the power consumption of a specific processing unit of the plurality of processing units based on the detected voltage at the voltage supply path coupled to the specific processing unit being equal to or less than a voltage threshold(Paragraph 149, the power value input into the AP PMIC 620 may be greater than the threshold power value allowed for the AP 630. The calculation module may output a result of the comparison that the power value input into the AP PMIC 620 is greater than the threshold power value allowed for the AP 630 to the control circuit 613. The control circuit 613 may generate a first signal for controlling at least one of the hardware and the application based on the result of the comparison or controlling the power value output into the AP 630 from the AP PMIC 620. The control circuit 613 may output the generated first signal to the AP PMIC 620. The AP PMIC 620 may receive the power value output into the AP 630 from the AP PMIC 620 in response to the received first signal. For example, the AP PMIC 620 may reduce the output power value by controlling operations of the one or more regulators 622, 624, and 626). Regarding claim 7, Han discloses apparatus of claim 1, wherein, to control the power consumption, the controller is configured to compare the detected voltages to respective voltage thresholds, wherein the voltage thresholds are different(Paragraph 148, The calculation module 611 may compare at least one of the current value and the power value received from the one or more sensors 621, 623, and 625 with a threshold stored in the memory 612, for example, at least one of a threshold current value and a threshold power value. The threshold power value may be set according to each piece of hardware or each application). Claims 8-10, 12-14, and 16-20 recite similar limitations as claims 1-3 and 5-7 and thus are taught by Han and Meunier, as explained above. Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han(US 2020/0159306) and Meunier(US 2022/0253358) and Nam(US 2024/0036626). Regarding claim 21, Han discloses apparatus of claim 1, but does not specifically another detector configured to detect the output current or voltage of the regulator, wherein the other detector is different than the voltage detection circuits. However, Nam discloses multiple detectors detecting output voltages of the regulators(Paragraph 46). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the to combine the teachings of Han, Meunier and Nam to have specifically another detector configured to detect the output current or voltage of the regulator, wherein the other detector is different than the voltage detection circuits. The motivation to do so would be to detect output voltage for analysis of the regulators. Response to Arguments Applicant's arguments are not persuasive. Applicant argues that Meunier is completely silent with respect to a controller configured to control power consumption of one or more of the plurality of processing units based on at least one of the detected voltages and an output current or voltage of the regulator. However, Meunier is not relied on to teach these features. Han discloses a controller configured to control a power consumption of one or more of the plurality of processing units based on at least one of the detected voltages and an output current or voltage of a regulator (Paragraphs 161, 164, Each of the one or more power sensors 811 to 818 may calculate the sensed current value or voltage value and determine a power value input into each of the sub PMICs 830, 850, 870, and 890. The control circuit 821 may generate the first signal according to a result of the comparison. For example, when the sum of the power values input into the sub PMICs 830, 850, 870, and 890 is greater than the threshold power value, the control circuit 821 may generate the first signal for limiting at least some functions of the hardware 840, 860, 880, and 895). Meunier discloses a distributive power system that is commonly used(Paragraph 2) and the advantages of a two-stage distributed power system(Paragraph 47). The combination of Han and Meunier teaches Power being supplied to a regulator(Meunier's primary PMIC) and the regulator supplying the power to plurality of power controllers(PMICs) and a controller configured to control a power consumption of one or more of the plurality of processing units based on at least one of the detected voltages and an output current or voltage of a regulator. Thus, Applicant's arguments are not persuasive. Applicants arguments regarding new claim 21 is moot due to new grounds of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMESH G PATEL/Primary Examiner, Art Unit 2187
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Prosecution Timeline

Jan 31, 2024
Application Filed
Jun 04, 2025
Non-Final Rejection mailed — §103
Aug 28, 2025
Response Filed
Dec 03, 2025
Final Rejection mailed — §103
Feb 03, 2026
Response after Non-Final Action
Mar 03, 2026
Request for Continued Examination
Mar 12, 2026
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
84%
With Interview (+7.4%)
2y 10m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 726 resolved cases by this examiner. Grant probability derived from career allowance rate.

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