DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/18/2026, in which claims 1, 9, 15 were amended, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign applications KR10-2023-0057775 filed on 05/03/2023 and KR10-2023-0039242 filed on 03/24/2023. The foreign applications are not in English. The certified copy of the foreign priority applications KR10-2023-0057775 and KR10-2023-0039242 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application KR10-2023-0057775 that is not in English, an English translation of the non-English language foreign application KR10-2023-0057775 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d).
To be entitled to the filing date of the foreign priority application KR10-2023-0039242 that is not in English, an English translation of the non-English language foreign application KR10-2023-0039242 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d).
The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, claim 16 recites “a bottom surface of the bonding insulating layer has a flat shape” while claim 15 on which claim 16 depends recites “a bottom surface of the bonding insulating layer has a flat shape.” It is unclear “a bottom surface” recited in claim 16 is the same or different from “a bottom surface” recited in claim 15.
For the purpose of this Action, the above limitation of claim 16 will be interpreted and examined as duplicate limitation and should be omitted.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Lee et al. (US Pub. 20140061890).
Regarding claim 1, Barth discloses in Fig. 6, Fig. 7, Fig. 8 a semiconductor package comprising:
a semiconductor chip [106][paragraph [0029]-[0030]];
a dummy semiconductor chip [120] on the semiconductor chip [106][paragraph [0029], [0031]-[0032]]; and
a bonding insulating layer [124] between the semiconductor chip [106] and the dummy semiconductor chip [120], the bonding insulating layer [124] attaching the semiconductor chip [106] to the dummy semiconductor chip [120][paragraph [0042]], wherein
the dummy semiconductor chip [120] includes a cooling channel [104] extending from an inlet [one of 134] to an outlet [another one of 134], the inlet [one of 134] is in fluid communication with the outlet [another one of 134] through the cooling channel [104], the inlet [one of 134] is configured to allow a cooling fluid to flow in, the outlet [another one of 134] is configured to allow the cooling fluid to flow out [paragraph [0032], [0038]-[0039], [0044]-[0045]];
a bottom surface of the bonding insulating layer [124] has a flat shape, and the bonding insulating layer [124] defines a bottom boundary of the cooling channel [104][paragraph [0035]].
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Notes, the limitation “the inlet is in fluid communication with the outlet through the cooling channel, the inlet is configured to allow a cooling fluid to flow in, the outlet is configured to allow the cooling fluid to flow out” direct to manner of operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).”
Barth fails to disclose
a top surface of the bonding insulating layer has a concave-convex shape.
Lee et al. discloses in Fig. 1A, paragraph [0037], [0050]
a top surface of the bonding insulating layer [150] has a concave-convex shape.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Barth to include a top surface of the bonding insulating layer has a concave-convex shape. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of improving an adhesive strength between the bonding insulating layer and the dummy semiconductor chip and thus improving an adhesive strength between the semiconductor chip and the dummy semiconductor chip; [paragraph [0050], [0066] of Lee et al.]
Regarding claim 2, Barth discloses in Fig. 6
wherein at least a portion of the top surface of the bonding insulating layer [124] is in contact with the cooling channel [104].
Regarding claim 4, Barth discloses in Fig. 6, paragraph [0041]
a barrier layer [118] on at least one of an inner sidewall of the inlet [one of 134], an inner sidewall of the outlet [another one of 134], or an inner sidewall of the cooling channel [104].
Regarding claim 7, Barth discloses in Fig. 8, Fig. 12
wherein, in a plan view, the outlet is closer to a center of a top surface of the semiconductor chip than the inlet.
Regarding claim 8, Barth discloses in Fig. 2, paragraph [0033]
wherein the bonding insulating layer [108] includes at least one of silicon oxide, SiN, SiCN, benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, or epoxy [silicon oxide].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Lee et al. (US Pub. 20140061890) as applied to claim 1 above and further in view of Dogiamis et al. (US Pub. 20220399249)
Regarding claim 3, Barth fails to disclose
wherein a thickness of a part of the bonding insulating layer overlapping the cooling channel in a vertical direction is less than a thickness of a portion the bonding insulating layer separated from the cooling channel in a horizontal direction.
Dogiamis et al. discloses in Fig. 3, Fig. 19-23
wherein a thickness of a part of the bonding layer [33 or 402] overlapping the cooling channel [35 or 405b] in a vertical direction is less than a thickness of a portion the bonding layer [33 or 402] separated from the cooling channel [35 or 405b] in a horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Dogiamis et al. into the method of Barth to include wherein a thickness of a part of the bonding insulating layer overlapping the cooling channel in a vertical direction is less than a thickness of a portion the bonding insulating layer separated from the cooling channel in a horizontal direction. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of enabling microfluidic channels to be deeper and be configured to meet particular cooling needs of the stacked ICs [paragraph [0041] of Dogiamis et al.].
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Lee et al. (US Pub. 20140061890) as applied to claim 1 above and further in view of Ching et al. (US Pub. 20100117201)
Regarding claims 5-6, Barth fails to disclose
a plurality of dummy through electrodes penetrating the dummy semiconductor chip in a vertical direction;
wherein at least one of the plurality of dummy through electrodes overlaps the cooling channel in the vertical direction.
Ching et al. discloses in Fig. 15, Fig. 18, Fig. 26, paragraph [0026]
a plurality of dummy through electrodes [20-1] penetrating the dummy semiconductor chip [10 and 12] in a vertical direction;
wherein at least one of the plurality of dummy through electrodes overlaps the cooling channel in the vertical direction.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ching et al. into the method of Barth to include a plurality of dummy through electrodes penetrating the dummy semiconductor chip in a vertical direction; wherein at least one of the plurality of dummy through electrodes overlaps the cooling channel in the vertical direction. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of enabling both dies on both side of the dummy semiconductor chip to be cooled thus significant increasing in the heat dissipating ability of the package [paragraph [0034], [0035] of Ching et al.].
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Shao et al. (US Pub. 20260076196).
Regarding claim 9, Barth discloses in Fig. 6, Fig. 7, Fig. 8 a semiconductor package comprising:
a first semiconductor chip [106][paragraph [0029]-[0030]];
a dummy semiconductor chip [120] on the first semiconductor chip [106][paragraph [0029], [0031]-[0032]]; and
a bonding insulating layer [124] between the first semiconductor chip [106] and the dummy semiconductor chip [120], the bonding insulating layer [124] attaching the first semiconductor chip [106] to the dummy semiconductor chip [120][paragraph [0042]], wherein
the dummy semiconductor chip [120] includes a cooling channel [104] extending from an inlet [one of 134] to an outlet [another one of 134],
the inlet [one of 134] is in fluid communication with the outlet [another one of 134] through the cooling channel [104],
the inlet [one of 134] is configured to allow a cooling fluid to flow in,
the outlet [another one of 134] is configured to allow the cooling fluid to flow out [paragraph [0032], [0038]-[0039], [0044]-[0045]], and
a bottom surface of the cooling channel [104] is in contact with at least a portion of a top surface of the bonding insulating layer [124];
a bottom surface of the bonding insulating layer [124] has a flat shape, and the bonding insulating layer [124] defines a bottom boundary of the cooling channel [104][paragraph [0035]].
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Notes, the limitation “the inlet is in fluid communication with the outlet through the cooling channel, the inlet is configured to allow a cooling fluid to flow in, the outlet is configured to allow the cooling fluid to flow out” direct to manner of operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).”
Barth fails to disclose
an interposer;
the first semiconductor chip on the interposer;
at least one second semiconductor chip on the interposer and separated from the first semiconductor chip in a horizontal direction.
Shao et al. discloses in Fig. 20A, paragraph [0013], [0027], [0031], [0037], [0053]
an interposer [70];
the first semiconductor chip [52] on the interposer [70];
at least one second semiconductor chip [80] on the interposer [70] and separated from the first semiconductor chip [52] in a horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shao et al. into the method of Barth to include an interposer; the first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer and separated from the first semiconductor chip in a horizontal direction. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of improving the integration density by providing a package including multiple integrated circuit devices [paragraph [0002], [0031] of Shao et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 12, Barth discloses in Fig. 6
wherein a side surface of the first semiconductor chip [106], a side surface of the dummy semiconductor chip [120], and a side surface of the bonding insulating layer [124] are aligned with one another in a vertical direction.
Shao et al. also discloses in Fig. 20A
wherein a side surface of the first semiconductor chip [50], a side surface of the dummy semiconductor chip [60], and a side surface of the bonding insulating layer [66] are aligned with one another in a vertical direction.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Shao et al. (US Pub. 20260076196) as applied to claim 9 above and further in view of Ching et al. (US Pub. 20100117201)
Regarding claims 10-11, Barth discloses in Fig. 6, paragraph [0029], [0033], [0041]
a barrier layer [118] on an inner sidewall of at least one of the inlet [one of 134], the outlet [another one of 134], or the cooling channel [104].
wherein the barrier layer [118] includes at least one of metal or silicon [silicon oxide].
Barth fails to disclose
a plurality of dummy through electrodes penetrating the dummy semiconductor chip in a vertical direction, and the plurality of dummy through electrodes include metal.
wherein, in a plan view, each of the plurality of dummy through electrodes is separated from the inlet and the outlet in the horizontal direction and overlaps the cooling channel in the vertical direction.
Ching et al. discloses in Fig. 15, Fig. 18, Fig. 26, paragraph [0025], [0026]
a plurality of dummy through electrodes penetrating the dummy semiconductor chip [10 and 12] in a vertical direction, and the plurality of dummy through electrodes include metal [paragraph [0025] “a diffusion barrier layer and a copper layer (not shown) may be formed on the sidewalls of channels 18”];
wherein at least one of the plurality of dummy through electrodes overlaps the cooling channel in the vertical direction.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ching et al. into the method of Barth to include a plurality of dummy through electrodes penetrating the dummy semiconductor chip in a vertical direction, and the plurality of dummy through electrodes include metal; wherein, in a plan view, each of the plurality of dummy through electrodes is separated from the inlet and the outlet in the horizontal direction and overlaps the cooling channel in the vertical direction. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of enabling both dies on both side of the dummy semiconductor chip to be cooled thus significant increasing in the heat dissipating ability of the package [paragraph [0034], [0035] of Ching et al.].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Shao et al. (US Pub. 20260076196) as applied to claim 9 above and further in view of Lee et al. (US Pub. 20140061890)
Regarding claim 13, Barth discloses in Fig. 2, paragraph [0029]
a topmost surface of the bonding insulating layer [108] and a bottom surface of the bonding insulating layer [108] each are in contact with only a semiconductor material.
Shao et al. also discloses in Fig. 20A, paragraph [0014], [0018]
a topmost surface of the bonding insulating layer [66] and a bottom surface of the bonding insulating layer [66] each are in contact with only a semiconductor material.
Barth fails to disclose
wherein the top surface of the bonding insulating layer has a concave-convex shape.
Lee et al. discloses in Fig. 1A, paragraph [0037], [0050]
the top surface of the bonding insulating layer [150] has a concave-convex shape.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Barth to include the top surface of the bonding insulating layer has a concave-convex shape. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of improving an adhesive strength between the bonding insulating layer and the dummy semiconductor chip and thus improving an adhesive strength between the semiconductor chip and the dummy semiconductor chip; [paragraph [0050], [0066] of Lee et al.]
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Shao et al. (US Pub. 20260076196) as applied to claim 9 above and further in view of Dogiamis et al. (US Pub. 20220399249)
Regarding claim 14, Barth fails to disclose
wherein a horizontal area of the bonding insulating layer in contact with a top surface of the first semiconductor chip is larger than a horizontal area of the bonding insulating layer in contact with a bottom surface of the dummy semiconductor chip.
Dogiamis et al. discloses in Fig. 3, Fig. 23
wherein a horizontal area of the bonding layer [33 or 412] in contact with a top surface of the first semiconductor chip [14 or 414] is larger than a horizontal area of the bonding layer [33 or 412] in contact with a bottom surface of the dummy semiconductor chip [406].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Dogiamis et al. into the method of Barth to include wherein a horizontal area of the bonding insulating layer in contact with a top surface of the first semiconductor chip is larger than a horizontal area of the bonding insulating layer in contact with a bottom surface of the dummy semiconductor chip. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of enabling microfluidic channels to be deeper and be configured to meet particular cooling needs of the stacked ICs [paragraph [0041] of Dogiamis et al.].
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US Pub. 20100127390) in view of Shao et al. (US Pub. 20260076196) and Lee et al. (US Pub. 20140061890).
Regarding claims 15-16, Barth discloses in Fig. 6, Fig. 7, Fig. 8 a semiconductor package comprising:
a first semiconductor chip [106][paragraph [0029]-[0030]];
a dummy semiconductor chip [120] on the first semiconductor chip [106][paragraph [0029], [0031]-[0032]]; and
a bonding insulating layer [124] between the first semiconductor chip [106] and the dummy semiconductor chip [120], the bonding insulating layer [124] attaching the first semiconductor chip [106] to the dummy semiconductor chip [120][paragraph [0042]], wherein
the dummy semiconductor chip [120] includes a cooling channel [104] extending from an inlet [one of 134] to an outlet [another one of 134],
the inlet [one of 134] is in fluid communication with the outlet [another one of 134] through the cooling channel [104],
the inlet [one of 134] is configured to allow a cooling fluid to flow in,
the outlet [another one of 134] is configured to allow the cooling fluid to flow out [paragraph [0032], [0038]-[0039], [0044]-[0045]];
a bottom surface of the bonding insulating layer [124] has a flat shape, and the bonding insulating layer [124] defines a bottom boundary of the cooling channel [104][paragraph [0035]].
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Notes, the limitation “the inlet is in fluid communication with the outlet through the cooling channel, the inlet is configured to allow a cooling fluid to flow in, the outlet is configured to allow the cooling fluid to flow out” direct to manner of operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).”
Barth fails to disclose
a package substrate;
an interposer on the package substrate;
the first semiconductor chip on the interposer;
at least one second semiconductor chip on the interposer and separated from the first semiconductor chip in a horizontal direction;
a molding layer on the interposer, the molding layer surrounding the first semiconductor chip, the at least one second semiconductor chip, the dummy semiconductor chip, and the bonding insulating layer.
Shao et al. discloses in Fig. 20A, paragraph [0013], [0027], [0031], [0033]-[0035], [0037], [0045], [0053]
a package substrate [150];
an interposer [70] on the package substrate [150];
the first semiconductor chip [52] on the interposer [70];
at least one second semiconductor chip [80] on the interposer [70] and separated from the first semiconductor chip [52] in a horizontal direction;
a molding layer [84 and/or 90] on the interposer [70], the molding layer [84 and/or 90] surrounding the first semiconductor chip [50], the at least one second semiconductor chip [80], the dummy semiconductor chip [60], and the bonding insulating layer [66].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shao et al. into the method of Barth to include a package substrate; an interposer on the package substrate; the first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer and separated from the first semiconductor chip in a horizontal direction; a molding layer on the interposer, the molding layer surrounding the first semiconductor chip, the at least one second semiconductor chip, the dummy semiconductor chip, and the bonding insulating layer. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of improving the integration density by providing a package including multiple integrated circuit devices [paragraph [0002], [0031] of Shao et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Barth fails to disclose
wherein a top surface of the bonding insulating layer has a concave-convex shape;
a topmost surface of the bonding insulating layer is at a higher vertical level than a bottommost surface of the dummy semiconductor chip.
Lee et al. discloses in Fig. 1A, paragraph [0037], [0050]
a top surface of the bonding insulating layer [150] has a concave-convex shape;
a topmost surface of the bonding insulating layer [150] is at a higher vertical level than a bottommost surface of the dummy semiconductor chip [160].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Barth to include a top surface of the bonding insulating layer has a concave-convex shape; a topmost surface of the bonding insulating layer is at a higher vertical level than a bottommost surface of the dummy semiconductor chip. The ordinary artisan would have been motivated to modify Barth in the above manner for the purpose of improving an adhesive strength between the bonding insulating layer and the dummy semiconductor chip and thus improving an adhesive strength between the semiconductor chip and the dummy semiconductor chip [paragraph [0050], [0066] of Lee et al.]
Regarding claim 17, Barth discloses in Fig. 2, Fig. 6
wherein the bonding insulating layer [108 or 124] entirely covers a top surface of the first semiconductor chip [106] and a bottommost surface of the dummy semiconductor chip [120].
Regarding claim 18, Barth discloses in Fig. 2, paragraph [0029], [0031]
wherein the dummy semiconductor chip [102] is a part of a bare wafer [102] including a semiconductor material, and a topmost surface of the bonding insulating layer [108] is in contact with only the semiconductor material.
Shao et al. also discloses in Fig. 20A, paragraph [0018]
wherein the dummy semiconductor chip [60] is a part of a bare wafer [62] including a semiconductor material, and a topmost surface of the bonding insulating layer [66] is in contact with only the semiconductor material.
Regarding claim 19, Shao et al. discloses in Fig. 18, Fig. 20A
wherein a top surface of the at least one second semiconductor chip [80], a top surface of the dummy semiconductor chip [60], and a top surface of the molding layer [90] are coplanar with one another, and a top surface of the first semiconductor chip [50] is at a lower vertical level than the top surface of the molding layer [90].
Regarding claim 20, claim 20 directs to product-by-process claim. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Furthermore, "[b]ecause validity is determined based on the requirements of patentability, a patent is invalid if a product made by the process recited in a product-by-process claim is anticipated by or obvious from prior art products, even if those prior art products are made by different processes." Amgen Inc. v. F. Hoffman-La Roche Ltd., 580 F.3d 1340, 1370 n 14, 92 USPQ2d 1289, 1312, n 14 (Fed. Cir. 2009). (MPEP 2113).
In this case, Barth, Shao et al. and Lee et al. discloses the bonding insulating layer thus it meets the claim.
Response to Arguments
Applicant's arguments filed 06/18/2026 have been fully considered but they are not persuasive.
As stated above, Barth discloses in Fig. 6 and paragraph [0035]
a bottom surface of the bonding insulating layer [124] has a flat shape, and the bonding insulating layer [124] defines a bottom boundary of the cooling channel [104].
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Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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