CTNF 18/428,207 CTNF 84142 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING DIPOLE FORMATION STRUCTURE COVERING BIT LINE CONTACT . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 3-5 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (US 2022/0415793 A1; hereinafter “Kim”) . Regarding claim 1, Kim teaches a semiconductor device, comprising: a substrate (100) including a recess region (t1) (Figs. 3A and 10A and paragraphs 33-34 and 102); a bit line contact (DC) in the recess region (Fig. 3A and paragraphs 30-32); a bit line (BL) on the bit line contact, the bit line extending in a first direction (D2) (Figs. 2-3A and paragraphs 24-26 and 32); a first insulating pattern (151) covering side surfaces of the bit line contact and an inner surface of the recess region (Fig. 3A and paragraphs 54-59); and a second insulating pattern (152 and/or a combination of 152 and 153) on the first insulating pattern (Fig. 3A and paragraphs 54-59), wherein an oxygen density of the first insulating pattern is higher than an oxygen density of the second insulating pattern (paragraph 59. For example, 151 formed of silicon oxide has higher oxygen density than 152 formed of silicon nitride, which does not have oxygen atom). Regarding claim 3, Kim teaches further comprising an insulating gapfill pattern on the second insulating pattern, wherein the insulating gapfill pattern fills the recess region, in which the first and second insulating patterns are formed (Fig. 3A, for claim 3, considering “a second insulating pattern” to be an outer portion of 152, an inner portion of 152 embedded within the outer portion of 152 is considered as “an insulating gapfill pattern” filling t1). Regarding claim 4, Kim teaches wherein the first and second insulating patterns extend on a side surface of the bit line (a side surface of BL) (Fig. 3A). Regarding claim 5, Kim teaches wherein: the first and second insulating patterns are in contact with each other with an interface therebetween (151 and 152 are in direct contact), and an electric dipole is at the interface (an electric dipole between silicon oxide of 151 and silicon nitride of 152) (Fig. 3A) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim . Regarding claim 2, Kim teaches that the bit line contact includes doped semiconductor material (paragraph 48). While Kim does not explicitly teach the semiconductor material such as polysilicon, it would have been obvious to one of ordinary skill in the art to utilize polysilicon as the readily available semiconductor material choice known in the art in order to provide the predictable semiconductive material characteristics for the bit line contact. Regarding claim 6, Kim teaches wherein: the first insulating pattern includes silicon oxide (paragraph 59, 151 formed of silicon oxide). While Kim does not explicitly teach that the second insulating pattern includes a metal oxide, Kim teaches that the material choice for the second insulating pattern (152) is not limited to only silicon oxide, silicon oxynitride, and silicon nitride (paragraph 59). Then, it would have been obvious to one of ordinary skill in the art to utilize metal oxide as the readily available metal oxide insulating material choice known in the art in order to provide the predictable insulating material characteristics . 07-21-aia AIA Claim s 7-8, 10-11, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0413525 A1; hereinafter “Lee”) . Regarding claim 7, Lee teaches a semiconductor device, comprising: a substrate (110) including an active pattern (ACT/118) (Figs. 2-3A and paragraphs 25-26 and 30-32); a bit line (BL/147) on the active pattern, the bit line extending in a first direction (a y-direction) (Figs. 2-3A and paragraphs 27 and 52); a bit line contact (134) between the bit line and the active pattern (Fig. 3A and paragraphs 48 and 51); a storage node contact (XL) on the active pattern and spaced apart from the bit line and the bit line contact (Fig. 3A and paragraph 35); and an insulating formation structure (150 and DSS) between a side surface of the bit line contact (a side surface of 134) and the storage node contact (Fig. 3A and paragraphs 47 and 56), the dipole formation structure including a first insulating pattern (152 of 150 formed of nitride) and a second insulating pattern (DSS, which is DS shown in Fig. 9A) (Figs. 3A and 9A and paragraphs 56 and 92-93), wherein the second insulating pattern includes a metal-based dielectric material (paragraph 93). Lee does not explicitly teach that the metal-based dielectric material for the second insulating pattern (DS/DSS) (paragraph 93) includes a metal oxide and thereby forms a dipole interface between the second insulating pattern (DS/DSS) and the first insulating pattern (150). Nevertheless, the metal oxide is readily available insulating material known in the art and it would have been obvious to one of ordinary skill in the art to utilize the metal oxide as the metal-based dielectric material choice from Lee for the second insulating pattern (DS/DSS) in order to provide the predictable metal-based insulating material characteristics. Furthermore, the first insulating pattern (150 formed of nitride such as silicon nitride) and the second insulating pattern (DS/DSS formed of metal oxide) then would form an oxide-nitride based dipole interface therebetween. Regarding claim 8, Lee teaches wherein the first insulating pattern is between the side surface of the bit line contact and the second insulating pattern (Fig. 3A). Regarding claim 10, Lee teaches wherein the dipole formation structure extends on the side surface of the bit line (Fig. 3A). Regarding claim 11, Lee teaches further comprising an insulating gapfill pattern (154 within OPH) between the dipole formation structure and the storage node contact (Figs. 3A and 7A and paragraphs 56 and 84), wherein: the first insulating pattern is in contact with the bit line contact (Fig. 3A, 152 is in direct contact with 134), and the second insulating pattern is in contact with the insulating gapfill pattern (Fig. 3A, DSS is in indirect contact with 154). Regarding claim 14, Lee teaches wherein: the active pattern includes a center portion (a portion of 118 directly under 134) and edge portions (portions of 118 directly under XL), the edge portions being spaced apart from each other with the center portion therebetween (Fig. 3A), the bit line contact is connected to the center portion (Fig. 3A), and the storage node contact is connected to one of the edge portions (Fig. 3A). Regarding claim 15, with the similar reason for rejecting claim 7 as discussed above, it would have been obvious to one of ordinary skill in the art to utilize the metal oxide, including the claimed lanthanum oxide or scandium oxide, as the metal-based dielectric material choice from Lee for the second insulating pattern (DS/DSS) in order to provide the predictable metal-based insulating material characteristics. Regarding claim 16, Lee teaches further comprising: a word line (WL/120) extending in a second direction (a x-direction) and crossing the active pattern (ACT), the second direction intersecting the first direction (the x-direction intersecting the y-direction) (Fig. 2 and paragraphs 26-27 and 37); and a data storage pattern (200) connected to the storage node contact (Fig. 3A and paragraph 63). Regarding claim 17, Lee teaches a semiconductor device, comprising: active patterns (ACT/118), each active pattern including edge portions (portions of 118 directly under XL) and a center portion (a portion of 118 directly under 134) between the edge portions (Figs. 2-3A and paragraphs 25-26 and 30-32); bit lines (BL/147) on the center portions, the bit lines extending in a first direction (a y-direction) (Figs. 2-3A and paragraphs 27 and 52); bit line contacts (134) between the center portions and the bit lines (Fig. 3A and paragraphs 48 and 51); word lines (WL/120) extending in a second direction (a x-direction) and crossing the active patterns, the second direction intersecting the first direction (Fig. 2 and paragraphs 26-27 and 37); data storage patterns (200) on the edge portions, respectively (Fig. 3A and paragraph 63); storage node contacts (XL) between the edge portions and the data storage patterns (Fig. 3A and paragraph 35); and insulating formation structures (150 and DSS) between side surfaces of the bit line contacts and the storage node contacts (side surfaces of 134 and XL), wherein: each of the insulating formation structures includes a first insulating pattern (152 of 150 formed of nitride) and a second insulating pattern (DSS, which is DS shown in Fig. 9A), which are in contact with each other (Figs. 3A and 9A and paragraphs 56 and 92-93), the bit line contact includes doped poly silicon (paragraph 51), and the second insulating pattern includes a metal-based dielectric material (paragraph 93). Lee does not explicitly teach that the metal-based dielectric material for the second insulating pattern (DS/DSS) (paragraph 93) includes a metal oxide and thereby forms a dipole interface between the second insulating pattern (DS/DSS) and the first insulating pattern (150). Nevertheless, the metal oxide is readily available insulating material known in the art and it would have been obvious to one of ordinary skill in the art to utilize the metal oxide as the metal-based dielectric material choice from Lee for the second insulating pattern (DS/DSS) in order to provide the predictable metal-based insulating material characteristics. Furthermore, the first insulating pattern (150 formed of nitride such as silicon nitride) and the second insulating pattern (DS/DSS formed of metal oxide) then would form an oxide-nitride based dipole interface therebetween. Regarding claim 19, Lee teaches wherein an electric dipole is at an interface between the first and second insulating patterns (with the similar reasoning for metal oxide of the second insulating pattern, 150 formed of nitride such as silicon nitride and DS/DSS formed of metal oxide would form an oxide-nitride based dipole interface therebetween). Regarding claim 20, Lee teaches wherein the dipole formation structure extends on a side surface of the bit line (Fig. 3A) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 9, 12-13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL WHALEN/Primary Examiner, Art Unit 2893 Application/Control Number: 18/428,207 Page 2 Art Unit: 2893 Application/Control Number: 18/428,207 Page 3 Art Unit: 2893 Application/Control Number: 18/428,207 Page 4 Art Unit: 2893 Application/Control Number: 18/428,207 Page 6 Art Unit: 2893 Application/Control Number: 18/428,207 Page 7 Art Unit: 2893 Application/Control Number: 18/428,207 Page 8 Art Unit: 2893 Application/Control Number: 18/428,207 Page 9 Art Unit: 2893
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