Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1.A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/3/2025 has been entered.
2. Claims 1-20 are presented for examination.
Objection
3. Regarding Claim 1, Claim recites “an amplifier having an input … to the output of the error amplifier …” referring to the amplifier with a term “error amplifier”. Terminology should be consistent throughout all claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1, 8-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Priego et al. (“Priego”), U.S. Patent Publication No. 2020/0106360.
Regarding Clam 1, Priego teaches an apparatus comprising:
switching converter circuitry (switching converter 500) having a control input (at switch node 522), a power input (Vin at 501) , and a power output (Vout at output node 524) [Para: 0025 and Fig-5]; and
control circuitry (circuit between Vin 501 – Vout at node 524) having a control output coupled to the control input of the switching converter circuitry [Fig-5], the control circuitry including:
an amplifier (amplifier 510) having an input (at FB node) coupled to the power output [Para: 0028(“converter circuit 500 is a feedback loop 532 between the output node 524 and the FB node …”) and Fig-5(via FB 532);
power saving mode (PSM) circuitry (gate driver 518) having inputs (see inputs to 518) and an output (one output from S1 or S2 when FB_COMP is asserted or not), the inputs coupled to at least one of the power input (via 514) or the power output (via S1 or S2) [Para: 0026(“When FB_COMP is asserted or “high”, S1 is on and S2 is off. When FB_COMP is not asserted or “low”, S1 is off and S2 is on. During operations of the nano-Iq buck converter circuit 500, a switch node (SW) 522 between S1 and S2 transitions between VIN (S1 on, S2 off) and ground (S1 off, S2 on) to regulate VOUT at the output node 524”) and Fig-5]; and
comparison circuitry (S1 and S2) having inputs and an output, the inputs coupled to the output of the error amplifier (see the connection between amplifier 510 through S1, S2) and to the output of the PSM circuitry, and the output of the comparison circuitry coupled to the control output [0026(as s1 and s2 on or off “to regulate VOUT at the output node 524”)].
Regarding Claims 8-14, Since they are directly related to Claims 1, 16, 17 and 19-20 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claims 1,16, 17 and 19-20 applies equally as well to Claims 8-14 and Priego furthermore teaches switching converter circuitry operable in a first mode or in a second mode, in which the switching converter circuitry switches at a reduced frequency in the second mode compared with the first mode, or skips one or more switching cycle in the second mode [Para: 0034 (frequency drops)].
Regarding Claim 15, Priego teaches an apparatus comprising:
switching converter circuitry configurable to generate an output voltage (Vout) responsive to an input voltage (Vin at 501) [Fig-5];
power saving mode (PSM) entry circuitry (518) coupled to the switching converter circuitry(S1 and S2), the PSM entry circuitry including:
comparison circuitry coupled to the switching converter circuitry, the comparison circuitry configurable to compare the input voltage and the output voltage to select one of the input voltage or the output voltage [Para: 0018(as comparator “when VIN approaches VOUT involves a VIN−VOUT voltage comparator (to identify when VIN−VOUT is greater than or less than a voltage threshold)”)];
scaling circuitry (offset circuit 503) coupled to the comparison circuitry, the scaling circuitry configurable to scale the one of the input voltage or the output voltage by a slope constant of the switching converter circuitry [Para: 0024(“the voltage at the FB node is adjusted using a 100% mode offset circuit 503 that includes an offset current (I.sub.OFFSET) source 506 coupled to the FB node” where the offset to the output voltage is by a slope, see para 0003-0006)]; and
offset circuitry coupled to the scaling circuitry, the offset circuitry configured configurable to offset a reference compensation voltage by the one of the input voltage or the output voltage to generate a PSM entry voltage [Para: 0024(“the voltage at the FB node is adjusted using a 100% mode offset circuit 503 that includes an offset current (I.sub.OFFSET) source 506 coupled to the FB node” where the FB node has an output FB_COMP and “ FB_COMP is asserted or “high” or “low” is an entry for PSM 518, see para 0026)]; and
comparison circuitry coupled to the offset circuitry, the comparison circuitry configurable to compare a compensation voltage to the PSM entry voltage [Para: 0018(“VIN approaches VOUT involves a VIN−VOUT voltage comparator (to identify when VIN−VOUT is greater than or less than a voltage threshold).”)], the compensation voltage represents an error between the output voltage of the switching converter circuitry and a reference voltage [Para: 0024-0026, voltage drop equal to V.sub.OFFSET at the FB node when there is a difference between Vin and Vout as “ When V.sub.OFFSET is applied, VOUT=VREF+V.sub.OFFSET. Otherwise, VOUT=VREF” see para 0026)].
Regarding Claim 16, Priego teaches an error amplifier (510) coupled to the switching converter circuitry (S1, S2), the PSM entry circuitry (518), and the comparison circuitry, the error amplifier configurable to generate the compensation voltage by determining a difference between the output voltage of the switching converter circuitry and the reference voltage, the reference voltage represents a target output voltage of the switching converter circuitry [Para: 0026(“a feedback comparison result (FB_COMP) based on the difference between VREF and the voltage at the FB node”) and 0033].
Regarding Claim 17, Priego teaches wherein the PSM entry circuitry includes:
first voltage-to-current (V-I) converter circuitry (517A) coupled to the switching converter circuitry and the comparison circuitry, the first V-I converter circuitry configurable to generate a first current that represents the input voltage of the switching converter circuitry (“When FB_COMP is asserted or “high”, S1 is on …”); and
second V-I converter circuitry coupled to the switching converter circuitry and the comparison circuitry, the second V-I converter circuitry configurable to generate a second current that represents the output voltage of the switching converter circuitry [Para: 0026(“When FB_COMP is not asserted or “low”, S1 is off and S2 is on”)].
Regarding Claim 19, Priego teaches wherein the scaling circuitry comprising:
a first transistor (M1) coupled to the comparison circuitry, the first transistor configurable to source a current proportional to the one of the input voltage or the output voltage of the switching converter circuitry [Fig-5];
a second transistor (M2) coupled to the first transistor (M1) and the offset circuitry (503), the second transistor configurable to source a scaled current (current Ioffset by 506) representing the current proportional to the one of the input voltage or the output voltage times the slope constant [Para: 0024(as “the voltage at the FB node is adjusted using a 100% mode offset circuit 503 that includes an offset current (I.sub.OFFSET) source 506 coupled to the FB node via a switch (M2)”); and
trim circuitry coupled to the second transistor, the trim circuitry configurable to set the slope constant of the second transistor responsive to at least one of the switching converter circuitry or a derating value of an inductor [Para: 0024(“the voltage at the FB node is adjusted using a 100% mode offset circuit 503 that includes an offset current (I.sub.OFFSET) source 506 coupled to the FB node” where the offset to the output voltage is by a slope, see para 0003-0006)].
Regarding Claim 20, Priego teaches wherein the offset circuitry (503) includes:
error amplifier coupled to the scaling circuitry, the error amplifier (by amplifier 510) configurable to determine an error between the one of the input voltage or the output voltage and the reference compensation voltage [Para: 0026” comparator 510 outputs a feedback comparison result (FB_COMP) based on the difference between VREF and the voltage at the FB node” where FB node receives Vout voltage)];
a resistor (Rbias) coupled to the scaling circuitry and the error amplifier, the resistor configurable to generate an offset voltage responsive to the one of the input voltage or the output voltage from the scaling circuitry [Para: 0028(“Rbias is leveraged to create V.sub.OFFSET at the FB node”)]; and
a transistor (M2) coupled to the error amplifier(510) and the resistor, the transistor configurable to supply an offset current to the resistor responsive to the error of the error amplifier {para: 0027(“M2, the offset current source 506, and the feedback loop 536 are active in the 100% mode of the nano-Iq buck converter circuit 500, where V.sub.OFFSET starts to be applied at the FB node of the hysteretic comparator 510”)].
Allowable Subject Matter
5. Claims 2, 3 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176