DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on November 10, 2025 is acknowledged. However, after further study of the invention, the examiner believes that Species II (claims 8-14) should be grouped together with Species I, which includes claims 1-7, but not species III (claims 15-20). The traversal is on the ground(s) that this approach is improper because a species can never be defined by claims and cited MPEP §806.04(e). This is not found persuasive because the restriction is based on the disclosed embodiments, not the claim language itself or the examiner’s statements in the restriction to include the groupings of the claims in the species. Further, the restriction is based on distinct embodiments (supported by MPEP § 806.04(f) and § 808.01(a)), and that the applicant's reliance on “claims are never species” misinterprets the purpose of a species restriction, which is to limit the search to a single embodiment among many.
The requirement is still deemed proper and is therefore made FINAL.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim (see the detail rejections under 35 U.S.C. §112(a) below). Applicant timely traversed the restriction (election) requirement in the reply filed on November 10, 2025.
Claim Objections
Claims 1-14 are objected to because of the following informalities:
1. (Proposed Amendment) A circuit comprising:
a partial sum circuit configured to generate partial sum values by summing decision feedback equalizer outputs;
a first decision feedback equalizer path coupled to the partial sum circuit, the first decision feedback equalizer path including;
a first adder circuit configured to generate a sum of a first subset of the partial sum values;
a first multiplexer having s coupled to an output of the first adder circuit, and an output;
a first two's complement circuit having an input coupled to the output of the first multiplexer, and an output;
a second multiplexer having a first input coupled to the output of the first multiplexer, and a second input coupled to the output of the first two's complement circuit; and
a first slicer having an input coupled to an output of the second multiplexer.
2. (Proposed Amendment) The circuit of claim 1, further comprising:
a second decision feedback equalizer path including;
a second adder circuit configured to generate a sum of a second subset of the partial sum values;
a third multiplexer having s coupled to an output of the second adder circuit, and an output;
a second two's complement circuit having an input coupled to the output of the third multiplexer, and an output;
a fourth multiplexer having a first input coupled to the output of the third multiplexer, and a second input coupled to the output of the second two's complement circuit; and
a second slicer having an input coupled to an output of the fourth multiplexer.
3. (Proposed Amendment) The circuit of claim [[2]] 1, wherein:
the output of the first adder circuit is a first output;
the first adder circuit has a second output; and
the circuit further comprises:
a second decision feedback equalizer path including:
a third multiplexer having s coupled to the second output of the first adder circuit, and an output;
a second two's complement circuit having an input coupled to the output of the third multiplexer, and an output;
a fourth multiplexer having s coupled to the output of the third multiplexer, and a second input coupled to the output of the second two's complement circuit; and
a second slicer having an input coupled to an output of the fourth multiplexer.
4. (Proposed Amendment) The circuit of claim 2, wherein the second adder circuit includes:
a first adder having a first inputs of the third multiplexer; and
a fifth multiplexer having an output coupled to the second input of the first adder, and the first and second inputs coupled to the partial sum circuit.
5. (Proposed Amendment) The circuit of claim 1, wherein first adder circuit includes:
a first adder having a first input, a second inputs of the first multiplexer; and
a third multiplexer having an output coupled to the first input of the first adder, and the first and second inputs coupled to the partial sum circuit.
8. (Proposed Amendment) A circuit comprising:
a partial sum circuit configured to generate partial sum values by summing decision feedback equalizer outputs;
a first decision feedback equalizer path coupled to the partial sum circuit, the first decision feedback equalizer path including:
a first adder circuit having a first output and a second output, the first adder circuit configured to generate a sum of a first subset of the partial sum values;
a first multiplexer having s coupled to [[a]] the first output of the first adder circuit, and an output; and
a first slicer having an input coupled to the output of the first multiplexer; and
a second decision feedback equalizer path including:
a second multiplexer having [[an]] inputs coupled to the second output of the first adder circuit, and an output; and
a second slicer having an input coupled to the output of the second multiplexer.
9. (Proposed Amendment) The circuit of claim 8, wherein the first decision feedback equalizer path further includes:
a two's complement circuit having an input coupled to the output of the first multiplexer, and an output; and
a third multiplexer having a first input coupled to the output of the first multiplexer, a second input coupled to the output of the two's complement circuit, and an output coupled to the input of the first slicer.
10. (Proposed Amendment) The circuit of claim 8, wherein the second decision feedback equalizer path further includes:
a two's complement circuit having an input coupled to the output of the second multiplexer, and an output; and
a third multiplexer having a first input coupled to the output of the second multiplexer, a second input coupled to the output of the two's complement circuit, and an output coupled to the input of the second slicer.
11. (Proposed Amendment) The circuit of claim 10, wherein the second decision feedback equalizer path further includes:
a second adder circuit including:
a first adder having a first inputs of the second multiplexer; and
a fifth multiplexer having an output coupled to the second the first and second inputs coupled to the partial sum circuit.
12. (Proposed Amendment) The circuit of claim 8, wherein first adder circuit includes:
a first adder having first and second inputs, and an output coupled to the s of the first multiplexer; and
a third multiplexer having an output coupled to the first input of the first adder, and the first and second inputs coupled to the partial sum circuit.
Claims 6 and 7 depend either directly or indirectly from claim 1, therefore they are also objected.
Claims 13 and 14 depend either directly or indirectly from claim 8, therefore they are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-7 and 11-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
According to the invention described in the specification and shown in the disclosure of the drawings, FIG. 2 is a block diagram of an example of 6 paths parallel decision feedback equalizer circuit suitable for use as the decision feedback equalizer of FIG. 1; FIG. 3 is a block diagram of example circuitry 300 of a first embodiment of a decision equalizer path 6 that takes advantage of symmetry of path output values to reduce path circuitry (par. [0027]); FIG. 4 is a block diagram of example circuitry 400 of a first embodiment of a decision equalizer path 5 that takes advantage of symmetry of path output values to reduce path circuitry (par. [0031]); FIG. 5 is a block diagram of example circuitry 500 of decision feedback equalizer paths 5 and 6 using the circuitry 300 and the circuitry 400 (par. [0034]); FIG. 6 is a block diagram of example circuitry 600 of a second embodiment of a decision equalizer path 6 that takes advantage of symmetry of path output values to reduce path circuitry (par. [0035]); and FIG. 7 is a block diagram of example circuitry 700 of a second embodiment of a decision equalizer path 5 that takes advantage of sequential computation of results in previous decision feedback equalizer paths (par. [0038]).
According to the invention recited in claims 1-14, the claim elements recited in claim 1 appear read on the embodiment of the decision equalizer path 6 (300) of FIG. 5; the claim elements recited in both claims 2 and 3 appear read on the embodiment of the decision equalizer path 5 (400) of FIG. 5; the claim elements recited in claims 8-10 appear read on the embodiment of the decision feedback equalizer paths 5 and 6 of FIG. 5; the claim elements recited in claims 4 and 11 appear read on the embodiment of the second embodiment of the decision equalizer path 6 of FIG. 6; and the claim elements recited in claims 5 and 12 appear read on the embodiment of the second embodiment of the decision equalizer path 5 of FIG. 7. However, as recited in claims 4, 5, 11, and 12, the specification fails to provide supports of the claim subject maters, for example, the specification fails to provide supports that the elements of adder (602) shown in FIG. 6 and the elements of adder (702) shown in FIG. 7 are the detail structures of the adders 32 and/or the adders 82 of FIG. 5. Further, as shown in Figures. 5-7, each of the multiplexers uses different numbers of inputs. In other words, the specification fails to describe how the multiplexers 306 (FIG. 5) and the multiplexer 610 (FIG. 6), and the multiplexers 406 (FIG. 5) and the multiplexer 710 (FIG. 6) are compatible with a different number of outputs of the adders.
Regarding claims 6 and 13, the claimed limitations of the third and fourth multiplexers are also not support by the specification. The third and fourth multiplexer recited in the claims appear relate to the multiplexers 314 and 306 shown in FIG. 3 and described in paragraph [0029].
Claim 7 depends from claim 6, therefore it is also rejected.
Claim 14 depends from claim 13, therefore it is also rejected.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim subject matter of the first and third multiplexers recited in claims 1-3 and the first and second multiplexers recited in claim 8 is vague and indefinite. In general, a multiplexer includes at least two inputs and one output, in other words, the phrase “a multiplexer” followed by only “a first input” and “an output” is considered indefinite because the claim language recited in the claims does not clearly delineate the boundaries of the invention and lacks necessary structural limitations to constitute a functional multiplexer. See the examiner’s proposed amendments above in the claim objections.
In claim 3 is also vague and indefinite because the same claim elements of “a third multiplexer”, “a second two’s complement circuit”, and “a fourth multiplexer” are already recited in the precedent claim 2. Clarification is required to clarify the differences. Claim 3 is suggested by the examiner to depend from claim 1 instead of claim 2.
In claim 6, claim 6 depends from claim 2, similar to claim 3, the same claim elements of “a third multiplexer” and “a fourth multiplexer” are already recited in the precedent claim 2. Clarification is required to clarify the differences.
Claims 4, 5, and 7 depend either directly or indirectly from claim 1, therefore they are also rejected.
Claims 9-14 depend either directly or indirectly from claim 8, therefore they are also rejected.
Allowable Subject Matter
Claims 1-3, 8-10, and 13-14 would be allowable if rewritten or amended to overcome the objection(s) set forth in this Office action.
Claims 1-3, 8-10, and 13-14 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
He relates to a DFE employing three-tap pre-computation in Figure 5 and a DFE employing parallel pre-computation units in Figure 6.
Aziz et al. relates to an apparatus that takes into account of operating voltage and temperature (VT) variations of a SER/DES receiver implemented in an integrated circuit, wherein the SER/DES receiver comprises an analog equalizer (AEQ) adaptation loop and a decision feedback equalizer (DFE) adaptation loop which are disabled after the loops have converged or stabilized the parameters of the AEQ and the DFE.
Palusa et al. relates to a DFE circuit illustrated in FIG. 7C includes: summing junctions 722; decision slicers 720; a multiplexor 724; and a latch or flip flop 726.
Ganesan et al. relates to a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Young T. Tse/Primary Examiner, Art Unit 2632