DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I (claims 1-9) in the reply filed on 06/30/2026 is acknowledged.
Claims 10-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claims. Therefore claims 10-15 have been cancelled.
Election was made without traverse in the reply filed on 06/30/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vook et al. (US 11,555,887).
Regarding claim 1, Vook et al. disclose a spectrum analyzer triggering system (100), comprising:
a frequency select trigger (FST) configured to generate a power signal from an input digital signal, the input power signal having high or low levels at given transmission intervals of the input digital signal (e.g. Col.5. lines 37-45: The voltage output by the RF power detector 130 indicating the power of the radar signal is input to the edge detecting circuit 140, which is configured to detect edges of the bursts of RF energy in the radar signal, respectively, and to provide a voltage waveform having pulses corresponding to the RF energy bursts. That is, each RF energy burst in the radar signal is represented by a pulse of high level voltage extending for a period of time corresponding to the length of the RF energy burst);
a hysteresis comparator configured to generate a trigger pulse at rising or falling edges of the input power signal (Col.5, lines 46-55: As mentioned above, each of the radar frames in the radar signal includes one or more of the RF energy bursts, depending on the type of radar signal. In an embodiment, the edge detecting circuit 140 may include an amplifier for amplifying the DC voltage output by the RF power detector 130, and a comparator for comparing the amplified voltage to a reference voltage, as discussed below with reference to FIGS. 4A and 4B. The comparator outputs a voltage waveform comprising pulses with corresponding rising and falling edges corresponding to the bursts of RF energy, Col.6, lines 7-16: as a digital circuit, the trigger generator 150 may generate rising and falling edge timestamps corresponding to the rising and falling edges of the voltage waveform pulses, respectively, and drive a finite state machine with the rising and falling edge timestamps to generate the trigger signals. That is, each of the rising and falling edge timestamps may advance the finite state machine until the trigger generator 150 outputs a trigger signal of predetermined length in response to entering the corresponding trigger generation state, Col.10, lines 1-15: Referring to FIG. 4A, the illustrative edge detecting circuit 140 includes a high speed amplifier 441 and a high speed comparator 442. The amplifier 441 amplifies the DC voltage output by the RF power detector 130, and the comparator 442 receives the amplified voltage and compares it to a reference voltage Vref. When the amplified voltage exceeds the reference voltage Vref, the comparator 442 outputs a high level voltage (1), and when the amplified voltage does not exceed the reference voltage Vref, the comparator 442 outputs a low level voltage (0), thereby generating a voltage waveform having pulses corresponding to the bursts of RF energy, respectively. Each of the pulses of the voltage waveform has corresponding rising and falling edges, which may be detected separately, as discussed above with reference to FIG. 3); and a leaky peak detector (LPD) configured to inhibit errant rising or falling edges of the input power signal from causing the hysteresis comparator to generate a trigger pulse (e.g. Col.14, lines 40-54: The trigger signal is de-asserted after a timeout period (e.g., 1 ms), and the finite state machine 600 transitions to state 607, looking for the first burst (e.g., long range burst) in the next radar frame of the radar signal, indicated by the trigger signal asserted at state 606. When a rising edge is detected, a timer (e.g., 1 ms timer) is started and the finite state machine 600 transitions to state 608, indicating a possible first burst. When a falling edge is detected within a predetermined rejection period (e.g., less than 0.60 ms), the corresponding pulse is rejected as a runt pulse (e.g., such as spurious pulse 315 shown in FIG. 3), and the finite state machine 600 returns to state 607 to continue looking for the first burst. When no falling edge is detected before the timer times out, the finite state machine 600 transitions to state 609, identifying a valid first burst of the radar frame).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vook et al. (US 11,555,887) in view of Hillman et al. (US 8,649,989, IDS record).
Regarding claim 2, Vook et al. fail to disclose wherein the digital signal is a complex IQ signal, and the power signal is generated having a magnitude I2 + Q2.
Hillman et al. teach the digital signal is a complex IQ signal and the power signal is generated having a magnitude I2 + Q2 (Col.1, lines 51-58: a digital downconverter to produce I (in-phase) and Q (quadrature) baseband component information from the digitized RF signal, a power detector to determine a power level using the I and Q baseband component information, and one or more demodulators to produce IQ-based time-domain traces when the power level determined by the power detector exceeds a predefined power threshold). It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Hillman et al. with the teaching of Vook et al. in order to provide enhanced triggering capabilities such as frequency and phase triggering in a test and measurement instrument (Hillman et al., abstract).
Regarding claim 18, Hillman et al. disclose an analog-to-digital converter configured to receive a wideband signal, wherein the power signal is generated based on a selected bandwidth of the wideband signal (e.g. Fig.1A, Col.2, lines 57-63, claim 10).
Allowable Subject Matter
Claims 3-9, 16-17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN H LE whose telephone number is (571)272-2275. The examiner can normally be reached on Monday-Friday from 7:00am – 3:30pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby A. Turner can be reached on (571) 272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN H LE/Primary Examiner, Art Unit 2857
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