DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-7 and 15-20, in the reply filed on 09/12/2025 is acknowledged. The traversal is on the ground(s) that no undue search burden exists and the claims of Group I and II are not patentably distinct. This is found persuasive and therefore the restriction has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Casey et al. (US 9,876,489).
In reference to claim 8 Casey discloses in Figure 2 a phase generator comprising:
a first logic gate branch comprising a pair of first branch transistors (214,216), the first logic gate branch configured to receive a first input clock signal (VΦ0) having a first phase; and
a second logic gate branch comprising a pair of second branch transistors (234,236), the second logic gate branch configured to receive a second input clock signal (VΦ1 bar) having a second phase, the second input clock signal having a clock frequency the same as the first input clock signal;
wherein the first logic gate branch and the second logic gate branch are bridged to generate an output signal (VΦmix bar) that has a phase shift as an average of the first phase and the second phase. The same applies to claim 15.
In reference to claim 9 Casey discloses in Figure 2 wherein the pair of first branch transistors comprises a first branch P-channel metal-oxide semiconductor (PMOS) transistor (216) and a first branch N-channel metal-oxide-semiconductor (NMOS) transistor (214), the first logic gate branch configured to receive the first input clock signal (VΦ0) at a gate terminal of the first branch PMOS transistor (216);
the pair of second branch transistors comprises a second branch PMOS transistor (236) and a second branch NMOS transistor (234), the second logic gate branch configured to receive the second input clock signal (VΦ1 bar) at a gate terminal of the second branch PMOS transistor (236);
wherein the first logic gate branch and the second logic gate branch are bridged with drain terminals of the first branch PMOS transistor (216) and the second branch PMOS transistor (236) connected. The same applies to claim 16.
Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lim et al. (US 11,411,555).
In reference to claim 8 Lim discloses in Figure 3 a phase generator comprising:
a first logic gate branch (202c) comprising a pair of first branch transistors (MP1, MN1), the first logic gate branch configured to receive a first input clock signal (clk_even) having a first phase; and
a second logic gate branch (202d) comprising a pair of second branch transistors (MP3, MN3), the second logic gate branch configured to receive a second input clock signal (clk_odd) having a second phase, the second input clock signal having a clock frequency the same as the first input clock signal;
wherein the first logic gate branch (202c) and the second logic gate branch (202d) are bridged to generate an output signal (at node n1) that has a phase shift as an average of the first phase and the second phase. The same applies to claim 15.
Allowable Subject Matter
Claims 1-7 are allowed.
Claims 10-14 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
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/CASSANDRA F COX/Primary Examiner, Art Unit 2849