DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 - 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (20210066279).
With regard to claim 1, Yu et al. disclose a semiconductor package (for example, see fig. 3) comprising:
a redistribution structure (130);
a semiconductor structure (referred to as “MD1” by examiner’s annotation shown in fig. 3 below) on the redistribution structure (130);
a plurality of semiconductor stacking structures (referred to as “MD2” by examiner’s annotation shown in fig. 3 below) on the redistribution structure (130),
the plurality of semiconductor stacking structures (MD2) being adjacent to the semiconductor structure (MD1), and
a height (referred to as “H2” by examiner’s annotation shown in fig. 3 below) of each of the plurality of semiconductor stacking structures (MD2) being greater than a height (referred to as “H1” by examiner’s annotation shown in fig. 3 below) of the semiconductor structure (MD1); and
a heat dissipation structure (structure 170, HC functions as a heat dissipation structure wherein the heat conduction block HC includes thermal conductivity larger than an encapsulant 170. Therefore structure 170, HC having the material 170 or 170, HC also functions a heat dissipation structure; for example, see paragraph [0039]) on the semiconductor structure (MD1), the heat dissipation structure (170, HC) comprising a plurality of through openings, (referred to as “OP” by examiner’s annotation shown in fig. 3 below) wherein each semiconductor stacking structure (MD2) among the plurality of semiconductor stacking structures (MD2) is positioned within a corresponding through opening (OP) among the plurality of through openings (OP), and wherein an upper surface of each of the plurality of semiconductor stacking structures (MD2) is exposed through the corresponding through opening (OP);
wherein a level of an upper surface (referred to as “T1” by examiner’s annotation shown in fig. 3 below) of the semiconductor structure (MD1) is greater (higher) than a level of a lower surface (referred to as “B1” by examiner’s annotation shown in fig. 3 below) of each semiconductor stacking structure (MD2) of the plurality of semiconductor stacking structures (MD2).
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With regard to claim 3, Yu et al. disclose a level of the upper surface of each of the plurality of semiconductor stacking structures (MD2) is equal to a level of an upper surface of the heat dissipation structure (170, HC).
With regard to claim 4, Yu et al. disclose the heat dissipation structure (170, HC) comprises silicon (for example, see paragraph [0039]).
With regard to claim 5, Yu et al. disclose the heat dissipation structure (170, HC) comprises a conductive material. (copper; for example, see paragraph [0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (20210066279) in view of Chen et al. (11869822).
With regard to claim 2, Yu et al. do not clearly disclose the upper surface of each of the plurality of semiconductor structures directly contacts a bottom surface of the heat dissipation structure.
However, Chen et al. disclose the upper surface of the semiconductor structure (120) directly contacts a bottom surface of the heat dissipation structure (162a). (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have the upper surface of each of the plurality of semiconductor structures directly contacts a bottom surface of the heat dissipation structure as taught by Lindsay et al. in order to enhance a high heat dissipation efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 6, Yu et al. do not clearly disclose a width of each through opening among the plurality of through openings in a horizontal direction decreases upwards in a vertical direction.
However, Chen et al. disclose a width of each through opening (referred to as “OP1” by examiner’s annotation shown in fig. 3 below) among the plurality of through openings (OP1) in a horizontal direction decreases upwards in a vertical direction. (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have a width of each through opening among the plurality of through openings in a horizontal direction decreases upwards in a vertical direction as taught by Lindsay et al. in order to enhance a high heat dissipation efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
4. Claims 7 - 17 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a bridge die on the redistribution structure; a first molding material molding the plurality of conductive posts and the bridge die on the redistribution structure; a semiconductor structure on the first molding material; a plurality of semiconductor stacking structures on the first molding material, the plurality of semiconductor stacking structures being adjacent to the semiconductor structure, and a height of each of the plurality of semiconductor stacking structures being greater than a height of the semiconductor structure; a heat dissipation structure on the semiconductor structure, the heat dissipation structure comprising a plurality of through openings, and each of the plurality of semiconductor stacking structures being positioned within a corresponding through opening of the plurality of through openings, and an upper surface of each of the plurality of semiconductor stacking structures being exposed through the corresponding through opening; and a second molding material, that molds the semiconductor structure and the plurality of semiconductor stacking structures, between the first molding material and the heat dissipation structure as recited in claim 7.
Response to Arguments
Applicant’s arguments filed 09/01/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “Yu fails to disclose or suggest at least "wherein a level of an upper surface of the semiconductor structure is greater than a level of a lower surface of each semiconductor stacking structure of the plurality of semiconductor stacking structures”. However, fig. 3 below of Yu et al. does show a level of an upper surface (referred to as “T1” by examiner’s annotation shown in fig. 3 below) of the semiconductor structure (MD1) is greater (higher) than a level of a lower surface (referred to as “B1” by examiner’s annotation shown in fig. 3 below) of each semiconductor stacking structure (MD2) of the plurality of semiconductor stacking structures (MD2).
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Conclusion
6. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
