Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 5, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 16, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendment filed August 5, 2026 has been entered. Claim 18 is cancelled and claim 22 is newly filed, leaving claims 1-17, 19, 21, and 22 pending in this application.
The amendment to the claims have overcome the objection to the claims, as presented in the prior office action mailed December 2, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (“Adaptive Granularity Based Last-Level Cache Prefetching Method with eDRAM Prefetch Buffer for Graph Processing Applications”) in view of Yoon et al. (“The Dynamic Granularity Memory System”).
Regarding claim 1, Choi teaches a processor (Fig. 1 showing the overall system architecture, see also table 2) comprising:
a cache comprising one or more cache lines each having a cache line size (Fig. 1 depicts a last level cache, also called the L3 cache in Table 2, with Table 2 also listing private L1 instruction and data caches for each core and L2 caches for each core, where Table 2 specifies that the cache features 64 byte block sizes, also described in Section 3, Paragraph 1 as the cache line size; Table 2 shows the overall size of each cache level, showing them to be a multiple of the cache line size);
a side buffer associated with the cache, the side buffer configured to store prefetched cache line data for storage in the one-cache lines (“The proposed eDRAM-based prefetch buffer is placed between the LLC and the main memory system,” Section 3, Paragraph 1, where the purpose of prefetching data is to retrieve data from the DRAM main memory and place into the prefetcher for use by the cache hierarchy, see Section 1, Paragraphs 8 and 9); and
a prefetcher (Fig. 1, controller has three different kinds of prefetcher modules, based on the granularity of request, see Section 3.1, Paragraph 1) configured to:
generate a prefetch request identifying data to be prefetched from a memory (“In our proposed model, prefetching operations only occurs for DRAM. In other words, only prefetched data are stored in the prefetch buffer… To conduct the prefetching, the controller determines whether the current access is on the same correlated as the previous access. When the accessed address is on the same correlated line, the controller analyzes the access pattern through modules I and II. When it does not exist on the same correlated line, the controller conducts a prefetching aggressively through module III,” Section. 3.4, Paragraph 2, where Sections 3.3.1, 3.3.2, and 3.3.3 provide more detail on the prefetching operations, where prefetching for DRAM teaches that the requests fetch data from the DRAM);
responsive to the prefetch request, receive the data from the memory (“If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2, necessarily teaching that the controller receives the fetched data); and
store the data in the side buffer as the prefetched cache line data for retrieval by the cache (“If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2).
Choi fails to teach where the one or more cache lines comprises one or more sub-cache lines, each sub-cache line being a subdivision of a respective cache line of the one or more cache lines and having a size that is less than the cache line size and therefore fails to teach where the prefetched data is specifically sub-cache line data. While Choi does operate with knowledge of different granularity patterns, see Section 3, Paragraph 1, none of those granularities is specifically a sub-cache line granularity. Choi also fails to teach where the memory data is fetched from is specifically fine grained, and as such also fails to teach where the prefetcher is fine-grained memory aware and the prefetch request is a fine-grained prefetch request and further where the data identified to be prefetched/received has a size less than the cache line size.
Yoon’s disclosure relates to providing memory system with dynamic granularities, and in particular the ability to operate in fine grained memory accesses, and as such comprises analogous art as being directed to the same field of endeavor of main memories.
As part of this disclosure, Yoon discloses that the proposed dynamic granularity memory system (DGMS) is an extension of an adaptive granularity memory system (AGMS), where DGMS allows for both coarse and fine grained memory accesses, see Section 1, Paragraph 4. To accomplish this, Yoon discloses that AGMS utilized a sector cache, where a 64B cache line was broken up into eight 8B subsectors allowing for management of FG data blocks, see Section 2.2. This allows for FG accesses, such as DRAM fetches/reads, where fine grained reads can fetch data and ECC from individual words while also leaving invalid subsectors of unrequested words, see Section 3.1, Paragraphs 3-5 and Figs. 5 and 6(a).
Yoon further discloses the use of hardware predictors to identify words within cache lines that are likely to be referenced, see Section 3.3, Paragraph 2, with further details in Sections 3.3.1 and 3.3.2, with the spatial pattern predictor of Section 3.3.1 being particularly notable for containing pattern/history tables similar to Choi’s tracking reference counts and related instructions and locality information, which results in a global prediction decision logic that also affects how to assign a mode for operation, whether in coarse grain or fine graine, see Fig. 9.
An obvious modification can be identified: incorporating Yoon’s DGMS into Choi’s DRAM main memory and also implementing the sub-cache line/word-level locality information of Yoon’s pattern and history tables into Choi’s prefetcher module history tables. Such a modification reads upon the limitation of the claim, as Yoon explicitly states that each cache line has multiple sectors (reading on the one or more sub-cache lines in the cache lines, where the sectors are a subdivision of a cache line and the size of a sector is less than the cache line size), provides the ability to access data/fetch data at a sector/word level fine granularity, reading upon the fine-grained memory, and the predictor shows the ability to track fine-grained operations with the spatial locality of words within the cache line, where incorporating this into Choi provides for a finer granularity of prediction/prefetching, reading upon the fine-grained prefetch request and pre-fetching sub-cache line data specifically. Further, as Yoon’s DGMS shows the ability to read specific words, then this reads on identifying data of a prefetch request that is less than the cache line size and receiving the data. Examiner notes that right now, the claim scope is broad enough that data received in the prefetch request can still include additional data like Yoon’s ECC for invalid/unrequested sectors.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Yoon’s DGMS and predictors tracking words within cache lines into Choi’s DRAM main memory system and prefetch buffer, as “Most applications touch less than 50% of each cache line, and a CG-only memory system wastes off-chip bandwidth and power for fetching unused data. A memory system that makes only a fine-grained (FG) access eliminates this minimum-granularity problem and may achieve higher system throughput than a CG-only memory system”, Section 1, Paragraph 2.
Regarding claim 2, the combination of Choi and Yoon teaches the processor of claim 1, and Choi further teaches wherein the cache comprises a cache hierarchy comprising a level 1 cache, a level 2 cache, and a last level cache (Table 2, showing the system configuration with L1 instruction and data caches for each core, L2 caches for each core, and a L3 unified shared cache, where Section 4.1.2, Paragraph 1 explicitly labels the L3 cache as the LLC).
Regarding claim 3, the combination of Choi and Yoon teaches the processor of claim 2, and Choi further teachers wherein the side buffer is deployed between the fine-grained memory and the last level cache (“The proposed eDRAM-based prefetch buffer is placed between the LLC and the main memory system,” Section 3, Paragraph 1).
Regarding claim 4, the combination of Choi and Yoon teaches the processor of claim 3, wherein the prefetched sub-cache line data comprises a prefetched atom (as discussed in the claim 1 rationale, Yoon provides for FG DRAM reads, where individual words can be fetched, see Section 3.1, Paragraphs 3-5, with the individual sectors/words reading on the atoms).
Regarding claim 5, the combination of Choi and Yoon teaches the processor of claim 4, wherein the prefetched atom has an atom size that is less than 64 bytes (as discussed in the claim 1 rationale, Yoon depicts a cache line split up into 8 subsectors/words, where each word has a size of 8B, see Section 2.2).
Regarding claim 6, the combination of Choi and Yoon teaches the processor of claim 5, wherein the fine-grained prefetch request identifies the atom size based on a size of the one or more sub-cache lines (as discussed in the claim 1 rationale, Yoon discloses FG DRAM reads identifying individual or multiple words to fetch, with the example of Fig. 6(a) and Section 3.1, Paragraph 4 fetching only 3 words out of the cache line – necessarily, the ability to identify individual words would be contingent on identifying the particular sectors, which are in turn dependent on the sector size).
Regarding claim 7, the combination of Choi and Yoon teaches the processor of claim 1, wherein the fine-grained memory aware prefetcher is further configured to:
select a load instruction associated with the data to be prefetched (as part of the claim 1 rationale, Yoon disclosed a prediction control mechanism to identify words for spatial locality, where the pattern history table can track the behavior of load/store instructions, see Section 3.3.1, Paragraph 4);
perform a cache lookup in the cache for a physical address associated with the load instruction (as part of the claim 1 rationale, Yoon disclosed a prediction control mechanism to identify words for spatial locality, where the current pattern table keeps track of words that are referenced in the L1 cache lines, see Section 3.3.1, Paragraph 2; necessarily, with every cache access, including the load/store instructions being tracked, the caches would be searched to determine whether an entry is already existing);
perform a side buffer lookup in the side buffer for the physical address associated with the load instruction (as part of the cache hierarchy of Choi, misses go to lower levels of caches, where LLC misses can make demand requests of the buffer, including sending a request address, see Figure 6); and
responsive to a hit in the cache lookup or the side buffer lookup, perform a prefetcher training table lookup in a prefetcher training table (Yoon’s predictor updates the PHT upon evicting a cache line, see Section 3.3.1, Paragraph 3, where a cache line being evicted necessarily means that there was a hit earlier; updating the PHT would also require a look up to determine whether the entry still exists, see also “The page table update depends on whether the page number of the current accessed address is already stored in it. If this page number is already stored, we update the CorLine_Info index stored by the block. By contrast, when the address does not exist in the page table, it will be stored sequentially if there is enough space” from Choi Section 3.2.1).
Regarding claim 8, the combination of Choi and Yoon teaches the processor of claim 7, wherein the fine-grained memory aware prefetcher is further configured to, responsive to a hit in the prefetcher training table lookup, update an entry in the prefetcher training table (“The page table update depends on whether the page number of the current accessed address is already stored in it. If this page number is already stored, we update the CorLine_Info index stored by the block. By contrast, when the address does not exist in the page table, it will be stored sequentially if there is enough space” Choi Section 3.2.1).
Regarding claim 9, the combination of Choi and Yoon teaches the processor of claim 7, wherein the fine-grained memory aware prefetcher is further configured to, responsive to a miss in the prefetcher training table lookup, allocate a new table entry in the prefetcher training table (“The page table update depends on whether the page number of the current accessed address is already stored in it. If this page number is already stored, we update the CorLine_Info index stored by the block. By contrast, when the address does not exist in the page table, it will be stored sequentially if there is enough space” from Choi Section 3.2.1).
Regarding claim 10, Choi teaches a system (Fig. 1 showing overall system architecture, see also Table 2) comprising:
a memory (fig. 1, DRAM main memory); and
a cache comprising one or more cache lines each having a cache line size,
a prefetcher (Fig. 1, controller has three different kinds of prefetcher modules, based on the granularity of request, see Section 3.1, Paragraph 1) configured to:
generate a prefetch request identifying data to be prefetched from the memory (“In our proposed model, prefetching operations only occurs for DRAM. In other words, only prefetched data are stored in the prefetch buffer… To conduct the prefetching, the controller determines whether the current access is on the same correlated as the previous access. When the accessed address is on the same correlated line, the controller analyzes the access pattern through modules I and II. When it does not exist on the same correlated line, the controller conducts a prefetching aggressively through module III,” Section. 3.4, Paragraph 2, where Sections 3.3.1, 3.3.2, and 3.3.3 provide more detail on the prefetching operations, where prefetching for DRAM teaches that the requests fetch data from the DRAM);
responsive to the prefetch request, receive the data from the memory (“If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2, necessarily teaching that the controller receives the fetched data); and
store the data in a side buffer for retrieval by a cache (“The proposed eDRAM-based prefetch buffer is placed between the LLC and the main memory system,” Section 3, Paragraph 1, see also Fig. 1, where the purpose of prefetching data is to retrieve data from the DRAM main memory and place into the prefetcher for use by the cache hierarchy, see Section 1, Paragraphs 8 and 9; see also “If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2, necessarily teaching that the controller receives the fetched data).
Choi fails to teach where the one or more cache lines comprise one or more sub-cache lines, each sub-cache line being a subdivision of a respective cache line of the one or more cache lines and having a size that is less than the cache line size. Choi also fails to teach where the memory data is fetched from is specifically fine grained, and as such also fails to teach where the prefetch request is specifically a fine-grained prefetch request, with the data requested and received being less than the cache line size.
Yoon’s disclosure relates to providing memory system with dynamic granularities, and in particular the ability to operate in fine grained memory accesses, and as such comprises analogous art as being directed to the same field of endeavor of main memories.
As part of this disclosure, Yoon discloses that the proposed dynamic granularity memory system (DGMS) is an extension of an adaptive granularity memory system (AGMS), where DGMS allows for both coarse and fine grained memory accesses, see Section 1, Paragraph 4. To accomplish this, Yoon discloses that AGMS utilized a sector cache, where a 64B cache line was broken up into eight 8B subsectors allowing for management of FG data blocks, see Section 2.2. This allows for FG accesses, such as DRAM fetches/reads, where fine grained reads can fetch data and ECC from individual words while also leaving invalid subsectors of unrequested words, see Section 3.1, Paragraphs 3-5 and Figs. 5 and 6(a).
Yoon further discloses the use of hardware predictors to identify words within cache lines that are likely to be referenced, see Section 3.3, Paragraph 2, with further details in Sections 3.3.1 and 3.3.2, with the spatial pattern predictor of Section 3.3.1 being particularly notable for containing pattern/history tables similar to Choi’s tracking reference counts and related instructions and locality information, which results in a global prediction decision logic that also affects how to assign a mode for operation, whether in coarse grain or fine graine, see Fig. 9.
An obvious modification can be identified: incorporating Yoon’s DGMS into Choi’s DRAM main memory, and also implementing the sub-cache line/word-level locality information of Yoon’s pattern and history tables into Choi’s prefetcher module history tables. Such a modification reads upon the limitation of the claim, as Yoon explicitly states that each cache line has multiple sectors (reading on the one or more sub-cache lines in the cache lines, where the sectors are a subdivision of a cache line and the size of a sector is less than the cache line size), provides the ability to access data/fetch data at a sector/word level fine granularity, reading upon the fine-grained memory, and the predictor shows the ability to track fine-grained operations with the spatial locality of words within the cache line, where incorporating this into Choi provides for a finer granularity of prediction/prefetching, reading upon the fine-grained prefetch request. Further, as Yoon’s DGMS shows the ability to read specific words, then this reads on identifying data of a prefetch request that is less than the cache line size and receiving the data. Examiner notes that right now, the claim scope is broad enough that data received in the prefetch request can still include additional data like Yoon’s ECC for invalid/unrequested sectors.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Yoon’s DGMS and predictors tracking words within cache lines into Choi’s DRAM main memory system and prefetch buffer, as “Most applications touch less than 50% of each cache line, and a CG-only memory system wastes off-chip bandwidth and power for fetching unused data. A memory system that makes only a fine-grained (FG) access eliminates this minimum-granularity problem and may achieve higher system throughput than a CG-only memory system”, Section 1, Paragraph 2.
Regarding claim 11, the combination of Choi and Yoon teaches the system of claim 10, and Choi teaches the system further comprising a processor including the side buffer, the cache, and the prefetcher, the cache comprising a cache hierarchy (Fig. 1, showing a system architecture for a processor, see also table 2).
Claims 12-17 are rejected according to the same rationale of claims 3-8 respectively.
Regarding claim 19, Choi teaches a method comprising:
generating, by a prefetcher, a prefetch request identifying data to be prefetched from a memory (“In our proposed model, prefetching operations only occurs for DRAM. In other words, only prefetched data are stored in the prefetch buffer… To conduct the prefetching, the controller determines whether the current access is on the same correlated as the previous access. When the accessed address is on the same correlated line, the controller analyzes the access pattern through modules I and II. When it does not exist on the same correlated line, the controller conducts a prefetching aggressively through module III,” Section. 3.4, Paragraph 2, where Sections 3.3.1, 3.3.2, and 3.3.3 provide more detail on the prefetching operations, where prefetching for DRAM teaches that the requests fetch data from the DRAM);
responsive to the fine-grained prefetch request, receiving, by the prefetcher, the data from the fine-grained memory (“If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2, necessarily teaching that the controller receives the fetched data); and
storing, by the prefetcher, the data in a side buffer as prefetched sub-cache line data for retrieval by a cache (“If the prefetch engine executes the prefetching, the fetched data are stored in the prefetch buffer by the controller,” Section 3.4, Paragraph 2).
Choi fails to teach where the memory is fine-grained, and as such fails to teach the prefetch request is specifically fine-grained, the data having a size that is less than a cache line size of a cache line of a cache, the cache line comprising one or more sub-cache lines, each sub-cache line being a subdivision of the cache line and having a size that is less than the cache lien size. Further, Choi fails to teach where the data prefetched is specifically prefetched sub-cache line data having a size that is less than the cache line size. While Choi does operate with knowledge of different granularity patterns, see Section 3, Paragraph 1, none of those granularities is specifically a sub-cache line granularity.
Yoon’s disclosure relates to providing memory system with dynamic granularities, and in particular the ability to operate in fine grained memory accesses, and as such comprises analogous art as being directed to the same field of endeavor of main memories.
As part of this disclosure, Yoon discloses that the proposed dynamic granularity memory system (DGMS) is an extension of an adaptive granularity memory system (AGMS), where DGMS allows for both coarse and fine grained memory accesses, see Section 1, Paragraph 4. To accomplish this, Yoon discloses that AGMS utilized a sector cache, where a 64B cache line was broken up into eight 8B subsectors allowing for management of FG data blocks, see Section 2.2. This allows for FG accesses, such as DRAM fetches/reads, where fine grained reads can fetch data and ECC from individual words while also leaving invalid subsectors of unrequested words, see Section 3.1, Paragraphs 3-5 and Figs. 5 and 6(a).
Yoon further discloses the use of hardware predictors to identify words within cache lines that are likely to be referenced, see Section 3.3, Paragraph 2, with further details in Sections 3.3.1 and 3.3.2, with the spatial pattern predictor of Section 3.3.1 being particularly notable for containing pattern/history tables similar to Choi’s tracking reference counts and related instructions and locality information, which results in a global prediction decision logic that also affects how to assign a mode for operation, whether in coarse grain or fine graine, see Fig. 9.
An obvious modification can be identified: incorporating Yoon’s DGMS into Choi’s DRAM main memory, and also implementing the sub-cache line/word-level locality information of Yoon’s pattern and history tables into Choi’s prefetcher module history tables. Such a modification reads upon the limitation of the claim, as Yoon explicitly states that each cache line has multiple sectors (reading on the one or more sub-cache lines in the cache lines, where the sectors are a subdivision of a cache line and the size of a sector is less than the cache line size), provides the ability to access data/fetch data at a sector/word level fine granularity, reading upon the fine-grained memory, and the predictor shows the ability to track fine-grained operations with the spatial locality of words within the cache line, where incorporating this into Choi provides for a finer granularity of prediction/prefetching, reading upon the fine-grained prefetch request and pre-fetching sub-cache line data specifically. Further, as Yoon’s DGMS shows the ability to read specific words, then this reads on identifying data of a prefetch request that is less than the cache line size and receiving the data. Examiner notes that right now, the claim scope is broad enough that data received in the prefetch request can still include additional data like Yoon’s ECC for invalid/unrequested sectors.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Yoon’s DGMS and predictors tracking words within cache lines into Choi’s DRAM main memory system and prefetch buffer, as “Most applications touch less than 50% of each cache line, and a CG-only memory system wastes off-chip bandwidth and power for fetching unused data. A memory system that makes only a fine-grained (FG) access eliminates this minimum-granularity problem and may achieve higher system throughput than a CG-only memory system”, Section 1, Paragraph 2.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Yoon and further in view of Guim Bernat et al. (US 2017/0353576).
The combination of Choi and Yoon teaches the processor of claim 1, but fails to teach wherein the fine-grained prefetch request identifies the size of the data to be prefetched.
While the request does not identify the size, the rationale of claim 1 does provide how Choi and Yoon can incorporate sub-cache line requests into a prefetching system, see Yoon Section 3.1, Paragraphs 3-5 and Figs. 5 and 6(a) discussing and depicting how data fetched can be less than a cache line size. Choi and Yoon fail to teach where the size information is found in the request itself.
Guim Bernat’s disclosure relates to a prefetching system, and as such comprises analogous art.
As part of this disclosure, Guim Bernat provides for a prefetching system in Fig. 1, where a processor 106A may generate prefetch requests. As part of this, “the prefetch request may specify a size of the data to be prefetched. The size may be indicated in any suitable manner. For example, the size may be specified by an integer that represents the number of cells, bytes, wordlines, pages, blocks, or other unit of memory that should be prefetched. In a particular embodiment, the group of data to be prefetched by a prefetch request is specified by an address (e.g., a beginning address or an end address) and a size of the data to be prefetched. Any suitable size may be specified by the requesting entity and the size may be varied between successive prefetch requests by the same entity,” [0065].
An obvious modification can be identified: incorporating Guim Bernat’s disclosure of including size information into prefetch requests into Choi’s memory system as modified by Yoon. Such a modification reads upon the limitation of the claim, as then a prefetch request includes information such as the size of data to be prefetched, where as earlier stated, the combination of Choi and Yoon provide where the size can be a sub-cache line size.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Guim Bernat’s size information in prefetch requests into Choi’s system, as this provides the system with greater amount of detailed information necessary for processing prefetching requests.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Yoon and further in view of Joshi et al. (US 2011/0145502)
The combination of Choi and Yoon teaches the processor of claim 1, but fails to teach wherein the fine-grained prefetch request is marked as non-temporal.
Joshi’s disclosure is related to prefetching, and as such comprises analogous art in the same field of endeavor of prefetching.
As part of this, Joshi discloses that meta information indicative of data access pattern is used for prefetching, where the meta information includes marking the prefetch as temporal or non-temporal, [0009]. For more detail, Joshi provides that marking the data as temporal or non-temporal is indicative of “whether the data is not going to be used for sufficiently long time indicating that the hardware prefetcher should prefetch the data non-temporally and vice versa… Prefetch operations (e.g., hardware or software prefetches) may have a temporal or non-temporal type. Since recently accessed data are likely to be needed again in the near future, the data is placed in the cache where it can be accessed quickly. A temporal prefetch prefetches data to a low-level cache (e.g., level-1 cache 14) and the data is later evicted to a higher-level cache (e.g., level-2 cache 16). A non-temporal prefetch prefetches data into level-1 of the cache, without evicting data to level-2 cache 16 or other levels of cache 13 unless the data access resulted in a hit in a higher-level cache” [0018].
An obvious modification can be identified: incorporating Joshi’s disclosure of marking prefetches as either temporal or non-temporal type, where marking the prefetches as non-temporal reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Joshi’s ability to mark temporal/non-temporal prefetches, as “ Non-temporal prefetches reduce cache pollution, i.e., situations where an executing application loads data into a level of the cache unnecessarily. Cache pollution causes other data needed by the processor to be evicted from a cache level into higher-levels of the memory hierarchy, potentially all the way up to main memory, thereby impacting performance. Thus, non-temporal prefetches are useful when prefetched data is not likely to be accessed again by the processor soon after its initial use,” [0018].
Response to Arguments
Applicant's arguments filed August 5, 2026 have been fully considered and are moot in part and unpersuasive in part.
The new dependent claim recited subject matter that sufficiently narrowed the claims around Choi and Yoon. However, upon an updated search of the art, Joshi was found to provide a disclosure capable of rendering this feature obvious, and as such the arguments are moot in part for a lack of opportunity to address the new rationale incorporating Joshi.
The arguments against Choi and Yoon are ultimately unpersuasive. Upon reconsideration of the claims in view of the interview conducted July 30, 2026 examiner finds that the current claim scope does not match the claim scope that was discussed in the interview. In the interview, the subject matter discussed was specifically where the size of the total transfer was less than a cache line size or where the data transferred was only the requested data, as merely reciting the size of the data requested/received did not narrow the scope to overcome Yoon in particular. The claims as currently amended recite where the prefetch request data size can be smaller than the cache line, but this does not explicitly exclude situations where the transfer of data still comprises a whole cache line as in Yoon. As such the arguments are unpersuasive as the scope of the claim is broader than argued.
Examiner notes that as discussed in the interview, if the claims’ scopes are amended to explicitly exclude where the requested sub-cache line data can be transferred along with some extra data or where the total data transferred in response to a prefetch request is only the requested sub-cache line data, then this would sufficiently overcome Choi and Yoon.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kannan et al. (US 2013/0254485) discloses prefetching data being associated with a temporal/non-temporal attribute,
Akin et al. (US 2018/0285280), discloses sub-page and fine-grained memory accesses, [0033,0037]; for clarity of record, examiner initially considered suggesting an examiner’s amendment to incorporate the language discussed in the interview to overcome Choi and Yoon, but upon an updated search of the art, Akin was found that discloses providing accesses that are less than a cache line size and only the accessed data; Akin is not considered necessary to incorporate into a rejection at this point, but examiner makes note that this reference does appear to potentially provide an obviousness rationale to address the narrower limitations discussed in the interview,
Vimercati et al. (US 2022/0385451) discloses prefetching a subpage based on address sizes received with requests, a review of Vimercati does not appear to be as clear as Akin concerning whether a prefetch can compose only the requested subpage,
Ray et al. (US 2023/0104845) discloses where a prefetch can indicate if associated data is temporal or non-temporal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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