Prosecution Insights
Last updated: October 02, 2026
Application No. 18/428,982

METHODS AND APPARATUS TO REJECT CURRENT RIPPLE

Non-Final OA §102
Filed
Jan 31, 2024
Priority
Aug 07, 2023 — provisional 63/531,051
Examiner
NGUYEN, HIEU P
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1145 granted / 1243 resolved
+32.1% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
19 currently pending
Career history
1258
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1243 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (U.S. 2021/0216092). Regarding claim 15, Chang et al. (hereinafter, Ref~092) discloses (please see Fig. 3 and related text for details) an apparatus (300 of Fig. 3) comprising: a low dropout regulator (302 of Fig. 3) including: an error amplifier (318 of Fig. 3) having a first input (e.g., inverting terminal of 318 of Fig. 3), a second input (non-inverting terminal of 318 of Fig. 3), and an output (output of 318 of Fig. 3), the first input coupled to a reference voltage (VREF of Fig. 3), the second input coupled to an output (VOUT 308 of Fig. 3) of the low dropout regulator; a pass transistor (MP1 of Fig. 3) having a control terminal (gate of MP1), a first current terminal (drain or source of MP1 of Fig. 3), and a second current terminal (source or drain of MP1), the control terminal coupled to the output of the error amplifier, the second current terminal coupled to the output of the low dropout regulator; and a circuit (304 of Fig. 3) having a first input, a second input, and an output, the first input of the circuit coupled to the control terminal of the pass transistor, the second input of the circuit coupled to the first current terminal of the pass transistor, the output of the circuit coupled to the output of the low dropout regulator, the circuit configurable to attenuate (at least via MN7 of Fig.3 configured to carry and/or shunt current between VOUT and ground; also see paragraph [0044] for details) a ripple current at output of the low dropout regulator responsive to states of the first and second inputs, meeting claim 15. Allowable Subject Matter Claims 16-18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all limitations of the base claim and any intervening claims. Allowable Subject Matter Claims 1-14 and 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: Claims 1-14 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “…the processing circuit including a first signal path and a second signal path coupled in parallel between the input and the output, the first signal path including a high-pass filter, and the second signal path including a low-pass filter” structurally and functionally interconnected with other limitations in the manner as cited in the claims. Claims 19-20 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations “the circuit including: a sensing transistor configurable to sense the current passing through the pass transistor; an amplifier having a gain, the amplifier configurable to amplify a signal the signal indicative of a current ripple through the pass transistor; a transistor configurable to inject the signal indicative of the current ripple into an output of the low dropout regulator circuit, the signal indicative of current ripple being 180 degrees out of phase with a sensed current ripple” structurally and functionally interconnected with other limitations in the manner as cited in the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Jan 31, 2024
Application Filed
Aug 26, 2026
Request for Continued Examination
Aug 27, 2026
Response after Non-Final Action
Sep 04, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.1%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1243 resolved cases by this examiner. Grant probability derived from career allowance rate.

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