DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-12 & 14 & 16-17 & 9 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Tran et al (US20220067499).
Regarding claim 1, Tran discloses a device comprising: a memory cell array(FIG 10; 33); and logic circuitry configured to: program first memory cells of the memory cell array to store first weights(FIG 10; [0033] discloses comprising memory array comprising cells, 35 programming and 33 stores weights); determine a context of the memory cell array(FIG 10 & 17A-17B verifying and programming e.g., verifying (determine the context e.g., state of the cell) and ; adjust, based on the determined context, a bias applied to at least one first access line coupled to the first memory cells(FIG 17A-17B; [0036 & 0103] discloses control circuity controlling programming of memory cell to a weight target such as controlling the bit lines bias voltage e.g., adjusting).
Regarding claim 3, Tran discloses wherein the logic circuitry is further configured to provide at least one first result from the multiplication, and send, via a host interface, the first result to a host (FIG 10; result from multiplication 33 is sent to 39 via ARY interface).
Regarding claim 4, Tran discloses wherein the first access line is a wordline (FIG 10 WLs).
Regarding claim 5, Tran discloses wherein the first access line is a bitline (FIG 10; BLs).
Regarding claim 6, Tran discloses wherein the memory cells are resistive random-access memory (RRAM) cells, phase-change memory (PCM) cells, NOR flash memory cells, or NAND flash memory cells (FIG 9-10; [0026] NAND flash).
Regarding claim 7, Tran discloses wherein the context includes values of weights stored in at least a portion of the first memory cells (FIG 10 & 17A-18B, wherein 33 effectively multiplies inputs by weights stored in 33 and adds them up per output lines to produce the output).
Regarding claim 8, Tran discloses wherein the context includes at least one of a temperature associated with the first memory cells when being programmed, or a temperature associated with the first memory cells when performing the multiplication (FIG 10, 17A-17B; [0042] discloses temperature).
Regarding claim 9, Tran discloses wherein the memory cell array comprises at least one reference cell, and the determined context includes a condition of the reference cell (FIG 10; [0044] discloses I to V converter using memory cell such as reference memory cell in order to convert input current IDS, into an input voltage Vg).
Regarding claim 10, Tran discloses wherein the logic circuitry is further configured to perform background scans when the memory cell array is not being used in an operation for a host, and wherein the context is determined using the background scans (FIG 9-10; [0028-0030] discloses hidden L1-L3 and scan input image with pixel 3X3, and filter scans across the entire 32 by 32-pixel imager input layer and so on C1 to layer S1).
Regarding claim 11 Tran discloses wherein a host is configured to keep track of a physical address for a location last programmed in the memory cell array, and the determined context includes the physical address (FIG 9-11; [003] pooling function P1 to average r out nearby location, e.g., reducing dependence of edger location and reduce data size before going to the next state).
Regarding claim 12, Tran discloses a system comprising(FIG 9-10): at least one sensor; a plurality of wordlines(FIG 10 WLs and BLs); sensing circuitry coupled to the wordlines and configured to measure currents associated with memory cells(FIG 10; [0032-0034] discloses I ANAIN[0:N] to 34, and 33 multiplying inputs by weights stored in 33 and adds them up per output lines source line e.g., 37 to produces output e.g., sensing currents); and voltage drivers configured to apply voltages to the wordlines (FIG 10; 35 applying to wordlines in array in 33 and CNTRL to 34 that is connected to WLx gate);
Regarding claim 14, Tran discloses wherein the output currents are accumulated for a matrix vector multiplication used to generate an inference output from a neural network (FIG 11).
Regarding claim 16, Tran discloses the memory cells are NAND flash memory cells(FIG 12); the controller is further configured to maintain a constant output current for each of the memory cells during each of a plurality of multiplication operations(FIG 10-12; Is); and voltages applied to the wordlines are adjusted for each of the multiplication operations based on string currents measured by the sensing circuitry (FIG 17A-17B; discloses 1721 sensing circuity and writing circuitry 1722, wherein verifying e.g., seining and programming is done concurrently on array e.g., adjusting voltages).
Regarding claim 17, Tran discloses an apparatus comprising: a semiconductor substrate; a memory cell array formed above the semiconductor substrate(FIG 9-11; [0114] element e.g., array formed over semiconductor substrate); and a controller formed on the semiconductor substrate and configured to: measure a current flowing through first memory cells connected in series((FIG 10; [0032-0034] discloses I ANAIN[0:N] to 34, and 33 multiplying inputs by weights stored in 33 and adds them up per output lines source line e.g., 37 to produces output e.g., sensing currents); and adjust, based on the measured current, a bias voltage applied to the first memory cells(FIG 10, 17A-17B; [0103] discloses control circuity controlling programming of memory cell to a weight target such as controlling the bit lines bias voltage e.g., adjusting based on measured currents).
Regarding claim 19, Tran discloses wherein the memory cell array comprises NAND flash memory cells organized in pillars extending vertically upward from the semiconductor substrate (FIG 11 string NAND flash).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al in view of Seo et a l(US20200152256).
Regarding claim 15, Tran discloses wherein the controller is further configured to adjust the voltages applied to the wordline FIG 17A-17B; [0036& 0103] discloses control circuity controlling programming of memory cell to a weight target such as controlling the bit lines bias voltage e.g., adjusting)
However, Tran does not disclose based on a time that has elapsed since programming the memory cells (FIG 17B; [0120-0122] discloses ACT command, activation votlage VA1 to selected wordline and deactivation voltage to VDA_v1 unselected, wherein after give time elapses time to when ACT is received to t1, memory device decreases a voltage of selected wordline from VA1 to VA2 and unselected from VDA_v1 to VDA-v2).
Tran and Seo are analogous art because they are all directed to a memory device comprising a flash memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Tran to include Seo because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Seo for the benefits avoiding high disturbances that may occur within the memory device due to a high voltage provided to the access line). (Seo [0004]).
Regarding claim 20, Tran discloses wherein: the memory cells are NAND flash memory cells; the current is a string current (FIG 11; string NAND flash); a bypass voltage is applied to the first memory cells when measuring the string current and the bias voltage is (FIG 10 & 17’ [0034 & 0101-0103] discloses 33 supplied to a differential summer e.g., summing op-amp difference wherein 1722 controls programming of memory cells to a target current such as controlling the bit line bias voltage(adjusting) or program current levels).
However, Tran does not disclose adjusted based on a difference in magnitude of the string current from a magnitude of a target string current.
In the same field of Seo discloses adjusted based on a difference in magnitude of the string current from a magnitude of a target string current (FIG 17B; [0121] discloses various parameters magnitude of activation voltage VA2 and deactivation voltage VDA_v1, a decrement of a variable deactivation voltage, a reference time in advance/ updated while the memory device operation, and adjusted a voltage of selected wordline and unselected wordlines during tRAS period).
Allowable Subject Matter
Claims 2, 13 & 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Regarding claim 2, Tran discloses wherein the logic circuitry is further configured to receive, via a host interface, the first inputs from a host (FIG 17A-17B; 1710); perform multiplication of the first weights by first inputs by summing output currents from the first memory cells, wherein the adjusted bias is applied to the first memory cells during the multiplication (FIG 10 & 17A-18B, wherein 33 effectively multiplies inputs by weights stored in 33 and adds them up per output lines to produce the output).
However, regarding to claim 2, the highlighted portion as whole combined with claim 1, it is allowable. Note, the allowability subject matter is allowed as a whole in combinations with claim 1, not just taken as a portion.
Regarding claim 13, Tran discloses wherein the controller is further configured to program the memory cells to target output currents, and wherein the voltages are adjusted to return the memory cells to the target output currents (FIG 10 & 17’ [0101-0103] discloses 1722 controls programming of memory cells to a target current such as controlling the bit line bias voltage(adjusting) or program current levels).
Regarding claim 18, Tran discloses wherein prior to performing the multiplication, the first memory cells are programmed to respective threshold voltages corresponding to values of weights for a neural network (FIG 10; [0033] 33 stores weights that will be used by VMM system prior to multiplying inputs by the weights stored in VMM array 33).
The same explanation of claim 2, is applied to claims 13 & 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al (US20230027768 FIG 1 & 8B; [0061] discloses memory device storing weight value of matrix multiplication, and weight value stored in the flash memory cell that is changed by adjusting the threshold voltage of a transistor).
Micheloni et al (US6144589 FIG 1 discloses signal 3 supply row decoder that generates signal 5 and driving stages 400, and selecting each one of rows of memory cells matrix 16).
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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