DETAILED ACTION
This action is responsive to the communications filed on 1/31/2024.
Currently, claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-11 and 13-14 are concurrently rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Rajapaksha et al. (US 2019/0386703: hereinafter “Rajapaksha”).
With regards to claim 8, A method of receiving power and data signals over a differential pair of conductors (see figs. 2-4: where figure 2 addresses that DC (or AC) power signals and RS485/RS422 data pulses/signals are concurrently communicated on the same pair of wires/conductors between two devices, also see [0013]. Which include transmitting/receiving data signals and receiving power (“Power In”) via a differential pair of conductors differential signals over twisted-pair cables (see [0009], [0011], and [0016]); which are also addressed by the differential data pulses/signals show graphically in figure 3 on the two conductors 310+310’).
Where figure 3 provides a more detailed analysis of power and data commination between the devices; and figure 4 shows a chip/IC implementation of figure 3 ([0018]), further including transceiver implementation and various external pins, see [0018-0019]. Where the method steps are implemented as functions of the cited hardware of the Rajapaksha reference), the method (previously addressed) comprising (addressed below):
generating or receiving a common mode voltage via the differential pair (figs. 2-4: note that either device (sub-system A or sub-system B) is capable of generating/outputting or received common mode voltage (AC or DC) power signals (as depending upon the selected configuration) via the differential pair of conductors, being mapped to 220+220’ and/or 310+310’. With regards to figure 4, Pins A and B connect to the two conductors (e.g. A [Wingdings font/0xE0] 310 and B [Wingdings font/0xE0] 310’).
Where the power is generated at “Power Out” 231/316 (for figs. 2 & 3) output as a common mode voltage (e.g. in the case of DC power, then Voltage DC power signal (i.e. VDC) is applied) to the two conductors via inductors 233+233’ and/or 317+317’ (see [0011+0016]). Where the power signal (e.g. VDC) is received (or “delivered”) by inductors 213+213’ and/or 315+315’ and “Power In” unit 211/314 within the other device, see [0011+0016].
Note that VDC signal are shown to exist within both versions of waveform 307 (i.e. differential waveform 307) when traveling through the conductor pair 310+310’ (and/or 220+220’). Further note that the data portion of the composite waveforms 307 are differential (i.e. have equal but opposite amplitude) in the conductor pair.
The remaining limitations were previously addressed and/or are readily apparent);
transmitting a signal indicating a logical value via an output conductor (figs. 2-4: see at least figure 3+4, where receiver 320/420 outputs/transmits a single-end OOK data signal that indicates/represents a logical value (bit value 1 or 0) via the electrical output connection to envelope detector 322/422. Where the electrical output connection from the receiver 320/420 to envelope detector 322/422 is inherently ‘a conductor’ and logically meets the limitation “via an output conductor”); and
detecting a pair of pulses via the differential pair (figs. 2-4: see at least figure 3+4, where receiver 320/420 receives and detects the differential OOK pulse pairs (see top/bottom waveforms 307 having equal but opposite amplitudes of the pulses at the time). Where the top/positive/high differential pulses/signal were transmitted on conductor 310 and the bottom/negative/low differential pulses/signal were transmitted on conductor 310’); and
adjusting the signal indicating the logical value based on the pair of pulses (figs. 2-4: see at least figure 3+4, where envelope detector 322/422 receives and adjusts single-end OOK data signal (that indicates/represents logical values) into digital bit stream/signal 323/324, which is ‘based’ on the values of the previously addressed pairs of differential pulses).
With regards to claim 9, Rajapaksha as modified supra teaches the limitations of claim 8 above.
Rajapaksha as modified supra teaches wherein detecting the pair of pulses (previously addressed) includes detecting a high voltage differential compared to the common mode voltage (figs. 2-4: see top/high voltage differential 307 compared to the reference voltage of VDC as shown graphically in figure 3) and detecting a low voltage differential compared to the common mode voltage (figs. 2-4: see bottom/low voltage differential 307 compared to the reference voltage of VDC as shown graphically in figure 3) prior to detecting a return to the common mode voltage (figs. 2-4: where the first pulse pair of waveform 307. The top/high voltage signal is above the CM reference voltage (e.g. VDC) and the bottom/low voltage signal is below the CM reference voltage (e.g. VDC) before returning to the zero/reference/VDC value (as shown graphically in figure 3)).
With regards to claim 10, Rajapaksha as modified supra teaches the limitations of claim 9 above.
Rajapaksha as modified supra teaches wherein a difference between the high voltage differential and the common mode voltage matches a difference between the low voltage differential and the common mode voltage (figs. 2-4: see the differential pulses of waveform 307, where the difference between the ‘top/high voltage differential and the common mode voltage’ matches ‘the low voltage differential and the common mode voltage’ as shown figure 3. Furthermore, the Examiner notes that differential signal pulses by technical definition have the equal amplitude/magnitude but opposite phase/direction at any given particular time instant. In other words, the voltage/amplitudes of differential pulse pairs are vertically mirrored with respect to each other. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 11, Rajapaksha as modified supra teaches the limitations of claim 9 above.
Rajapaksha as modified supra teaches wherein an amount of time for which the high voltage differential is generated matches an amount of time for which the low voltage differential is generated (figs. 2-4: see the differential pulses of waveform 307, where the difference between the ‘top/high voltage differential and the common mode voltage’ matches ‘the low voltage differential and the common mode voltage’ as a functions of time, as shown figure 3. Furthermore, the Examiner notes that differential signal pulses by technical definition have the equal amplitude/magnitude but opposite phase/direction at any given particular time instant. In other words, the voltage/amplitudes of differential pulse pairs are vertically mirrored with respect to each other. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 13, Rajapaksha as modified supra teaches the limitations of claim 8 above.
Rajapaksha as modified supra teaches wherein an amount of time for which the pair of pulses is detected is less than a data rate of logical values transmitted via the output conductor (figs. 2-4: see the differential OOK pulses of waveform 307 of figure 3, where a single ‘logic 1’ is represented by multiple pulses (and pulse pairs) and logically meet the instant limitation(s) since the ‘amount of time’ required to detect each pulse pair (top/positive and bottom/negative) takes less time than the data/bit rate of the incoming data signal. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 14, Rajapaksha as modified supra teaches the limitations of claim 8 above.
Rajapaksha as modified supra teaches the method of claim 8 (previously addressed), further comprising receiving power via the differential pair (previously addressed, e.g. see the DC power signal VDC within waveform 307 of figure 3 and “Power In”. The remaining limitations were previously addressed and/or are readily apparent).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Rajapaksha et al. (US 2019/0386703: hereinafter “Rajapaksha”)
With regards to claim 1, Rajapaksha teaches a method of receiving power and transmitting data signals via a differential pair of conductors (see figs. 2-4: where figure 2 addresses that DC (or AC) power signals and RS485/RS422 data pulses/signals are concurrently communicated on the same pair of wires/conductors between two devices, also see [0013]. Which include transmitting data signals and receiving power (“Power In”) via a differential pair of conductors differential signals over twisted-pair cables (see [0009], [0011], and [0016]); which are also addressed by the differential data pulses/signals show graphically in figure 3 on the two conductors 310+310’.
Where figure 3 provides a more detailed analysis of power and data commination between the devices; and figure 4 shows a chip/IC implementation of figure 3 ([0018]), further including transceiver implementation and various external pins, see [0018-0019]. Where the method steps are implemented as functions of the cited hardware of the Rajapaksha reference), the method (previously addressed) comprising (addressed below):
generating or receiving a common mode voltage via the differential pair (figs. 2-4: note that either device (sub-system A or sub-system B) is capable of generating/outputting or received common mode voltage (AC or DC) power signals (as depending upon the selected configuration) via the differential pair of conductors, being mapped to 220+220’ and/or 310+310’. With regards to figure 4, Pins A and B connect to the two conductors (e.g. A [Wingdings font/0xE0] 310 and B [Wingdings font/0xE0] 310’).
Where the power is generated at “Power Out” 231/316 (for figs. 2 & 3) output as a common mode voltage (e.g. in the case of DC power, then Voltage DC power signal (i.e. VDC) is applied) to the two conductors via inductors 233+233’ and/or 317+317’ (see [0011+0016]). Where the power signal (e.g. VDC) is received (or “delivered”) by inductors 213+213’ and/or 315+315’ and “Power In” unit 211/314 within the other device, see [0011+0016].
Note that VDC signal are shown to exist within both versions of waveform 307 (i.e. differential waveform 307) when traveling through the conductor pair 310+310’ (and/or 220+220’). Further note that the data portion of the composite waveforms 307 are differential (i.e. have equal but opposite amplitude) in the conductor pair.
The remaining limitations were previously addressed and/or are readily apparent); and
in response to detecting an edge of an incoming digital signal via an input pin/port (figs. 2-4: where the raw data bits/signal 302/303 is input via data input port 402 of figure 4. Where Data In signal/waveform 303 is shown graphically shown to the be a digital waveform/signal). Furthermore, the transmitter inherently detects to edges of input raw data bits/signal 302/303 in order to perform the OOK data modulation 306/406 in order to generate OOK data modulated signal 305 as applicable to figures 3+4),
transmitting a pair of pulses (figs. 2-4: where the TX driver 308/408 converts the OOK modulated data signal 305 into a differential signal format (see top/bottom waveforms 307 having equal but opposite amplitudes for of the pulses). Where the top/positive/high differential pulses/signal is transmitted to conductor 310 and the bottom/negative/low differential pulses/signal is transmitted to conductor 310’) based on the edge (previously addressed and/or readily apparent) via the differential pair (previously addressed and/or readily apparent).
Limitation 1 (below):
Rajapaksha is silent to explicitly disclosing that the input data port/pin 402 (or the input data bits/signals 302/303) are connected to ‘an input conductor’.
With regards to the claim language, Rajapaksha is silent to explicitly disclosing “in response to detecting an edge of an incoming digital signal via an input conductor” (emphasis added).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the input data pin 402 of figure 4 (containing/conveying the input data bits/signals 302/303 of figure 3) of Rajapaksha would obviously be connected to as well as receive the ‘incoming digital signal via a separate/third input conductor’ which is further connected to another circuit (that generated the ‘incoming data bits/signal’) in order to actually function/operate in the real world.
With regards to claim 15, Rajapaksha teaches a communication device configured to receive power and communicate data signals via a differential pair of conductors (see the communication devices of figs. 2-4. Where figure 2 addresses that DC (or AC) power signals and RS485/RS422 data pulses/signals are concurrently communicated on the same pair of wires/conductors between two devices, also see [0013]. Which include transmitting data signals and receiving power (“Power In”) via a differential pair of conductors differential signals over twisted-pair cables (see [0009], [0011], and [0016]); which are also addressed by the differential data pulses/signals show graphically in figure 3 on the two conductors 310+310’.
Where figure 3 provides a more detailed analysis of power and data commination between the devices; and figure 4 shows a chip/IC implementation of figure 3 ([0018]), further including transceiver implementation and various external pins, see [0018-0019]. Where the method steps are implemented as functions of the cited hardware of the Rajapaksha reference), the communication device (previously addressed) comprising (addressed below):
circuitry (see the circuitry addressed below) configured to generate or receive a common mode voltage via the differential pair (figs. 2-4: note that either device (sub-system A or sub-system B) is capable of generating/outputting or received common mode voltage (AC or DC) power signals (as depending upon the selected configuration) via the differential pair of conductors, being mapped to 220+220’ and/or 310+310’. With regards to figure 4, Pins A and B connect to the two conductors (e.g. A [Wingdings font/0xE0] 310 and B [Wingdings font/0xE0] 310’).
Where the power is generated at “Power Out” 231/316 (for figs. 2 & 3) output as a common mode voltage (e.g. in the case of DC power, then Voltage DC power signal (i.e. VDC) is applied) to the two conductors via inductors 233+233’ and/or 317+317’ (see [0011+0016]). Where the power signal (e.g. VDC) is received (or “delivered”) by inductors 213+213’ and/or 315+315’ and “Power In” unit 211/314 within the other device, see [0011+0016].
Note that VDC signal are shown to exist within both versions of waveform 307 (i.e. differential waveform 307) when traveling through the conductor pair 310+310’ (and/or 220+220’). Further note that the data portion of the composite waveforms 307 are differential (i.e. have equal but opposite amplitude) in the conductor pair.
The remaining limitations were previously addressed and/or are readily apparent); and
at least one of (addressed below):
circuitry (see the circuitry addressed below) configured to,
in response to detecting an edge of an incoming digital signal via an input pin/port (figs. 2-4: where the raw data bits/signal 302/303 is input via data input port 402 of figure 4. Where Data In signal/waveform 303 is shown graphically shown to the be a digital waveform/signal). Furthermore, the transmitter inherently detects to edges of input raw data bits/signal 302/303 in order to perform the OOK data modulation 306/406 in order to generate OOK data modulated signal 305 as applicable to figures 3+4),
transmit an outgoing pair of pulses (figs. 2-4: where the TX driver 308/408 converts the OOK modulated data signal 305 into a differential signal format (see top/bottom waveforms 307 having equal but opposite amplitudes for of the pulses). Where the top/positive/high differential pulses/signal is transmitted to conductor 310 and the bottom/negative/low differential pulses/signal is transmitted to conductor 310’) based on the detected edge (previously addressed and/or readily apparent) via the differential pair (previously addressed and/or readily apparent); or
circuitry configured to detect an incoming pair of pulses via the differential pair and adjust a signal transmitted via an output conductor indicating a logical value based on the incoming pair of pulses (This limitation is NOT given patentable weight due to the “OR” statement).
Limitation 1 (below):
Rajapaksha is silent to explicitly disclosing that the input data port/pin 402 (or the input data bits/signals 302/303) are connected to ‘an input conductor’.
With regards to the claim language, Rajapaksha is silent to explicitly disclosing “in response to detecting an edge of an incoming digital signal via an input conductor” (emphasis added).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the input data pin 402 of figure 4 (containing/conveying the input data bits/signals 302/303 of figure 3) of Rajapaksha would obviously be connected to as well as receive the ‘incoming digital signal via a separate/third input conductor’ which is further connected to another circuit (that generated the ‘incoming data bits/signal’) in order to actually function/operate in the real world.
With regards to claims 2 and 16, Rajapaksha as modified supra teaches the limitations of claims 1 and 15 above.
Rajapaksha as modified supra teaches wherein transmitting the pair of pulses (previously addressed) includes generating a high voltage differential compared to the common mode voltage (figs. 2-4: see top/high voltage differential 307 compared to the reference voltage of VDC as shown graphically in figure 3) and generating a low voltage differential compared to the common mode voltage (figs. 2-4: see bottom/low voltage differential 307 compared to the reference voltage of VDC as shown graphically in figure 3) prior to returning to generating the common mode voltage (figs. 2-4: where the first pulse pair of waveform 307. The top/high voltage signal is above the CM reference voltage (e.g. VDC) and the bottom/low voltage signal is below the CM reference voltage (e.g. VDC) before returning to the zero/reference/VDC value (as shown graphically in figure 3)).
With regards to claim 3, Rajapaksha as modified supra teaches the limitations of claim 2 above.
Rajapaksha as modified supra teaches wherein a difference between the high voltage differential and the common mode voltage matches a difference between the low voltage differential and the common mode voltage (figs. 2-4: see the differential pulses of waveform 307, where the difference between the ‘top/high voltage differential and the common mode voltage’ matches ‘the low voltage differential and the common mode voltage’ as shown figure 3. Furthermore, the Examiner notes that differential signal pulses by technical definition have the equal amplitude/magnitude but opposite phase/direction at any given particular time instant. In other words, the voltage/amplitudes of differential pulse pairs are vertically mirrored with respect to each other. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 4, Rajapaksha as modified supra teaches the limitations of claim 2 above.
Rajapaksha as modified supra teaches wherein an amount of time for which the high voltage differential is generated matches an amount of time for which the low voltage differential is generated (figs. 2-4: see the differential pulses of waveform 307, where the difference between the ‘top/high voltage differential and the common mode voltage’ matches ‘the low voltage differential and the common mode voltage’ as a functions of time, as shown figure 3. Furthermore, the Examiner notes that differential signal pulses by technical definition have the equal amplitude/magnitude but opposite phase/direction at any given particular time instant. In other words, the voltage/amplitudes of differential pulse pairs are vertically mirrored with respect to each other. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 6, Rajapaksha as modified supra teaches the limitations of claim 1 above.
Rajapaksha as modified supra teaches wherein an amount of time for generating the outgoing pair of pulses is less than a data rate of the incoming digital signal (figs. 2-4: see the differential OOK pulses of waveform 307 of figure 3, where a single ‘logic 1’ is represented by multiple pulses (and pulse pairs) and logically meet the instant limitation(s) since the ‘amount of time’ required to generate each pulse pair (top/positive and bottom/negative) takes less time than the data/bit rate of the incoming data signal. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 7, Rajapaksha as modified supra teaches the limitations of claim 1 above.
Rajapaksha as modified supra teaches the method of claim 1 (previously addressed), further comprising receiving power via the differential pair (previously addressed, e.g. see the DC power signal VDC within waveform 307 of figure 3. The remaining limitations were previously addressed and/or are readily apparent).
With regards to claim 17, Rajapaksha as modified supra teaches the limitations of claim 15 above.
Rajapaksha as modified supra teaches wherein detecting the incoming pair of pulses includes detecting a high voltage differential compared to the common mode voltage and detecting a low voltage differential compared to the common mode voltage prior to detecting a return to the common mode voltage (This limitation is NOT given patentable weight due to the “OR” statement in parent claim 15. In other words, the limitation is directed to the unselected option of the “OR” statement in parent claim 15, and thus limitation is met due to the merits of the rejection of claim 15 supra).
With regards to claim 18, Rajapaksha as modified supra teaches the limitations of claim 15 above.
Rajapaksha as modified supra teaches the communication device of claim 15 (previously addressed), further comprising circuitry configured to receive power via the differential pair (previously addressed, e.g. “Power In” and VDC within waveform 307).
With regards to claim 19, Rajapaksha as modified supra teaches the limitations of claim 15 above.
Rajapaksha as modified supra teaches the communication device of claim 18 (previously addressed), further comprising circuitry configured to separate the power from the incoming pair of pulses or outgoing pair of pulses (figs. 2-4: see figure 3, where the capacitors 312+312’ and 313+313’ as well as inductors 315+315+ and 317+317’ perform the claimed separate functionality of separating/combining common mode power signal VDC from the differential OOK pulse pairs).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Rajapaksha et al. (US 2019/0386703: hereinafter “Rajapaksha”) as applied to claim 18 above, and further in view of Peker et al. (USPN 9,571,669: hereinafter “Peker”).
With regards to claim 20, Rajapaksha as modified supra teaches the limitations of claim 18 above.
Rajapaksha as modified supra teaches the communication device of claim 18 (previously addressed), further comprising circuitry configured to separate the power from pair of pulses (figs. 2-4: see figure 3, where the capacitors 312+312’ and 313+313’ as well as inductors 315+315+ and 317+317’ perform the claimed separate functionality of separating/combining common mode power signal VDC from the differential OOK pulse pairs, in regards to the “Power In” unit 211/314 for electrical ‘power delivery’).
Limitation A (below):
However, Rajapaksha as modified supra teaches is silent to explicitly disclosing “wherein the circuitry configured to receive power via the differential pair includes rectifier circuitry” (emphasis added).
However, secondary reference Peker discloses a similar communication system for providing both data communication and electrical power transfer on the same twisted-pair copper wiring connecting at least two different devices (see col. 1, line 5 through col. 2, line 13).
Furthermore, col. 9, line 65 through col. 10, line 4 states “a classification circuit is further supplied (not shown) which provides the PSE of the respective CPE 40 or 45 with the respective power drawing information of the power transfer circuit 110. The DC power is received at diode bridge 140, which rectifies the input DC power, thus ensuring polarity neutrality” (Emphasis added).
Therefore, in view of the cited teachings of Peker, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously addressed “Power In” unit (or circuitry nested/connected to the “Power In” unit) of the Rajapaksha reference to include ‘rectifier circuity’ (like the diode bridge) to rectify a received power signal as stated by Peker (previously addressed) in order to yield the corresponding disclosed benefits such as ‘ensuring polarity neutrality’ (as stated in Peker, col. 9, line 65 through col. 10, line 4).
Allowable Subject Matter
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, including teaching reference Rumbaugh (USPN 6,275,144), which defines the meaning of digital signals being defined by strings of bits (binary 1s and 0s) as well as the definition of On-Off Keying (OOK) modulation as addressed in figure 1 and col. 1, lines 16-27; where col. 1, lines 16-27 states:
“Referring to FIG. 1, data 10 includes information that may be transmitted over the power line using one of the illustrated transmission techniques. Data 10 is represented by digital signals that are transmitted in strings of binary 1s and 0s. When amplitude modulation technique 20 is used to transmit data 10, the data signal is blended into a carrier by varying the amplitude of the carrier. Specifically, the amplitude is modulated when it corresponds to a binary 0 of the data signal. On-off modulation technique 30 uses a transmitter which is turned off every time the transmitted data signal is represented by a binary 0” (Emphasis added).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James M. Perez, telephone number (571)270-3231. The examiner can normally be reached Monday through Friday: 10am to 6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David C. Payne can be reached at (571)272-3024. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES M PEREZ/Primary Examiner, Art Unit 2635 1/31/2026