DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amended claims 1-20 as submitted on 12/29/25 were examined.
Response to Amendment
Applicant’s amendments submitted on 12/29/25 were fully considered. Any new rejections made below were in response to the amendment.
Applicant states that claim 16 was amended to address the rejection of the claim under 35 USC 112 as being indefinite. However, there does not appear to be any amendment to claim 16 which addresses the indefiniteness rejection, thus the rejection is repeated below for record. It is assumed that applicant accidentally forgot to amend claim 16.
Response to Arguments
Applicant’s arguments submitted on 12/29/25 were considered but are not persuasive.
Applicant argues that the verification using checksum as taught by Chu is not the same as the firmware resiliency management operation as disclosed and claimed. Applicant’s argument does not appear to comply with 37 CFR 1.111(b) because the argument appears to merely be allegations that there is a difference between the cited reference and what is claimed without any explanation as how the two differ. As explained on p4, section c of the rejection of claim 1 in the last Office action, firmware verification using checksum is a type of resiliency management operation since the checksum passing verification or not determines the integrity of the firmware.
Applicant argues that the BIOS disclosed by Chu is not a distributed BIOS. The examiner respectfully disagrees. Cited paragraph 17 shows that the BIOS disclosed by Chu are divided into multiple firmware which are stored in multiple places in BIOS memory 110. In this manner, the BIOS can be considered “distributed”. Additionally, paragraph 13 of Chu discloses that BIOS memory 110 can be a combination of several types of storage. Since the BIOS (and the firmware which makes up what is considered BIOS) is stored a combination of storage (i.e. DRAM, SRAM, NAND flash memory, NOR flash memory, etc.), in this manner, the BIOS is also considered “distributed” among different types of storage.
Applicant argues that Chu does not teach “a distributed BIOS, the distributed BIOS including a plurality of components and a plurality of BIOS variables, the distributed BIOS being implemented to function with any of a plurality of processor environments, each of the plurality of processing environments implementing a respective processor architecture” as required in amendment claims 1, 7, and 13.
The examiner respectfully disagrees. First, it is noted that claims 1, 7, and 13 do not actually recite this limitation that applicant is arguing. Nonetheless, for the sake of compact prosecution (in case applicant intends to amend the claims to align more closely with this argued limitation later), the examiner will address the argument as presented since Chu discloses the argued limitation.
Chu disclosing the BIOS being distributed BIOS is already addressed above. Further, in paragraphs 17-18 of Chu, it is disclosed that multiple firmware which makes up the distributed BIOS are stored in BIOS memory 110. Chu discloses that the distributed BIOS (i.e. multiple firmware stored in multiple storage locations, i.e. as per paragraph 13) can be used with multiple processor families. Each processor family, as understood in the art, is a different processor environment having their own processor architecture.
For example, ARM family and x86 family are two different families of processors and each are based different architectures and environments. As disclosed in paragraphs 17-18, the BIOS will use a boot path that corresponds to the CPU installed in the computer system. The particular boot path and firmware(s) selected for each processor detected can be considered different BIOS variables. Whatever variables used in the programming of the different firmware selected for each type of processor family can also be considered a plurality of BIOS variables. One skilled should appreciate that each firmware must use different variables since each firmware is meant to work with different processor families. At the very least, each firmware must define different expected boot paths for each processor family, and each boot path for each processor family can be considered different BIOS variables. As such, the argued limitation is met by Chu.
Note also that Chu also discloses the newly added limitations as recited in claims 1, 7, and 13, see art rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites “the unified BIOS memory map” in line 3, which lacks antecedent basis.
Claims not specifically addressed are rejected due to dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-8, and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chu (US 2022/0197746).
Claims 1, 7, and 13:
As per claim 7, Chu discloses:
a processor; a data bus coupled to the processor (paragraph 16 and Fig 1; All computers have these limitations); and
a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor (paragraphs 33 and 36) and configured for:
providing an information handling system with a distributed BIOS (paragraphs 13 and 17; BIOS memory 110, which stores the BIOS, is implemented as a combination of storage locations, i.e. DRAM, SRAM, NAND flash memory, NOR flash memory FeRAM, etc. The BIOS itself is comprised of multiple firmware stored in BIOS memory 110. As such the BIOS is distributed across multiple firmware and across multiple storage locations, which makes the BIOS “distributed BIOS” twice over), the distributed BIOS being implemented to function with any of a plurality of processor environments (paragraphs 17-18; The same group of firmware which makes up the distributed BIOS can function with a number of processor families. Depending on the processor family, only certain firmware portions which make up the BIOS are utilized. Each processor family inherently provides for a different processor environment. This can be seen in that different firmware are chosen for use with each processor family and different boot paths), each of the plurality of processing environments implementing a respective processor architecture (paragraphs 17-18; By definition and as understood in the art, a processor family implements a different processor architecture. For example, ARM family processors and x86 family processors have different architectures);
identifying a processor environment installed on an information handling system from the plurality of processor environments (paragraphs 17, 20, and 28; See especially paragraph 28 which discusses identifying an installed CPU and selecting a firmware that corresponds to the identified CPU as well as the boot path corresponding to the processor environment);
performing a firmware resiliency management operation, the firmware resiliency management operation resiliently maintaining integrity of firmware code associated with the processor architecture of the processor environment installed on the information handling system, the firmware code including the distributed BIOS (paragraphs 13, 17-18 and 21; The verification of the firmware performed in this paragraph is considered firmware resiliency management operation as the verification process uses a checksum calculation or other mechanism to ensure the integrity of the firmware).
The rejection of claim 7 applies, mutatis mutandis, to claims 1 and 13.
Claims 2, 8, and 14:
Chu further discloses wherein:
the processor environment installed on the information handling system includes a plurality of processor cores (paragraphs 11, 17, 20, 28, and Fig1, CPU cores(s) 104); and,
the firmware resiliency management operation resiliently maintaining integrity of firmware code associated with each of the plurality of processor cores (paragraph 21 and 28; Checksum verification of firmware for CPUs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 9-10, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Smith, II et al (US 2018/004953).
Claims 3, 9, and 15:
Chu does not teach, but Smith teaches the information handling system includes an embedded controller, the embedded controller being implemented to enable a BIOS root of trust (paragraphs 33, 39, and 41).
Before the effective filing date of applicant’s claimed invention, it would have been obvious to one of ordinary skill in the art to modify Chu’s invention in accordance with Smith’s teachings. One of ordinary skill in the art would have been motivated to do so as it would provide for a secure audit trail about the firmware (Smith: paragraph 42).
Claims 4 and 10:
Smith further discloses wherein:
the information handling system includes a platform controller hub (paragraph 37); and,
the BIOS root of trust is implemented to provide resiliency information to the platform controller hub (paragraphs 33, 35, 37, 39, and 41).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Chang et al (US 2014/0006763) in further view of.
Claim 11:
Chu does not explicitly disclose wherein: the resiliency information is implemented as a plurality of signed configuration vectors, each of the plurality of signed configuration vectors corresponding to a particular processor core of the processor environment installed on the information handling system.
However, Chang discloses wherein: the resiliency information is implemented as a plurality of configuration vectors, each of the plurality of configuration vectors corresponding to a particular processor core of the processor environment installed on the information handling system (paragraphs 15 and 20-21). The configuration vectors taught by Chang is used to deliver firmware and Smith teaches signed firmware (paragraph 33). Based on these combined teachings by Chang and Smith, before the effective filing date of applicant’s claimed invention, it would have been obvious to one of ordinary skill in the art to modify Chu’s invention in so that the resiliency information is implemented as a plurality of signed configuration vectors, each of the plurality of signed configuration vectors corresponding to a particular processor core of the processor environment installed on the information handling system.
The rationale for why it would have been obvious to incorporate Chang’s teachings is that doing so is nothing more than simple substitution of one known element (i.e. firmware delivery mechanism) for another (i.e. use of configuration vectors for delivery) to achieve predictable results, see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007). One of ordinary skill in the art would have found it obvious to incorporate Smith’s teachings because as it would provide for a secure audit trail about the firmware (Smith: paragraph 42).
Claim 12:
Chang further discloses wherein: each of the plurality of signed configuration vectors is stored within a respective plurality of registers within the platform controller hub (paragraphs 21 and 29).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Smith, II et al (US 2018/004953) in further view of Chang et al (US 2014/0006763).
Claim 5:
Claim 5 recites a further limitation similar to what is recited in claim 11 and is rejected over the combined teachings of Chu, Smith, and Chang as set forth in the rejection of claim 11 as seen above.
Claim 6:
Chang further discloses wherein: each of the plurality of signed configuration vectors is stored within a respective plurality of registers within the platform controller hub (paragraphs 21 and 29).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Smith, II et al (US 2018/004953) in further view of Montero et al (US 2020/0201714).
Claim 16:
Chu does not disclose, but Montero discloses wherein: the unified BIOS memory map includes a firmware (FW) equivalent interrupt (IRQ) mapping table (paragraph 3; The limitation describes a feature of UEFI).
Before the effective filing date of applicant’s claimed invention, it would have been obvious to one of ordinary skill in the art to further modify Chu’s invention in accordance with the limitation further recited in claim 16. One of ordinary skill in the art would have found it obvious to do so because UEFI is a standard and standards are meant to be used.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Smith, II et al (US 2018/004953) in further view of Montero et al (US 2020/0201714) in further view of Chang et al (US 2014/0006763).
Claim 17:
Claim 17 recites a further limitation similar to what is recited in claim 11 and is rejected over the combined teachings of Chu, Smith, and Chang as substantially set forth in the rejection of claim 11 as seen above.
Claim 18:
Chang further discloses wherein: each of the plurality of signed configuration vectors is stored within a respective plurality of registers within the platform controller hub (paragraphs 21 and 29).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746) in view of Jaber et al (US 2013/0185564).
Claim 19:
Chu does not explicitly disclose, but Jaber discloses wherein: the computer executable instructions are deployable to a client system from a server system at a remote location (paragraph 16).
Before the effective filing date of applicant’s claimed invention, it would have been obvious to one of ordinary skill in the art to modify Chu’s invention such that the computer executable instructions are deployable to a client system from a server system at a remote location. The rationale for why it is obvious is that doing so is nothing more than simple substitution of one known element for another to achieve predictable results, see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007). In this case one merely substitutes a generic source of the firmware/BIOS for a server as the source location that the firmware/BIOS is obtained from.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chu (US 2022/0197746).
Claim 20:
Chu discloses wherein: the computer executable instructions are provided by a service provider to a user (paragraphs 14 and 20; BIOS update tool obtains firmware/BIOS).
Chu does not explicitly disclose the instructions are provided on an on-demand basis. However, official notice is taken that before the effective filing date of applicant’s claimed invention, on-demand delivery of computer executable instructions to a user was well-known in the art. Thus, it would have been obvious to modify Chu’s invention so that the computer executable instructions are provided on an on-demand basis. One of ordinary skill in the art would have been motivated to do so as it would allow the user to choose when updates to firmware/BIOS are to occur.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PONNOREAY PICH/Primary Examiner, Art Unit 2495
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