Details Action
Claims 1-27 are pending.
Claims 1-2, 5-7, 10-12, 16-17 and 21-27 are rejected.
Claims 3-4, 8-9, 13-15 and 18-20 are objected to.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 5-7, 10-12, 16-17 and 21-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a mental process grouping of abstract ideas without significantly more. Claim 1 recites recording a value representing a time duration for a frame on a PHY datapath to travel between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-cable interface; and asserting an indication that the recorded value is available to be read from a PHY. Recording a value and asserting an indication is a process that, under its broadest reasonable interpretation, covers performance of the limitations in the mind. The claim does not recite any additional limitations of the judicial exceptions enumerated in the 2019 PEG.
This judicial exception is not integrated into a practical application because the claim is directed to the abstract idea with no additional elements that integrate the judicial exception into a practical application. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the claims merely recite recoding and asserting.Claim 2 adds some details to the time duration that is recorded and thus the limitation is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.Similarly claim 5 adds the limitation enabling provision of a value which is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.
Similarly claim 6 adds the limitation reading the value and changing a value of a timestamp from a first value to a second value which is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.
Claim 7 adds some details to the time duration that is recorded and thus the limitation is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.Claim 10 adds the limitation reading the value and changing a value of a timestamp from a first value to a second value which is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.
Claim 11 is an apparatus claim corresponding to claim 1 and adds the limitations a memory and a logic circuit to perform the recording and asserting. The memory and the logic circuit are recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data (the amount of use of each icon, or the ranking of the icons based on the determined amount of use). This generic processor limitation is no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application.
Claim 12 adds some details to the time duration that is recorded and thus the limitation is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.Claims 16 adds the limitation enabling provision of a value which is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind. Similarly, the logic circuit comprising a gating circuit, performing the enabling, is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data (the amount of use of each icon, or the ranking of the icons based on the determined amount of use). This generic processor limitation is no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical.
Claim 17 adds some details to the time duration that is recorded and thus the limitation is still, under its broadest reasonable interpretation, covers performance of the limitations in the mind.Claim 21 is a system claim corresponding to claim 1 and adds the limitation a physical layer to perform the recording and asserting and a media access controller to read and change the value. The physical layer and the media access controller are recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data (the amount of use of each icon, or the ranking of the icons based on the determined amount of use). This generic processor limitation is no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical.
Claims 22-27 does not add any significantly more elements to the abstract idea to integrate the abstract idea into a practical application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harriman et al (Pub. No.: US 2015/0117504 A1).
As per claim 1, Harriman discloses a method comprising: - recording a value representing a time duration for a frame on a PHY datapath to travel between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-cable interface (Harriman, paragraph 0097-0098, wherein “an apparatus comprises: timing logic to associate a first value with a unit of data upon entry into a path of a physical layer coupled to a serial interconnect; and latency logic to associate a second value upon an exit from the path of the physical layer and to determine a latency associated with the path of the physical layer based on the first and second values.In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”); and - asserting an indication that the recorded value is available to be read from a PHY (Harriman, paragraph 0098-0099, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value.In an example, the resolution logic is to output, to a MAC unit, a time value corresponding to the latency and a valid signal to indicate that the time value is valid. The apparatus may comprise a precise time measurement circuit, and a latency of the precise time measurement circuit is locked to a latency of traversal of a symbol from an interconnect interface of the physical layer to a MAC interface”);
As per claim 2, claim 1 is incorporated and Harriman further discloses wherein the time duration for the frame to travel between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-cable interface comprises: a time duration for the frame to travel from the predetermined reference plane of the PHY-MAC interface to the predetermined reference plane of the PHY-cable interface (Harriman, paragraph 0097-0098, wherein “an apparatus comprises: timing logic to associate a first value with a unit of data upon entry into a path of a physical layer coupled to a serial interconnect; and latency logic to associate a second value upon an exit from the path of the physical layer and to determine a latency associated with the path of the physical layer based on the first and second values.In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”);
As per claim 3, claim 2 is incorporated and Harriman further discloses starting counting clock cycles at least partially responsive to an asserted indication of presence of the frame at the predetermined reference plane of the PHY-MAC interface (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”); stopping counting clock cycles at least partially responsive to an asserted indication of presence of the frame at the predetermined reference plane of the PHY-cable interface (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”); and setting the value to a counted number of clock cycles (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”);
As per claim 7, claim 1 is incorporated and Harriman further discloses wherein the time duration for the frame to travel between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-cable interface comprises: a time duration for the frame to travel from the predetermined reference plane of the PHY-cable interface to the predetermined reference plane of the PHY-MAC interface (Harriman, paragraph 0097-0098, wherein “an apparatus comprises: timing logic to associate a first value with a unit of data upon entry into a path of a physical layer coupled to a serial interconnect; and latency logic to associate a second value upon an exit from the path of the physical layer and to determine a latency associated with the path of the physical layer based on the first and second values.In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”);
As per claim 8, claim 7 is incorporated and Harriman further discloses starting counting clock cycles at least partially responsive to an asserted indication of presence of the frame at the predetermined reference plane of the PHY-cable interface (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”); stopping counting clock cycles at least partially responsive to an asserted indication of presence of the frame at the predetermined reference plane of the PHY-MAC interface (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”); and setting the value to a counted number of clock cycles (Harriman, paragraph 0097-0098, wherein “In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”);
Claims 11-13 and 17-18 are rejected under the same rationale as claims 1-3 and 7-8.
As per claim 27, claim 1 is incorporated and Harriman further discloses wherein one or more of the predetermined reference plane of the PHY-MAC interface or the predetermined reference plane of the PHY- cable interface are defined at respective internal sublayer boundaries of the PHY (Harriman, paragraph 0097-0098, wherein “an apparatus comprises: timing logic to associate a first value with a unit of data upon entry into a path of a physical layer coupled to a serial interconnect; and latency logic to associate a second value upon an exit from the path of the physical layer and to determine a latency associated with the path of the physical layer based on the first and second values.In an example, the apparatus further includes: a counter to count between a start value and an end value according to a local clock signal, the timing logic comprising the counter; a first register to store an output of the counter, where the first register is to be sampled according to a recovered clock signal; a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of the physical layer; and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine the latency for the data unit to traverse the physical layer based at least in part on the counter output sample and the current counter value”);
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Harriman et al (Pub. No.: US 2015/0117504 A1) in view of HE et al (Pub. No.: US 2020/0412469 A1).
As per claim 23, claim 21 is incorporated and Harriman does not explicitly disclose wherein the media access controller to implement a precision time protocol, and the frame is one of a SYNCHRONIZATION frame or a DELAY_REQUEST frame. However, using a precision time protocol and having a SYNCHRONIZATION frame or a DELAY_REQUEST frame is well known in the art. For example, HE discloses wherein the media access controller to implement a precision time protocol, and the frame is one of a SYNCHRONIZATION frame or a DELAY_REQUEST frame (HE, paragraph 0006, 0032-0033, wherein the IEEE 1588 protocol for Ethernet is mainly implemented by identifying a synchronization frame header at a Media Access Control (MAC) layer and recording timestamp information. The Precision Time Protocol (PTP), such as the 1588 Protocol, is usually used to synchronize a master clock and a slave clock in a distributed system. Accordingly, the time information messages used are generally 1588 event messages. In a synchronization process of a system, a master clock periodically publishes PTP time synchronization and time information, a slave clock port receives timestamp information sent from a master clock port, and the system calculates master-slave line delay and master-slave time difference according to the timestamp information, and adjusts local time by using the time difference).
Therefore, it would have it would have been obvious to one ordinary skill in the art before the effective filing date of the invention to incorporate HE teachings into Harriman to achieve the claimed limitations because this would have provided a way to improve time accuracy which leads to precise master-slave synchronization and thus better performance and efficiency.
As per claim 24, claim 21 is incorporated and Harriman does not explicitly disclose wherein the media access controller and the physical layer are provided at a device that includes a mater clock of a precision time protocol synchronization process. However, HE discloses wherein the media access controller and the physical layer are provided at a device that includes a mater clock of a precision time protocol synchronization process (HE, paragraph 0006, 0032-0033, wherein the IEEE 1588 protocol for Ethernet is mainly implemented by identifying a synchronization frame header at a Media Access Control (MAC) layer and recording timestamp information. The Precision Time Protocol (PTP), such as the 1588 Protocol, is usually used to synchronize a master clock and a slave clock in a distributed system. Accordingly, the time information messages used are generally 1588 event messages. In a synchronization process of a system, a master clock periodically publishes PTP time synchronization and time information, a slave clock port receives timestamp information sent from a master clock port, and the system calculates master-slave line delay and master-slave time difference according to the timestamp information, and adjusts local time by using the time difference).
Therefore, it would have it would have been obvious to one ordinary skill in the art before the effective filing date of the invention to incorporate HE teachings into Harriman to achieve the claimed limitations because this would have provided a way to improve time accuracy which leads to precise master-slave synchronization and thus better performance and efficiency.
As per claim 25, claim 21 is incorporated and Harriman does not explicitly disclose wherein the media access controller and the PHY-cable interface are provided at a device that includes a slave clock of a 1588 precision time protocol synchronization process. However, HE discloses wherein the media access controller and the PHY-cable interface are provided at a device that includes a slave clock of a 1588 precision time protocol synchronization process (HE, paragraph 0006, 0032-0033, wherein the IEEE 1588 protocol for Ethernet is mainly implemented by identifying a synchronization frame header at a Media Access Control (MAC) layer and recording timestamp information. The Precision Time Protocol (PTP), such as the 1588 Protocol, is usually used to synchronize a master clock and a slave clock in a distributed system. Accordingly, the time information messages used are generally 1588 event messages. In a synchronization process of a system, a master clock periodically publishes PTP time synchronization and time information, a slave clock port receives timestamp information sent from a master clock port, and the system calculates master-slave line delay and master-slave time difference according to the timestamp information, and adjusts local time by using the time difference).
Therefore, it would have it would have been obvious to one ordinary skill in the art before the effective filing date of the invention to incorporate HE teachings into Harriman to achieve the claimed limitations because this would have provided a way to improve time accuracy which leads to precise master-slave synchronization and thus better performance and efficiency.
As per claim 26, claim 21 is incorporated and Harriman does not explicitly disclose wherein the media access controller and the physical layer are provided at a device that includes a clock of a precision time protocol synchronization process. However, HE discloses wherein the media access controller and the physical layer are provided at a device that includes a clock of a precision time protocol synchronization process (HE, paragraph 0006, 0032-0033, wherein the IEEE 1588 protocol for Ethernet is mainly implemented by identifying a synchronization frame header at a Media Access Control (MAC) layer and recording timestamp information. The Precision Time Protocol (PTP), such as the 1588 Protocol, is usually used to synchronize a master clock and a slave clock in a distributed system. Accordingly, the time information messages used are generally 1588 event messages. In a synchronization process of a system, a master clock periodically publishes PTP time synchronization and time information, a slave clock port receives timestamp information sent from a master clock port, and the system calculates master-slave line delay and master-slave time difference according to the timestamp information, and adjusts local time by using the time difference).
Therefore, it would have it would have been obvious to one ordinary skill in the art before the effective filing date of the invention to incorporate HE teachings into Harriman to achieve the claimed limitations because this would have provided a way to improve time accuracy which leads to precise master-slave synchronization and thus better performance and efficiency.
Allowable Subject Matter
Claims 4, 9, 14-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMZA N ALGIBHAH whose telephone number is (571)270-7212. The examiner can normally be reached 7:30 am - 3:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wing Chan can be reached on (571) 272-7493. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAMZA N ALGIBHAH/Primary Examiner, Art Unit 2441