Non-Final
This office action is in response to Election/Restriction filed 3/30/26.
The Examiner acknowledged (Group 1 – Claims 1-10 and 16-20) has been elected and has been examined in this office action.
35 USC 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 USC 103 as being unpatentable over (VANAPARTHY – CN 2018/10995459) in view of Kong et al. (US Pub. No. 2009/0241009).
With respect to claim 1, the VANAPARTHY reference teaches a first memory device (page 9, lines 40-45 – processor may include one or more processor cores and may be configured to execute system software. The system software may include, for example, an operating system. The device memory may include an I/O memory buffer configured to store one or more data packets to be sent or received by the network interface); a second memory device (page 9, lines 40-45 – processor may include one or more processor cores and may be configured to execute system software. The system software may include, for example, an operating system. The device memory may include an I/O memory buffer configured to store one or more data packets to be sent or received by the network interface); and a control logic circuit configured to control the first memory device and the second memory device (column 5, lines 45-48 – memory controller control circuit 110 is configured to receive, for example, data to be written from the processor circuit 102 to the memory device 106), wherein the control logic circuit includes an error correction circuit configured to generate, based on puncturing option information, a first error correction code of a first size, and a second error correction code of a second size (column 5, lines 27-40 – LDPC codeword having information of size 4256 (N-k) bits and parity of 800 (k) bits has a block length (N) of 5056 bits. In a memory device (e.g., memory device 106), a plurality of codewords may be interspersed across a plurality of dies), wherein the second size is larger than the first size codeword (column 5, lines 27-40 – LDPC codeword having information of size 4256 (N-k) bits and parity of 800 (k) bits has a block length (N) of 5056 bits. In a memory device (e.g., memory device 106), a plurality of codewords may be interspersed across a plurality of dies).
The VANAPARTHY reference does not teach and wherein the control logic circuit is configured to store the first error correction code in the first memory device during a first write operation, and store the second error correction code in the second memory device during a second write operation..
The Kong et al. reference teaches and wherein the control logic circuit is configured to store the first error correction code in the first memory device during a first write operation ([0077] - The first decoding module 210 may perform ECC decoding with respect to a first codeword 213. The first codeword 213 may include a first message m1 211 and a first parity p1 212, which may be read from the memory cell array 110. The first decoding module 210 may generate a first message m1 (1) 214, which may be estimated by performing ECC decoding with respect to the first codeword 213), and store the second error correction code in the second memory device during a second write operation ([0078] - The second decoding module 220 may perform ECC decoding with respect to a second codeword 223. The second codeword 223 may include the estimated first message m1(1) 214, a second message m2 221, and a second parity p12 222, which may be read from the memory cell array 110. The second decoding module 220 may generate an estimated second message m2(1) 226 and a re-estimated first message m1(2) 225, which are estimated by performing ECC decoding with respect to the second codeword 223).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references VANAPARTHY and Kong et al. to incorporate the limitations and wherein the control logic circuit is configured to store the first error correction code in the first memory device during a first write operation, and store the second error correction code in the second memory device during a second write operation. into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the VANAPARTHY and Kong et al. references for performance ([0009] - Kong et al).
With respect to claim 2, the VANAPARTHY reference teaches wherein the first memory device is configured to apply a punctured error correction code, and the second memory device is configured to apply an original error correction code (page 6, lines 39-48 – presence or absence of puncturing may be known prior to, and the presence or absence of erasure may be determined in operation by, for example, error correction circuit 112).
With respect to claim 3, the VANAPARTHY reference teaches wherein the first memory device is a volatile memory device, and wherein the second memory device is a non-volatile memory device (page 10, lines 6-10 – The SDC mitigating memory 124 may include one or more of the following types of memory: Semiconductor firmware memory, programmable memory, non-volatile memory, read-only memory, electrically programmable memory, random access memory, flash memory, disk memory and/or optical disk memory).
With respect to claim 4, the VANAPARTHY reference teaches wherein the control logic circuit is configured to variably set the first size based on an error rate of data stored in the first memory device (page 6, lines 24-31 – the threshold determination logic 126 may be configured to retrieve the RBER and the UBER from the SDC mitigating memory 124. The threshold determination logic 126 may then be configured to identify the ECC and the corresponding codeword size N implemented by the error correction circuit 112).
With respect to claim 5, the VANAPARTHY reference teaches wherein the puncturing option information is set in a register during an initialization operation (page 5, lines 21-27 – The SDC mitigating memory 124 is configured to store one or more SDC mitigating parameters. The SDC mitigation parameter 125 may include, but is not limited to, RBER, UBER, maximum variation of UBER (i.e., maximum allowable increment) (AUBER), ECC identifier, puncturing information, and/or erasure information).
With respect to claim 6, the VANAPARTHY reference teaches wherein the error correction circuit is configured to change the puncturing option information in real-time (column 5, lines 36-44 – The nominal threshold may be adjusted based at least in part on an amount of whether a stored codeword may be punctured and/or erased).
With respect to claim 7, the VANAPARTHY reference teaches wherein the error correction circuit is configured to vary the puncturing option information based on an error rate of read data (column 5, lines 36-40 – If there is a puncturing and/or erasure, the valid codeword size may be updated at operation 218).
With respect to claim 8, the VANAPARTHY reference teaches wherein the error correction circuit is configured to vary the puncturing option information an error rate range (column 5, lines 36-40 – If there is a puncturing and/or erasure, the valid codeword size may be updated at operation 218).
With respect to claim 9, the VANAPARTHY reference teaches wherein the error correction circuit is configured to change settings of an encoder/decoder based on the puncturing option information (page 6, lines 39-48 – For example, when a threshold is determined, the number of valid bits in the codeword may be used for N (i.e., the number of bits in the codeword minus the number of punched bits and/or erased bits). Therefore, the thresholds can be updated to accommodate puncturing and/or erasure. The decision of whether to accept or reject a successful decoded codeword may then be performed based on the valid bits).
With respect to claim 10, the VANAPARTHY reference teaches wherein the error correction circuit is configured to change at least one of a type of error correction code or an H matrix based on the puncturing option information (page 6, lines 39-48 – presence or absence of puncturing may be known prior to, and the presence or absence of erasure may be determined in operation by, for example, error correction circuit 112).
With respect to claim 16, the VANAPARTHY reference teaches receiving write data receiving write data (column 5, lines 45-48 – memory controller control circuit 110 is configured to receive, for example, data to be written from the processor circuit 102 to the memory device 106); setting an error correction code level based on puncturing option information (column 5, lines 27-40 – LDPC codeword having information of size 4256 (N-k) bits and parity of 800 (k) bits has a block length (N) of 5056 bits. In a memory device (e.g., memory device 106), a plurality of codewords may be interspersed across a plurality of dies).
The VANAPARTHY reference does not teach generating an error correction code for the write data based on the error correction code level; and storing the write data and the error correction code in a first memory device corresponding to the error correction code level..
The Kong et al. reference teaches generating an error correction code for the write data based on the error correction code level ([0077] - The first decoding module 210 may perform ECC decoding with respect to a first codeword 213. The first codeword 213 may include a first message m1 211 and a first parity p1 212, which may be read from the memory cell array 110. The first decoding module 210 may generate a first message m1 (1) 214, which may be estimated by performing ECC decoding with respect to the first codeword 213); and storing the write data and the error correction code in a first memory device corresponding to the error correction code level ([0077] - The first decoding module 210 may perform ECC decoding with respect to a first codeword 213. The first codeword 213 may include a first message m1 211 and a first parity p1 212, which may be read from the memory cell array 110. The first decoding module 210 may generate a first message m1 (1) 214, which may be estimated by performing ECC decoding with respect to the first codeword 213).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references VANAPARTHY and Kong et al. to incorporate the limitations generating an error correction code for the write data based on the error correction code level; and storing the write data and the error correction code in a first memory device corresponding to the error correction code level into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the VANAPARTHY and Kong et al. references for performance ([0009] - Kong et al).
With respect to claim 17, the VANAPARTHY reference teaches setting the puncturing option information in a register in an initialization operation (page 5, lines 21-27 – The SDC mitigating memory 124 is configured to store one or more SDC mitigating parameters. The SDC mitigation parameter 125 may include, but is not limited to, RBER, UBER, maximum variation of UBER (i.e., maximum allowable increment) (AUBER), ECC identifier, puncturing information, and/or erasure information).
With respect to claim 18, the VANAPARTHY reference teaches tracking an error rate on data read from the first memory device (page 6, lines 24-31 – the threshold determination logic 126 may be configured to retrieve the RBER and the UBER from the SDC mitigating memory 124. The threshold determination logic 126 may then be configured to identify the ECC and the corresponding codeword size N implemented by the error correction circuit 112); and changing the puncturing option information based on the error rate (page 6, lines 24-31 – the threshold determination logic 126 may be configured to retrieve the RBER and the UBER from the SDC mitigating memory 124. The threshold determination logic 126 may then be configured to identify the ECC and the corresponding codeword size N implemented by the error correction circuit 112).
With respect to claim 19, the VANAPARTHY reference teaches further comprising outputting failure alarm information to a system in response to the error rate being greater than a predetermined value (page 2, lines 30-40 – relatively large RBER is related to the failure mode (e.g., word line or bit line failure) of the selected memory device).
With respect to claim 20, the VANAPARTHY reference teaches further comprising moving erroneous data to a second memory device different from the first memory device in response to an error rate of data read from the first memory device being greater than or equal to a reference value (page 2, lines 6-15 – error correction code may provide less reliability than, for example, an uncorrectable bit error rate (UBER) of 1E-17, wherein the input (i.e., the original) bit error rate (RBER) is approximately 1E-3. This can be accomplished by encoding a sequence of K data bits into a sequence of N codeword bits including N-K parity bits. The N-bit codeword may then be stored on a medium. The errors introduced by the non-ideal characteristics of the medium may be included in the data read from the medium. The decoder can be configured to recover the encoded sequence of K bits in the presence of at least some errors).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
6/24/26
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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