Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 8, 10-13, and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Publication No. 20230422165 to Sun et al.
Referring to claim 1, Sun et al disclose in Figures 1-9 a method for activating a TRS, comprising:
Receiving (steps 905, 910), by a terminal device (UE), a first MAC CE (SCell activation/deactivation MAC-CE of Figures 6a-6b) sent by a network device (BS), wherein the first MAC CE is used for indicating whether each of a plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and indicating whether TRSs (AP-TRS) of at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 2, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries first information (C-fields) and second information (CSI request field), wherein the first information is used for indicating whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and the second information is used for indicating whether the TRSs of the at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 3, Sun et al disclose in Figures 1-9 wherein at least one first SCell of the plurality of SCells is to be activated through indication of the first information (SCells, indicated by a corresponding SCell index, is to be activated when C-field set to 1 or deactivated when C-field set to 0), and the second information is used for indicating whether a TRS of the at least one first SCell is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
The second information comprises TRS information corresponding to each of the at least one first SCell (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field), wherein the TRS information is used for indicating whether a TRS of a first SCell corresponding to the TRS information is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 7, Sun et al disclose in Figures 1-9 a method for activating a TRS, comprising:
Sending (steps 905, 910), by a network device (BS), a first MAC CE (SCell activation/deactivation MAC-CE of Figures 6a-6b) to a terminal device (UE), wherein the first MAC CE is used for indicating whether each of a plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and indicating whether TRSs (AP-TRS) of at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 8, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries first information (C-fields) and second information (CSI request field), wherein the first information is used for indicating whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and the second information is used for indicating whether the TRSs of the at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
Wherein at least one first SCell of the plurality of SCells is to be activated through indication of the first information (SCells, indicated by a corresponding SCell index, is to be activated when C-field set to 1 or deactivated when C-field set to 0), and the second information is used for indicating whether a TRS of the at least one first SCell is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
The second information comprises TRS information corresponding to each of the at least one first SCell (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field), wherein the TRS information is used for indicating whether a TRS of a first SCell corresponding to the TRS information is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 10, Sun et al disclose in Figures 1-9 wherein:
The TRS information in the second information in an order from front to back corresponds to the at least one first SCell in an ascending order of SCell indexes (increasing order of i, wherein each i represents a SCell index). In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. So: the AP-TRS activation information in the CSI request field corresponds to a SCell in an increasing order of SCell indexes i.
Or, the TRS information in the second information in the order from front to back corresponds to the at least one first SCell in a descending order of SCell indexes (not in reference; claim is in “or’ form). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 11, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries first information (C-fields) and second information (CSI request field), wherein the first information is used for indicating whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and the second information is used for indicating whether the TRSs of the at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
The second information is used for indicating whether TRSs of all of the plurality of SCells are to be activated. A CSI request field is associated with each of the plurality of SCells and is used to indicate AP-TRS activation for each of the plurality of SCells. So: all of the plurality of SCells have an associated CSI request field that can indicate the claimed “whether TRSs of all of the plurality of SCells are to be activated”.
The second information comprises TRS information corresponding to each of the plurality of SCells (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field), wherein the TRS information is used for indicating whether a TRS of a first SCell corresponding to the TRS information is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 12, Sun et al disclose in Figures 1-9 a device (UE) for activating a TRS, applied to a terminal device (UE), wherein the device comprises:
A processor (processor 205), a memory (memory 210) configured to store a computer-executable instructions, and a transceiver (transceiver 225).
Wherein the processor is configured to invoke and run the computer-executable instructions stored in the memory to perform an operation of (processor 205 executes instructions stored in memory 210 to perform UE functions):
Receiving (steps 905, 910), via the transceiver, a first MAC CE (SCell activation/deactivation MAC-CE of Figures 6a-6b) sent by a network device (BS), wherein the first MAC CE is used for indicating whether each of a plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and indicating whether TRSs (AP-TRS) of at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 13, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries third information (C-field or CSI request field) for indicating at least one of: whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), or whether a TRS of the SCell is to be activated (AP-TRS of an activated SCell is activated by a CSI request field).
Wherein the third information comprises N bits (Ci field of 31 bits or CSI request field of 6 bits), each M bits (each Ci field or each CSI request field) among the N bits corresponds to one SCell (each Ci field corresponds to one SCell according to the SCell index i), a value of the M bits is used for indicating whether the SCell corresponding to the M bits is to be activated (C-field set to 1) or deactivated (C-field set to 0), or whether a TRS of the SCell is to be activated (CSI request field has a maximum of 6 bits to index one out of 64 RRC-configured AP-TRS that is to be activated) , where N and M are positive integers (1 or more bits). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 15, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries first information (C-fields) and second information (CSI request field), wherein the first information is used for indicating whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and the second information is used for indicating whether the TRSs of the at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
The second information is used for indicating whether TRSs of all of the plurality of SCells are to be activated. A CSI request field is associated with each of the plurality of SCells and is used to indicate AP-TRS activation for each of the plurality of SCells. So: all of the plurality of SCells have an associated CSI request field that can indicate the claimed “whether TRSs of all of the plurality of SCells are to be activated”.
The second information comprises TRS information corresponding to each of the plurality of SCells (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field), wherein the TRS information is used for indicating whether a TRS of a first SCell corresponding to the TRS information is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 16, Sun et al disclose in Figures 1-9 wherein the first MAC CE further carries fourth information (CSI request field) comprising TRS information corresponding to each of at least one target SCell, wherein the target SCell is a to-be-activated SCell of which the TRS is to be activated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. So: when a SCell is to be activated, the corresponding TRS for the to-be-activated SCell is also activated (claimed “the target SCell is a to-be-activated SCell of which the TRS is to be activated”). In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered So: when a SCell is to be activated, the corresponding TRS for the to-be-activated SCell is also activated (claimed “the target SCell is a to-be-activated SCell of which the TRS is to be activated”). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 17, Sun et al disclose in Figures 1-9 a device (BS) for activating a TRS, applied to a network device (BS), wherein the device comprises:
A processor (processor 305), a memory (memory 310) configured to store a computer-executable instructions, and a transceiver (transceiver 325).
Wherein the processor is configured to invoke and run the computer-executable instructions stored in the memory to perform an operation of (processor 305 executes instructions stored in memory 310 to perform BS functions):
Sending (steps 905, 910), via the transceiver, a first MAC CE (SCell activation/deactivation MAC-CE of Figures 6a-6b) to a terminal device (UE), wherein the first MAC CE is used for indicating whether each of a plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and indicating whether TRSs (AP-TRS) of at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered. Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 18, Sun et al disclose in Figures 1-9 wherein the first MAC CE carries first information (C-fields) and second information (CSI request field), wherein the first information is used for indicating whether each of the plurality of SCells (indicated by a corresponding SCell index) is to be activated (C-field set to 1) or deactivated (C-field set to 0), and the second information is used for indicating whether the TRSs of the at least part of the plurality of SCells are to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
Wherein at least one first SCell of the plurality of SCells is to be activated through indication of the first information (SCells, indicated by a corresponding SCell index, is to be activated when C-field set to 1 or deactivated when C-field set to 0), and the second information is used for indicating whether a TRS of the at least one first SCell is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field).
The second information comprises TRS information corresponding to each of the at least one first SCell (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field), wherein the TRS information is used for indicating whether a TRS of a first SCell corresponding to the TRS information is to be activated (when a SCell is activated, MAC-CE activates the corresponding AP-TRS via the CSI request field). A SCell activation/deactivation MAC-CE comprises 31 C-fields; a C-field set to 1 indicates the SCell with the corresponding SCell index is to be activated, and a C-field set to 0 indicates the SCell with the corresponding SCell index is to be deactivated. In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS. In Figure 6b: SCell activation/deactivation MAC-CE includes a five bit SCell index field and a six bit CSI request field for each activated SCell; the SCell index indicates the SCell that is to be activated and the CSI request indicates the AP-TRS that is to be triggered.
Wherein the TRS information comprises a TRS index, a value of the TRS index being used for indicating whether the TRS is to be activated (not in reference; claim is in “or” form); or, the TRS information comprises the TRS index (Section 0044: “maximum 6 bits to index one out of 64 RRC-configured AP-TRS”) and at least one of TRS burst information (not in reference; claim is in “or” form) or TRS offset information (Sections 0042 and 0047: TRS information includes slot offset information which is a slot offset between the DCI that triggers the AP-TRS and the actual transmission of the AP-TRS). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 19, Sun et al disclose in Figures 1-9 wherein when the TRS information comprises the TRS index (Section 0044: “maximum 6 bits to index one out of 64 RRC-configured AP-TRS”), a number of bits occupied by the TRS index is fixed (not in reference; claim is in “or” form); or a number of bits occupied by the TRS index is variable (not in reference; claim is in “or” form).
Wherein in a case where the number of bits occupied by the TRS index is fixed, the number of bits occupied by the TRS index is determined based on a number of TRS configurations supported by a second SCell among the plurality of SCells, wherein the second SCell is an SCell supporting a maximum number of TRS configurations among the plurality of SCells (not in reference; limitation refers to the claimed “the number of bits occupied by the TRS index is fixed” which is not in the reference since claim is in “or” form).
In a case where the number of bits occupied by the TRS index is variable, the number of bits occupied by the TRS index is determined based on first configuration information sent by the network device, wherein the first configuration information is used for configuring the number of bits occupied by the TRS index with a granularity of SCell, or the first configuration information is used for configuring the number of bits occupied by the TRS index with a granularity of terminal device (not in reference; limitation refers to the claimed “the number of bits occupied by the TRS index is variable” which is not in the reference since claim is in “or” form). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Referring to claim 20, Sun et al disclose in Figures 1-9 wherein when TRS information comprises the TRS index (Section 0044: “maximum 6 bits to index one out of 64 RRC-configured AP-TRS”) and at least one of the TRS burst information (not in reference; claim is in “or” form) or the TRS offset information (Sections 0042 and 0047: TRS information includes slot offset information which is a slot offset between the DCI that triggers the AP-TRS and the actual transmission of the AP-TRS), a number of bits occupied by the TRS burst information is fixed (not in reference; limitation refers to the claimed “TRS burst information” which is not in the reference since claim is in “or” form); or a number of bits occupied by the TRS burst information is variable (not in reference; limitation refers to the claimed “TRS burst information” which is not in the reference since claim is in “or” form).
Wherein in a case where the number of bits occupied by the TRS burst information is fixed, the number of bits occupied by the TRS burst information is determined based on a number of TRS bursts supported by a third SCell among the plurality of SCells, wherein the third SCell is an SCell supporting a maximum number of TRS bursts among the plurality of SCells (not in reference; limitation refers to the claimed “TRS burst information” which is not in the reference since claim is in “or” form).
In a case where the number of bits occupied by the TRS burst information is variable, the number of bits occupied by the TRS burst information is determined based on second configuration information sent by the network device, wherein the second configuration information is used for configuring the number of bits occupied by the TRS burst information with a granularity of SCell, or the second configuration information is used for configuring the number of bits occupied by the TRS burst information with a granularity of terminal device (not in reference; limitation refers to the claimed “TRS burst information” which is not in the reference since claim is in “or” form). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 20230422165 to Sun et al in further view of U.S. Publication No. 20210135821 to Guan et al.
Referring to claim 4, Sun et al disclose in Figures 1-9 wherein the TRS information comprises a TRS index (Section 0044) … In Figure 6a: SCell activation/deactivation MAC-CE includes 31 C-fields; for each Ci that is 1, in increasing order of i, the MAC-CE also triggers the corresponding AP-TRS via the CSI request field, which has a maximum 6 bits to index one out of 64 RRC-configured AP-TRS (claimed “TRS index”). Refer to Sections 0017-0082, specifically Sections 0039-0048 and 0052-0057.
Sun et al do not disclose wherein the TRS information comprises a TRS index, a value of the TRS index being used for indicating whether the TRS is to be activated.
Guan et al disclose in Figures 1-20 and Sections 0178, 0181, 0184, 0191, and 0205 wherein a MAC-CE includes an ID of the serving cell, an ID of a BWP, and an indication bit used to indicate whether a TCI state is activated. Each TCI state is associated with a TRS. UE receives indication information in an M-bit bitmap from BS, to indicate which TRS are activated, wherein each TRS must be identified by an index (Section 0191) to distinguish between different TRS. The M-bit bitmap is used to indicate a specific TRS that is activated, where 1 indicates that a TRS is activated, and 0 indicates that a TRS is not activated, or 1 indicates that a TRS is not activated, and 0 indicates that a TRS is activated (claimed “a value of the TRS index being used for indicating whether the TRS is to be activated”). Refer to Sections 0095-0285. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the TRS information comprises a TRS index, a value of the TRS index being used for indicating whether the TRS is to be activated. One would have been motivated to do so to indicate to UE which TRS are activated and which TRS are deactivated, thereby facilitating TRS reception.
Referring to claim 5, Sun et al do not disclose wherein when the value of the TRS index is a first value, the TRS index is used for indicating that the TRS is not to be activated; and when the value of the TRS index is not the first value, the TRS index is used for indicating that the TRS is to be activated.
Guan et al disclose in Figures 1-20 and Sections 0178, 0181, 0184, 0191, and 0205 wherein a MAC-CE includes an ID of the serving cell, an ID of a BWP, and an indication bit used to indicate whether a TCI state is activated. Each TCI state is associated with a TRS. UE receives indication information in an M-bit bitmap from BS, to indicate which TRS are activated, wherein each TRS must be identified by an index (Section 0191) to distinguish between different TRS. The M-bit bitmap is used to indicate a specific TRS that is activated, where 1 indicates that a TRS is activated (claimed “when the value of the TRS index is a not the first value, the TRS index is used for indicating that the TRS is to be activated”), and 0 indicates that a TRS is not activated (claimed “when the value of the TRS index is a first value, the TRS index is used for indicating that the TRS is not to be activated”), or 1 indicates that a TRS is not activated (claimed “when the value of the TRS index is a first value, the TRS index is used for indicating that the TRS is not to be activated”), and 0 indicates that a TRS is activated (claimed “when the value of the TRS index is not the first value, the TRS index is used for indicating that the TRS is to be activated”). Refer to Sections 0095-0285. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the TRS information comprises a TRS index, a value of the TRS index being used for indicating whether the TRS is to be activated. One would have been motivated to do so to indicate to UE which TRS are activated and which TRS are deactivated, thereby facilitating TRS reception.
Referring to claim 6, Sun et al do not disclose wherein the TRS index is further used for indicating a TRS configuration in a case where the value of the TRS index is not the first value.
Guan et al disclose in Figures 1-20 and Sections 0178, 0181, 0184, 0191, and 0205 wherein a MAC-CE includes an ID of the serving cell, an ID of a BWP, and an indication bit used to indicate whether a TCI state is activated. Each TCI state is associated with a TRS. UE receives indication information in an M-bit bitmap from BS, to indicate which TRS are activated, wherein each TRS must be identified by an index to distinguish between different TRS. The M-bit bitmap is used to indicate a specific TRS that is activated, where 1 indicates that a TRS is activated, and 0 indicates that a TRS is not activated, or 1 indicates that a TRS is not activated, and 0 indicates that a TRS is activated. Sections 0016, 0020, 0027, 0038, 0138, 0183, and 0214: when BS activates a TRS, BS also provides TRS configuration to UE. Refer to Sections 0095-0285. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the TRS information comprises a TRS index, a value of the TRS index being used for indicating whether the TRS is to be activated. One would have been motivated to do so so that when TRS is activated, BS can provide TRS configuration to UE to configure the activated TRS.
Allowable Subject Matter
Claims 9 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Publication No. 20220086676 to Ai et al disclose in Figures 1-12 and Sections 0023, 0040, 0043, 0050, 0053, 0068, 0069, 0073, and 0075-0085 wherein a SCell can be in an activated state, a deactivated state or a dormant state; a SCell can be transited to an activated state by a SCell activation MAC CE; periodic TRS resource for SCell can be configured wherein when UE receives MAC CE for SCell activation, UE can detect the TRS according to configured offset and periodicity. Refer to Sections 0023-0089.
U.S. Publication No. 20190356444 to Noh et al disclose in Figures 1-23 and Sections 0112-0113, 0168-0170 wherein a MAC CE is used for SCell activation and deactivation; BS instructs UE to perform SCell activation using a MAC CE and if it is determined that TRS transmission is required in the activated SCell, BS triggers an A-TRS to UE through a CSI request field. Refer to Sections 0038-0186.
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/Christine Ng/
Examiner, AU 2464
February 20, 2026