DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-13, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banik (USP 5,656,962).
For claim 1, Figures 3, 5, 6, and 7 of Banik each teaches a circuit comprising: a latch (313-317, 319, 519, 722) comprising: a drive path circuitry (316-317) configured to transmit an output signal (OUTPUT 208); and a storage path circuitry (313-315, 319, 519, 722) configured to retain the output signal (OUTPUT 208).
For claim 2, Figures 3, 5, 6, and 7 of Banik each teaches a portion (519, 317) of each of the drive path circuitry (316-317) and the storage path circuitry (313-315, 319, 519, 722) is configured as a multiplexer (519, 317); a selector signal (CLOCK, output of 318) configured as a selector of the multiplexer (519, 317); the multiplexer (519, 317) is configured to select between a drive path signal (output of 316) and a storage path signal (output of 315) and transmit a multiplexed output signal (OUTPUT 208); and the drive path signal (output of 316) corresponds to the output signal (OUTPUT 208).
For claim 3, Figures 3, 5, 6, and 7 of Banik each teaches wherein the portion (519, 317) comprises a pass gate (519, 317).
For claim 4, Figures 6 and 7 of Banik each teaches clock restructuring circuitry (318, 620) comprising: first and second clock gates (318 and 620) configured to generate first and second clock inverter signals (output of 318, and output of 620), wherein the selector signal (CLOCK, output of 318) comprises one of the clock signal (CLOCK) or the first clock inverter signal (output of 318).
For claim 5, Figures 6 and 7 of Banik each teaches the first and second clock gates (318 and 620) are serially coupled; the first and second clock inverter signals (output of 318, and output of 620) comprise a different polarity; and the clock signal (CLOCK) and the second clock inverter signal (output of 620) comprise a same polarity.
For claim 8, Figures 3, 5, 6 and 7 of Banik each teaches the storage path circuitry (313-315, 319, 519, 722) comprises two pass gates (319, 519); the drive path circuitry (316, 317) comprises a sole pass gate (317); and the sole pass gate (317) of the drive path circuitry (316, 317) is configured to generate the output signal (OUTPUT 208), and wherein the drive path circuitry (316, 317) is distinct from the storage path circuitry (313-315, 319, 519, 722).
For claim 9, Figures 3, 5, 6 and 7 of Banik each teaches a master latch (310-312 and 721) coupled to the latch (313-317, 319, 519, 722), wherein the latch (313-317, 319, 519, 722) comprises a slave latch (313-317, 319, 519, 722).
For claim 10, Figures 6 and 7 of Banik each teaches wherein the master latch (310-312 and 721) comprises a first storage node (output of 311); the slave latch (313-317, 319, 519, 722) comprises a second storage node (output of 313); each of the master latch (310-312 and 721) and the slave latch (313-317, 319, 519, 722) comprises a respective feedback loop memory structure (311-312 and 721; 313-314 and 722) coupled to the first storage node and the second storage node, respectively, wherein the feedback loop memory structure (311-312 and 721; 313-314 and 722) comprises an inverter (311; 313) and a tri-state inverter (312 and 721; 313 and 722); and the drive path circuitry (316-317) of the slave latch (313-317, 319, 519, 722) is distinct from the first and second storage nodes (output of 311; output of 313).
For claim 11, Figures 3, 5, 6 and 7 of Banik each teaches a master latch (310-312 and 721) coupled to the latch (313-317, 319, 519, 722), wherein the latch (313-317, 319, 519, 722) comprises a slave latch (313-317, 319, 519, 722); and the slave latch (313-317, 319, 519, 722) comprises multiplexer circuitry (519, 317) configured to select between a first input signal (input of 316) and a second input signal (input of 315); wherein the multiplexer circuitry (519, 317) is formed from portions of the drive path circuitry (316-317) and the storage path circuitry (313-315, 319, 519, 722).
For claim 12, Figures 3, 5, 6 and 7 of Banik each teaches the multiplexer circuitry (519, 317) comprises a pass gate (519) of the storage path circuitry (313-315, 319, 519, 722) and a pass gate (317) of the drive path circuitry (316, 317); the first input signal (input of 316) corresponds to a drive path signal (input of 316) of the drive path circuitry (316, 317) and the second input signal (input of 315) corresponds to a storage path signal (input of 315) of the storage path circuity (313-315, 319, 519, 722); and the multiplexer circuitry (519, 317) is configured to transmit a multiplexed output signal (OUTPUT 208); wherein the multiplexer circuitry (519, 317) is disposed within the slave latch (313-317, 319, 519, 722) and is configured to select between the storage path circuitry (313-315, 319, 519, 722) and the drive path circuitry (316, 317).
For claim 13, Figures 3, 5, 6 and 7 of Banik each teaches wherein: the pass gate (519) of the storage loop circuitry (313-315, 319, 519, 722) and the pass gate (317) of the drive path circuitry(316, 317) are configured to operate out-of-phase; and the out-of-phase operation comprises opposing activation of the storage path circuitry (313-315, 319, 519, 722) and the drive path circuitry (316, 317), wherein the multiplexer (519, 317) is configured, during activation of the drive path circuitry (316, 317), to couple the drive path circuitry (317, 317) to an output node (208).
For claim 17, Figures 3, 5, 6 and 7 of Banik each teaches a method comprising: in response to a first occurrence of a first phase of a clock signal (CLOCK), receiving, at a first latch (310-312 and 721), an input signal (INPUT 209); and in response to a first occurrence of a second phase of the clock signal (CLOCK): receiving, at a drive path circuitry (316, 317) of a second latch (313-317, 319, 519, 722), the input signal (209) from the first latch (310-312 and 721), and transmitting the input signal (209) from the drive path circuitry (316, 317) of the second latch (313-317, 319, 519, 722), wherein the drive path circuitry (316, 317) is distinct from a storage path circuitry (313-315, 319, 519, 722) of the second latch (313-317, 319, 519, 722).
For claim 18, Figures 3, 5, 6 and 7 of Banik each teaches in response to the first occurrence of the first phase of the clock signal (CLOCK), storing, at the first latch (310-312 and 721), the input signal (209); and storing, at the storage path circuitry (313-315, 319, 519, 722) of the second latch (313-317, 319, 519, 722), a stored input signal (output of 313), wherein, during the transmitting, the input signal (209) is transmitted via the drive path circuitry (316, 317) of the second latch (313-317, 319, 519, 722).
For claim 19, Figures 3, 5, 6 and 7 of Banik each teaches in response to a second occurrence of the first phase of the clock signal (CLOCK), storing, at the storage path circuitry (313-315, 319, 519, 722) of the second latch (313-317, 319, 519, 722), the input signal (209).
Claims 1, 9, and 17-19 are also rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inoue (USP 7,492,202).
For claim 1, Figures 3-4 of Inoue each teaches a circuit comprising: a latch (102, 307) comprising: a drive path circuitry (115) configured to transmit an output signal (output of 115); and a storage path circuitry (116) configured to retain the output signal (output of 115).
For claim 9, Figures 3-4 of Inoue each teaches a master latch (101) coupled to the latch (102, 307), wherein the latch (102, 307) comprises a slave latch (102, 307).
For claim 17, Figures 3-4 of Inoue each teaches a method comprising: in response to a first occurrence of a first phase of a clock signal (Timing Signal 104), receiving, at a first latch (101), an input signal (Data Input 105); and in response to a first occurrence of a second phase of the clock signal (104): receiving, at a drive path circuitry (115) of a second latch (102), the input signal (105) from the first latch (101), and transmitting the input signal (105) from the drive path circuitry (115) of the second latch (102), wherein the drive path circuitry (115) is distinct from a storage path circuitry (116) of the second latch (102).
For claim 18, Figures 3-4 of Inoue each teaches in response to the first occurrence of the first phase of the clock signal (104), storing, at the first latch (101), the input signal (105); and storing, at the storage path circuitry (116) of the second latch (102), a stored input signal (output of 115), wherein, during the transmitting, the input signal (105) is transmitted via the drive path circuitry (115) of the second latch (102).
For claim 19, Figures 3-4 of Inoue each teaches in response to a second occurrence of the first phase of the clock signal (104), storing, at the storage path circuitry (116) of the second latch (102), the input signal (105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Liu (USP 6,583,656).
For claim 6, Figures 6-7 of Banik each teaches all the limitations of this claim including a clock restructuring circuitry (318, 620). Banik does not teach the clock restructuring circuitry comprising: a third clock gate configured to the generate a third clock inverter signal, wherein: the third clock gate is parallel coupled to the first and second clock gates; the first and the third clock inverter signals comprise a same polarity; and selector signal comprises the third clock inverter signal. However, Figure 1 of Liu teaches a clock restructuring circuitry (14, 12, 10) comprising: a third clock gate (10) configured to the generate a third clock inverter signal (CLKB), wherein: the third clock gate (10) is parallel coupled to the first (14) and second (12) clock gates; the first and the third clock inverter signals (ICLKB and CLKB) comprise a same polarity. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figures 6-7 of Banik to use the clock restructuring circuitry (14, 12, 10) as taught in Figure 1 of Liu to replace the broad restructuring circuitry (318, 620) for the purpose of generating a differential clock signals so as it can be used in a high-speed system (Liu, Col. 1, lines 17-31). Thus, this combination/modification teaches all the limitations of claim 6 including wherein the selector signal comprises the third clock inverter signal (CLKB).
Claims 7, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Venugopal et al. (USP 11,139,803).
For claim 7, Figures 6-7 of Banik each teaches all the limitations of this claim including a clock restructuring circuitry (318, 620), wherein the selector signal (output of 318 is a selector for multiplexer 519, 317) comprises the first clock inverter signal (output of 318). Banik does not teach the clock restructuring circuitry comprising: a third clock gate configured to the generate a third clock inverter signal, wherein: the third clock gate is serially coupled to the first and second clock gates; and the first and the third clock inverter signals comprises a same polarity. However, Figure 2 of Venugopal et al. teaches a clock restructuring circuitry (222, 224, 226) comprising: first, second, and third clock gates (222, 224, 226) configured to generate first, second, and third clock inverter signals (CLK_L, CLK2, CLK3_L), wherein: the third clock gate (226) is serially coupled to the first and second clock gates 222, 224); and the first and the third clock inverter signals (CLK_L and CLK3_L) comprises a same polarity. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figures 6-7 of Banik to use the clock restructuring circuitry (222, 224, 226) as taught in Figure 2 of Venugopal et al. to replace the broad restructuring circuitry (318, 620) for the purpose of achieving a balance of rising and falling edges of the flip-flop (Venugopal et al., Col. 9, lines 4-20). Thus, this combination/modification teaches all the limitations of claim 7.
For claim 16, Figures 3, 5, 6, and 7 of Banik each teaches all the limitations of this claim including a clock restructuring circuitry (120) except for the clock restructuring circuitry comprising: first, second, and third clock gates configured to generate first, second, and third clock inverter signals supplied to the slave latch, wherein either: the first, second, and third clock gates are serially coupled; or the first and second clock gates are parallel coupled to the third clock gate. However, Figure 2 of Venugopal et al. teaches a clock restructuring circuitry (222, 224, 226) comprising: first, second, and third clock gates (222, 224, 226) configured to generate first, second, and third clock inverter signals (CLK_L, CLK2, CLK3_L), wherein the first, second, and third clock gates (222, 224, 226) are serially coupled. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify each circuitry of Banik to use the clock restructuring circuitry (222, 224, 226) as taught in Figure 2 of Venugopal et al. to control the flip-flop for the purpose of achieving a balance of rising and falling edges of the flip-flop (Venugopal et al., Col. 9, lines 4-20).
For claim 20, the combination/modification of Banik and Venugopal et al. as discussed in claims 7 and 16 above also teaches a circuit (the combination/modification of Inoue and Venugopal et al. as discussed) comprising: clock restructuring circuitry (222, 224, 226; Figure 2 of Venugopal et al.) configured to generate respective first, second, and third clock inverter signals (CLK_L, CLK2, CLK3_L); a first latch (310-312 and 721 in Figures 3 and 6-7 of Banik) configured to transmit a drive path signal (input of 316); a second latch (313-317, 319, 519, and 722 in Figures 3 and 6-7 of Banik) configured to transmit a storage path signal (output of 313); and a multiplexer (519, 317), wherein: one or more transistor devices of the first (310-312 and 721 in Figures 3 and 6-7 of Banik) and the second (313-317, 319, 519, and 722 in Figures 3 and 6-7 of Banik) latches are activated by the second or the third clock inverter signals (CLK2, CLK3_L) ; the multiplexer (519, 317) is configured to select between the drive path signal (input of 316) and the storage path signal (output of 313) based on a selector signal; and the selector signal is either a clock signal (CLK) or the first clock inverter signal (CLK_L).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Maeno (USP 8,274,319).
For claim 15, Figures 3, 5, 6, and 7 of Banik each teaches all the limitations of this claim as discussed in the 102 rejection above except for the layout of the circuit wherein “one or more of: a clock signal supplied to the slave latch, a first clock inverter signal supplied to the slave latch, the multiplexer circuitry of the slave latch, and an output buffer coupled to the slave latch are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break”. However, Maeno teaches a flip-flop with a layout wherein one or more of: a clock signal, a first clock inverter signal, the multiplexer circuitry, and an output buffer are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break (see Figures 8-9). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify each circuitry of the Banik so that the flip-flop has the layout wherein “one or more of: a clock signal supplied to the slave latch, a first clock inverter signal supplied to the slave latch, the multiplexer circuitry of the slave latch, and an output buffer coupled to the slave latch are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break”, as taught in Maeno, for the purpose of decreasing the chip size (Maeno, Col. 5, lines 17-30).
Response to Arguments
Applicant's arguments filed on 12/31/25 have been fully considered but they are not persuasive.
Applicant argues that “The Office Action’s mapping improperly aggregates separate
blocks in Banik into a singled alleged “latch” … The Office Action's mapping effectively collects components from different functional blocks (e.g.. the bypass block and separate master and slave blocks) and labels the resulting collection a single "latch". That approach is inconsistent with Banik's own partitioning and is not a proper anticipation analysis”.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the claims: i.e., i) a "latch" to elements 313-317, 319, 519, 722, (ii) "drive path circuitry" to elements 316- 317 configured to transmit an output signal (OUTPUT 208), and (iii) "storage loop circuitry" to elements 313-315, 319, 519, 722 configured to retain the output signal (OUTPUT 208).
Applicant further argues that “Banik's alleged "drive path circuitry (316-317)" is not
circuitry of the claimed latch, and is not the claimed drive path. The Office Action maps Banik's alleged "drive path circuitry" to elements 316-317 path. However, in Banik, elements 316-317 reside in the bypass block (207),which exists specifically to provide a bypass around portions of the flip-flop. The bypass block is not part of the slave latch portion (i.e., SLAVE 206) itself; it is a separate path that can drive or affect the output through a bypass function. Accordingly, even if Banik's bypass circuitry can influence OUTPUT 208, that does not contemplate (and therefore cannot disclose) a latch that "comprises a drive path circuitry" as required by claim 1 … Banik's bypass path is, by design, separate and external from the slave latch (206) and is provided to route signals around the slave latch rather than through it. As such, the bypass circuitry cannot reasonably be treated as "drive path circuitry" of the latch, because the claim requires that the drive path circuitry be circuitry of the latch itself”.
However, this argument is not persuasive because the because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered as “a latch” and it is reasonable to consider "drive path circuitry (316-317)" is the drive path circuitry of the claim’s latch.
Applicant further argues that “Banik's identified "storage loop circuitry" does not "retain
the output signal" as claimed. The Office Action further asserts that Banik's "storage loop circuitry" (e.g., 313-315, 319, etc.) is "configured to retain the output signal (OUTPUT 208)." That characterization is not supported by Banik's latch topology. In Banik's latch portions, the feedback circuitry is arranged to retain an internal storage state (i.e., an internal node value within the latch), not to retain the output signal (OUTPUT 208) in the manner claimed. In Banik, OUTPUT 208 is generated at an output stage of the slave portion (and may also be affected by the bypass block). The feedback circuitry in the latch portion retains a stored state at internal nodes of the latch; it does not describe "storage path circuitry configured to retain the output signal", as recited. Put differently, Banik's latch feedback retains the latch's internal storage node value; the Office Action's mapping equates that internal storage function with "retaining the output signal (OUTPUT 208)", which is not the same disclosure and is not what is claimed”.
However, this argument is not persuasive because, again, the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for elements of the circuit; so for broadest reasonable interpretation, it is reasonable to consider the elements (313-315, 319, 519, 722) in Banik as the “storage path circuit” to retain the output (208) because, in Banik’s Figures 3 and 5-7, the drive path circuitry (316-317) provides transmit an output signal (208) and the “storage path circuit” (313-315, 319, 519, 722) which also provides output signal (208) so it is reasonable to be considered as “to retain the output signal”.
Applicant further argues that Banik does not contemplate (and therefore cannot disclose)
the claimed latch architecture. Claim 1 requires a latch architecture that includes both a storage path (for retention) and a drive path (for transmission) as circuitries of the latch.
Importantly, Banik's core design premise is to separate "fast output" behavior from "storage" behavior using an external bypass. In Banik, "bypass 207 does not store the signal from master portion 205 and thus, it can transmit a signal to output 208 faster than slave portion 206 which does store the signal from master portion 205" (see Banik, col. 3, II. 22- 25) and "slave portion 206 in this embodiment, is only used for storage purposes" (see id, col. 3, II. 31-32). That architecture is fundamentally different from claim 1's structure in which the claimed latch itself comprises both the drive path circuitry and the storage path circuitry. Banik's disclosure does not contemplate a single latch that integrates both circuitries as internal latch paths. Rather, Banik teaches that storage is handled by the (slave) latch, while speed is achieved by routing around that storage circuitry through a separate bypass circuit. Accordingly, Banik does not contemplate (and therefore cannot disclose) the limitations of claim 1”.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the claims: i.e., i) a "latch" to elements 313-317, 319, 519, 722, (ii) "drive path circuitry" to elements 316- 317 configured to transmit an output signal (OUTPUT 208), and (iii) "storage loop circuitry" to elements 313-315, 319, 519, 722 configured to retain the output signal (OUTPUT 208). Note that all the claim limitations are met because all the elements in the claims are provided in Figures 3 and 5-7 of Banik’s as discussed.
Applicant further argues that Banik's design choice teaches away to the claimed
approach Banik's disclosure is directed to achieving a faster flip-flop behavior by introducing a bypass path external to the latch portions, rather than implementing latch-internal path circuitry as claimed. As would be appreciated, Banik's written description reinforces that its preferred solution is to achieve speed improvements by adding and using a separate bypass circuit and by treating the slave portion as "only" storage. (See Banik, col. 3, lines 22-25, 31-32). Thus, Banik's stated objective and design choice is to maintain a storage-oriented slave portion and to improve output speed by routing the output through an external bypass. This is contrary to the claim 1 architecture, which requires the latch to comprise both the storage path circuitry and the drive path circuitry as part of the latch. At minimum, Banik's approach underscores that Banik does not envision the claimed latch structure and therefore cannot disclose it”.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the claims: i.e., i) a "latch" to elements 313-317, 319, 519, 722, (ii) "drive path circuitry" to elements 316- 317 configured to transmit an output signal (OUTPUT 208), and (iii) "storage loop circuitry" to elements 313-315, 319, 519, 722 configured to retain the output signal (OUTPUT 208). Note that all the claim structure limitations are met because all the elements in the claims are provided in Figures 3 and 5-7 of Banik as discussed.
Applicant further argues that “Improper Broadest Reasonable Interpretation:
The Office Action's anticipation position relies on an overbroad interpretation that effectively collapses Banik's separate master portion, slave portion, and bypass circuit into a single "latch" and then treats circuitry drawn from different blocks as satisfying the "latch comprising" limitations of claim 1. Under a proper broadest reasonable interpretation, the claim language still requires that the recited drive path circuitry and storage path circuitry are circuitries of the latch itself, as opposed to a bypass circuit that is separate from the latch and merely supplies an output. Interpreting "a latch comprising" to encompass unrelated circuitry external to the latch, solely because it affects the same output node, reads structural requirements out of the claim and is not a reasonable construction in view of the specification and the claim context”.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the claims: i.e., i) a "latch" to elements 313-317, 319, 519, 722, (ii) "drive path circuitry" to elements 316- 317 configured to transmit an output signal (OUTPUT 208), and (iii) "storage loop circuitry" to elements 313-315, 319, 519, 722 configured to retain the output signal (OUTPUT 208). Note that all the claim limitations are met because all the elements in the claims are provided in Figures 3 and 5-7 of Banik as discussed.
For claims 17-19, Applicant argues that “The Office Action asserts that FIGS. 3, 5, 6, and 7 of Banik teach the method of claim 17 by mapping: (i) a first latch to elements 310-312 and 721; (ii) a "second latch" to elements 313-315, 319, 519, and 722; and (iii) a "drive path circuitry of the second latch" to elements 316 and 317. Applicant respectfully disagrees. As explained above with respect to claim 1, Banik's elements 316 and 317 are expressly described as part of a bypass circuit (207) that is separate from the slave latch portion (206). Banik repeatedly distinguishes the bypass from the slave latch, explaining that the bypass does not store the signal and is used to avoid the delays of the slave portion, while the slave portion is "only used for storage purposes". Thus, Banik does not contemplate "drive path circuitry of the [same] second latch," as required by claim 17. Rather, Banik describes output transmission during the relevant clock phase via a separate bypass circuit external to the second latch, while the slave latch remains storage-oriented. Accordingly, the Office Action's mapping improperly treats Banik's bypass circuitry as though it were circuitry of the second latch, which is inconsistent with Banik's disclosure and with a reasonable interpretation of the claim language. Because Banik does not describe receiving and transmitting the input signal via a drive path circuitry of the second latch that is distinct from a storage path circuitry of that same latch, Banik cannot anticipate the phase- specific method steps as recited in claim 17. Hence, claim 17 is patentable over Banik. Claims 18-19 are at least patentable over Banik since they depend from claim 17”.
However, this argument is not persuasive because the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3 and 5-7 of Banik is reasonable to be considered with the mapping as discussed above, i.e., “in response to a first occurrence of a first phase of a clock signal (CLOCK), receiving, at a first latch (310-312 and 721), an input signal (INPUT 209); and in response to a first occurrence of a second phase of the clock signal (CLOCK): receiving, at a drive path circuitry (316, 317) of a second latch (313-317, 319, 519, 722), the input signal (209) from the first latch (310-312 and 721), and transmitting the input signal (209) from the drive path circuitry (316, 317) of the second latch (313-317, 319, 519, 722), wherein the drive path circuitry (316, 317) is distinct from a storage path circuitry (313-315, 319, 519, 722) of the second latch (313-317, 319, 519, 722)”.
A. Regarding the Ioue’s reference, Applicant argues Claim 1, as amended, recites: "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal." Inoue discloses a master-slave flip-flop with a separate output selecting portion, not a "latch comprising" both recited circuitries. Inoue's architecture is not a single latch that internally includes both a storage path circuitry and a drive path circuitry. Instead, Inoue's disclosure separates storage functionality (within the latch portions) from output selection and driving (within the selecting portion). Claim 1, however, requires a single latch comprising both the drive path circuitry and the storage path circuitry. Inoue does not contemplate (and therefore cannot disclose) such a latch-level integration.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3-4 of Inoue is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the claims, and that all the limitations of the claims are met as discussed.
B. Applicant further argues that “Inoue's "drive" element (115) is not a drive path circuitry of the claimed latch. The Office Action maps Inoue's inverter 115 to the claimed "drive path circuitry." However, Inoue describes inverter 115 as part of the slave latch portion's output stage whose output is then supplied to the data output selecting portion. In other words, inverter 115 is not disclosed as a distinct drive path circuitry within a latch that is selectively used in lieu of storage circuitry; it is simply part of the conventional slave latch output path. Critically, Inoue's disclosure emphasizes that output selection is performed by the data output selecting portion (e.g., pass gates 117, 118 and inverter 119, or tri-state inverters 317, 318, e.g., as in FIG. 3), not by internal latch path selection. The selecting portion is a separate circuit block whose purpose is to keep input/output physical characteristics constant, not to provide latch-internal drive versus storage paths. Accordingly, mapping inverter 115 to a "drive path circuitry" of the latch reads the selecting portion and its function out of Inoue's disclosure and improperly attributes output- driving behavior to the latch itself”.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, in the circuit in each of the Figures 3-4 of Inoue, it is reasonable to be considered drive element (115) as a drive path circuit because element 115 transmit an output signal as discussed in the claim rejection.
C. Applicant further argues that “Inoue's storage circuitry does not “retain the output signal” as claimed. The Office Action further asserts that Inoue's inverter 116 constitutes "storage loop circuitry configured to retain the output signal." That characterization conflates internal latch storage with retention of the output signal. In Inoue, the slave latch portion holds data internally depending on the timing signal, and the data output selecting portion determines whether the output reflects: . the signal held in the master latch portion (via bypass), or . the signal held in the slave latch portion. In Inoue, the latch circuitry retains an internal storage state, while the output signal is generated downstream of the latch portions by a separate selecting portion and output driver. By contrast, claim 1 recites a latch that itself comprises storage path circuitry configured to retain the output signal alongside drive path circuitry configured to transmit the output signal. Inoue does not contemplate, and therefore cannot disclose, this configuration.
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, in the circuit in each of the Figures 3-4 of Inoue, it is reasonable to be considered element 116 constitutes "storage loop circuitry configured to retain the output signal because the output of 115 is feedback and looping through element 116, and the output of element 116 if fed into the input of 115 and thus 115-116 keep latching and thus retains the output signal 115.
Regarding applicant further argues that “D. Inoue does not contemplate the claimed latch architecture and therefore cannot disclose it”, and E. Broadest reasonable interpretation (BRI) applied to Inoue is improper, such arguments are not persuasive for the similar reasons as discussed above with regard to Banik’s reference, i.e.,
However, this argument is not persuasive because the claim only broadly recites "a circuit comprising: a latch comprising: a drive path circuitry configured to transmit an output signal; and a storage path circuitry configured to retain the output signal"; and the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3-4 of Inoue’s reference is reasonable to be considered as “a latch” and it is reasonable to map the elements as discussed in the rejection above. Note that all the claim limitations are met because all the elements in the claims are provided in Figures 3-4 of Inoue as discussed.
For claims 17-19, Applicant further argues that “Claim 17 recites a phase-dependent method in which, during a first phase of a clock signal, an input signal is received at a first latch, and during a second phase of the clock signal, the input signal is received and transmitted via a drive path circuitry of a second latch, where the drive path circuitry is distinct from a storage path circuitry of that latch. As discussed above with respect to claim 1, Inoue discloses a master-slave flip-flop architecture in which output transmission during different clock states is performed by a data output selecting portion that selects between signals held in the master latch portion and the slave latch portion. Inoue does not contemplate (and therefore cannot disclose) a method in which, during the second clock phase, transmission occurs via a drive path circuitry of the second latch itself that is distinct from the storage path circuitry of that latch. Rather, Inoue teaches that output transmission is effected through selection circuitry external to the latch portions, while the latch portions perform storage operations”.
However, this argument is not persuasive because the claim does not specifically require any specific connections for the elements of the circuit; so for broadest reasonable interpretation, the circuit in each of the Figures 3-4 of Inoue is reasonable to be considered with the mapping as discussed above, i.e., “in response to a first occurrence of a first phase of a clock signal (Timing Signal 104), receiving, at a first latch (101), an input signal (Data Input 105); and in response to a first occurrence of a second phase of the clock signal (104): receiving, at a drive path circuitry (115) of a second latch (102), the input signal (105) from the first latch (101), and transmitting the input signal (105) from the drive path circuitry (115) of the second latch (102), wherein the drive path circuitry (115) is distinct from a storage path circuitry (116) of the second latch (102)”.
Regarding the 103 rejection, Applicant further argues “Claim 6 depends from claim 1. As cited for different claim features, Liu fails to remedy the deficiencies of Banik with regard to claim 1. Thus, claim 1 is patentable over Banik and Liu alone or in cited combinations. Accordingly, claim 6 is patentable over the combination of cited art, at least for its dependence from claim 1”. However, this argument is not persuasive because Banik teaches all the limitations of claim 1 as discussed above.
Regarding the 103 rejection, Applicant further argues “Claims 7 and 16 depend from claims 1 or 17. As cited for different claim features, Venugopal fails to remedy the deficiencies of Banik with regard to claims 1 or 17. Thus, claim 1 is patentable over Banik and Venugopal alone or in cited combinations. Accordingly, claims 7 and 16 are patentable over the combination of cited art, at least for their dependence from either claims 1 or 17”. However, this argument is not persuasive because Banik teaches all the limitations of claims 1, 11 and 17 as discussed above. It is also note that claim 16 depends on claim 11 (not claim 17).
For claim 20, Applicant further argues: A. “The cited art does not disclose the coordinated interaction of clock-restructured latch activation and signal selection. In Banik, clock signals are used to alternately enable latch transparency or bypass behavior, but Banik does not envision the claimed arrangement in which selected clock- restructured signals are used to activate latch devices while a separate selector signal controls multiplexing between latch-derived signals”; B. “Venugopal does not cure the missing coordination between latch activation and signal selection. Venugopal is directed to clock restructuring and the generation of multiple clock inverter signals. While Venugopal may describe circuitry for producing first, second, and third clock inverter signals, it does not address how such clock-restructured signals are to be coordinated with latch operation and signal selection between latch-derived signals, as required by claim 20. In particular, Venugopal does not contemplate: activating transistor devices of both a first latch and a second latch using selected ones of the clock inverter signals, while also controlling a multiplexer that selects between a drive path signal and a storage path signal using either a clock signal or a first clock inverter signal. Accordingly, even if Venugopal's clock restructuring circuitry were combined with Banik, the result would at most be a system in which certain clock-derived signals are generated, without the specific multi-signal coordination between latch activation and signal selection recited in claim 20”.
However, these arguments are not persuasive because applicant’s arguments against the references individually. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It is note that, the 103 rejection was constructed with clearly 5 steps 103 provided, and the combination/modification as discussed teaches all the claims limitations.
Applicant further argues that “C. Claim 20 requires a multi-signal control scheme not contemplated by the cited art. Claim 20 requires a particular control architecture in which: multiple clock inverter signals are generated; selected ones of those clock inverter signals activate transistor devices in both latches; and a selector signal - distinct from the latch-activation signals - controls multiplexing between latch-derived signals. The cited art treats latch activation, bypass behavior, and output selection as largely serial or mutually exclusive operations, rather than as coordinated functions driven by different clock-derived signals as recited. Nothing in Banik or Venugopal teaches or suggests the claimed control scheme”. However, this argument is not persuasive because applicant’s arguments against the references individually. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It is note that, the 103 rejection was constructed with clearly 5 steps 103 provided, and the combination/modification as discussed teaches all the claims limitations.
Applicant further argues that “D. The rejection relies on hindsight reconstruction. Moreover, the Office Action's rejection relies on selecting elements from Banik and Venugopal and then combining them in a manner that mirrors Applicant's disclosure, without any teaching or suggestion in the cited art to do so. In particular, the rejection assumes that clock restructuring from Venugopal would naturally be integrated with Banik's latch and selection logic in the specific manner recited in claim 20. This reconstruction uses Applicant's disclosure as a roadmap and is not supported by the cited references. Absent impermissible hindsight, a person of ordinary skill in the art would have no reason to arrive at the claimed coordination of latch activation and signal selection. (See MPEP §§ 2141, 2143, 2145(X)(A))”.
However, this argument is not persuasive because in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
For claim 15, Applicant further argues “Claim 15 depends from claim 1. As cited for different claim features, Maeno fails to remedy the deficiencies of Banik with regard to claim 1. Thus, claim 1 is patentable over Banik and Maeno alone or in cited combinations. Accordingly, claim 15 is patentable over the combination of cited art, at least for its dependence from claim 1”. However, this argument is not persuasive because Banik teaches all the limitations of claims 1 as discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Long Nguyen/
Primary Examiner
Art Unit 2842