DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/20/26 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7, 10, 11, 13, and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 2, the recitation “a drive path signal and a storage path signal” on line 5-6 is indefinite because it is not clear the relationship of a drive path signal and a storage path signal with the drive path circuitry and the storage path circuitry (i.e., it is not clear which circuitry comprises a drive path signal and a storage path signal, or are they any arbitrary signals). Clarification and/or appropriate correction is required.
Claims 3-7 are indefinite because they depend on claim 2 and include the indefinite problems of claim 2.
For claim 6, the recitation “the selector signal comprises the third clock inverter signal” on line 6 is indefinite because the claim already recited that “the selector signal comprises one of: the clock signal or the first clock inverter signal” (see claim 4, line 4-5), so it is not clear why it is now recited “the selector signal comprises the third clock inverter signal” and that causes the claim to be indefinite because it not clear what exactly the selector signal comprising. Clarification and/or appropriate correction is required.
For claim 10, the recitation “each of the master latch and the slave latch comprises a respective feedback loop memory structure coupled to the storage node and the second storage node, respectively” on line 5-7 is indefinite because the claim is amended to recited the slave latch comprises the storage node (line 3) and the master latch comprises a second storage node (line 4); so it is not understood why it is now recited “each of the master latch and the slave latch comprises a respective feedback loop memory structure coupled to the storage node and the second storage node, respectively” (i.e., how the master latch comprises a respective feedback loop memory structure coupled to the storage node (of the slave latch), and how the slave latch comprises a respective feedback loop memory structure coupled to the second storage node (of the master latch)). Also, the recitation “second storage node” on line 10 lacks clear antecedent basis and should be changed to “the second storage node”. Clarification and/or appropriate correction is required.
For claim 11, the recitation “a first input signal and a second input signal” on line 5 is indefinite because it is not clear a first input signal and a second input signal of which elements in the circuit (i.e., it is not known which circuitry receiving “a first input signal and a second input signal” as recited). Clarification and/or appropriate correction is required.
For claim 13, the recitation “wherein the multiplexer is configured, during activation of the drive path circuitry, to couple the drive path circuitry to an output node” on line 5-6 is indefinite because it is not clear if it should be “to couple the drive path signal to an output node” (instead of “the drive path circuitry”) because the multiplexer is for selecting one signal to the output node. Clarification and/or appropriate correction is required.
Claims 15-16 are indefinite because they depend on claim 11 and include the indefinite problem of claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-13, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banik (USP 5,656,962).
For claim 1, Figure 7 of Banik teaches a circuit comprising: a latch (313-317, 319, 519, and 722 in Figure 7) comprising: a drive path circuitry (316-317) configured to transmit an output signal (OUTPUT 208); and a storage path circuitry (313-315, 319, 519, 722) comprising a storage node (input node of 313) configured to retain the output signal (OUTPUT 208); wherein the drive path circuitry (316-317) is distinct from the storage node (input node of 313).
For claim 2, Figure 7 of Banik teaches a portion of each of the drive path circuitry (316-317) and the storage path circuitry (313-315, 319, 519, 722) is configured as a multiplexer (519, 317); a selector signal (CLOCK, output of 318) configured as a selector of the multiplexer (519, 317); the multiplexer (519, 317) is configured to select between a drive path signal (output of 316) and a storage path signal (output of 315) and transmit a multiplexed output signal (OUTPUT 208); and the drive path signal (output of 316) corresponds to the output signal (OUTPUT 208).
For claim 3, Figure 7 of Banik teaches wherein the portion comprises a pass gate (519, 317).
For claim 4, Figure 7 of Banik teaches clock restructuring circuitry (318, 620) comprising: first and second clock gates (318 and 620) configured to generate first and second clock inverter signals (output of 318, and output of 620), wherein the selector signal (CLOCK, output of 318) comprises one of the clock signal (CLOCK) or the first clock inverter signal (output of 318).
For claim 5, Figure 7 of Banik teaches the first and second clock gates (318 and 620) are serially coupled; the first and second clock inverter signals (output of 318, and output of 620) comprise a different polarity; and the clock signal (CLOCK) and the second clock inverter signal (output of 620) comprise a same polarity.
For claim 8, Figure 7 of Banik each teaches the storage path circuitry (313-315, 319, 519, 722) comprises two pass gates (319, 519); the drive path circuitry (316, 317) comprises a sole pass gate (317); and the sole pass gate (317) of the drive path circuitry (316, 317) is configured to generate the output signal (OUTPUT 208), and wherein the drive path circuitry (316, 317) is distinct from the storage path circuitry (313-315, 319, 519, 722).
For claim 9, Figure 7 of Banik teaches a master latch (310-312 and 721) coupled to the latch (313-317, 319, 519, 722), wherein the latch (313-317, 319, 519, 722) comprises a slave latch (313-317, 319, 519, 722).
Insofar as understood in claim 10, Figure 7 of Banik teaches wherein the slave latch (313-317, 319, 519, 722) comprises the storage node (input node of 313), the master latch (310-312 and 721) comprises a second storage node (output of 311); each of the master latch (310-312 and 721) and the slave latch (313-317, 319, 519, 722) comprises a respective feedback loop memory structure (311-312 and 721; 313-314 and 722) coupled to the second storage node and the storage node, respectively, wherein the feedback loop memory structure (311-312 and 721; 313-314 and 722) comprises an inverter (311; 313) and a tri-state inverter (312 and 721; 313 and 722); and the drive path circuitry (316-317) of the slave latch (313-317, 319, 519, 722) is distinct from the storage node and the second storage node (output of 311; input of 313).
For claim 11, Figure 7 of Banik each teaches a master latch (310-312 and 721) coupled to the latch (313-317, 319, 519, 722), wherein the latch (313-317, 319, 519, 722) comprises a slave latch (313-317, 319, 519, 722); and the slave latch (313-317, 319, 519, 722) comprises multiplexer circuitry (519, 317) configured to select between a first input signal (input of 316) and a second input signal (input of 315); wherein the multiplexer circuitry (519, 317) is formed from portions of the drive path circuitry (316-317) and the storage path circuitry (313-315, 319, 519, 722).
For claim 12, Figure 7 of Banik teaches the multiplexer circuitry (519, 317) comprises a pass gate (519) of the storage path circuitry (313-315, 319, 519, 722) and a pass gate (317) of the drive path circuitry (316, 317); the first input signal (input of 316) corresponds to a drive path signal (input of 316) of the drive path circuitry (316, 317) and the second input signal (input of 315) corresponds to a storage path signal (input of 315) of the storage path circuity (313-315, 319, 519, 722); and the multiplexer circuitry (519, 317) is configured to transmit a multiplexed output signal (OUTPUT 208); wherein the multiplexer circuitry (519, 317) is disposed within the slave latch (313-317, 319, 519, 722) and is configured to select between the storage path circuitry (313-315, 319, 519, 722) and the drive path circuitry (316, 317).
For claim 13, Figure 7 of Banik teaches wherein: the pass gate (519) of the storage path circuitry (313-315, 319, 519, 722) and the pass gate (317) of the drive path circuitry(316, 317) are configured to operate out-of-phase; and the out-of-phase operation comprises opposing activation of the storage path circuitry (313-315, 319, 519, 722) and the drive path circuitry (316, 317), wherein the multiplexer (519, 317) is configured, during activation of the drive path circuitry (316, 317), to couple the drive path circuitry (317, 317) to an output node (208).
For claim 17, Figure 7 of Banik teaches a method comprising: in response to a first occurrence of a first phase of a clock signal (CLOCK), receiving, at a first latch (310-312 and 721), an input signal (INPUT 209); and in response to a first occurrence of a second phase of the clock signal (CLOCK): receiving, at a drive path circuitry (316, 317) of a second latch (313-317, 319, 519, 722), the input signal (209) from the first latch (310-312 and 721), and transmitting the input signal (209) from the drive path circuitry (316, 317) of the second latch (313-317, 319, 519, 722), wherein the second latch includes a storage node (input node of 313) of a storage path circuitry (313-315, 319, 519, 722), the drive path circuitry (316, 317) is distinct from the storage node (input of 313).
For claim 18, Figure 7 of Banik teaches in response to the first occurrence of the first phase of the clock signal (CLOCK), storing, at the first latch (310-312 and 721), the input signal (209); and storing, at the storage path circuitry (313-315, 319, 519, 722) of the second latch, a stored input signal (input of 313), wherein, during the transmitting, the input signal (209) is transmitted via the drive path circuitry (316, 317) of the second latch (313-317, 319, 519, 722).
For claim 19, Figure 7 of Banik teaches in response to a second occurrence of the first phase of the clock signal (CLOCK), storing, at the storage path circuitry (313-315, 319, 519, 722) of the second latch (313-317, 319, 519, 722), the input signal (209).
Claims 1-3, 8, 9, 11-13 and 17-19 are also rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inoue (USP 7,492,202).
For claim 1, Figures 3-4 of Inoue each teaches a circuit comprising: a latch (102, 307) comprising: a drive path circuitry (318) configured to transmit an output signal (106); and a storage path circuitry (102, 317) comprising a storage node (input of 115) configured to retain the output signal (106), wherein the drive path circuitry (318) is distinct from the storage node (input 115).
For claim 2, Figures 3-4 of Inoue each teaches a portion of each of the drive path circuitry (318) and the storage path circuitry (102, 317) is configured as a multiplexer (317, 318); a selector signal (104, output of 120) configured as a selector of the multiplexer (317, 318); the multiplexer (317, 318) is configured to select between a drive path signal (input of 318) and a storage path signal (input of 317) and transmit a multiplexed output signal (output of 317-318); and the drive path signal (input of 318) corresponds to the output signal (output of 317-318).
For claim 3, Figures 3-4 of Inoue each teaches wherein the portion comprises a pass gate (317, 318).
For claim 8, Figures 3-4 of Inoue each teaches the storage path circuitry (102, 317) comprises two pass gates (102, 317); the drive path circuitry (318) comprises a sole pass gate (318); and the sole pass gate (318) of the drive path circuitry (318) is configured to generate the output signal (106), and wherein the drive path circuitry (318) is distinct from the storage path circuitry (102, 317).
For claim 9, Figures 3-4 of Inoue each teaches a master latch (101) coupled to the latch (102, 307), wherein the latch (102, 307) comprises a slave latch (102, 307).
For claim 11, Figures 3-4 of Inoue each teaches a master latch (101) coupled to the latch (102, 307), wherein the latch (102, 307) comprises a slave latch (102, 307); and the slave latch (102, 307) comprises multiplexer circuitry (317, 318) configured to select between a first input signal (input of 318) and a second input signal (input of 317); wherein the multiplexer circuitry (317, 318) is formed from portions of the drive path circuitry (318) and the storage path circuitry (102, 317).
For claim 12, Figures 3-4 of Inoue teaches the multiplexer circuitry (317, 318) comprises a pass gate (317) of the storage path circuitry (102, 317) and a pass gate (318) of the drive path circuitry (318); the first input signal (input of 318) corresponds to a drive path signal (input of 318) of the drive path circuitry (318) and the second input signal (input of 317) corresponds to a storage path signal (input of 317) of the storage path circuity (102, 317); and the multiplexer circuitry (317, 318) is configured to transmit a multiplexed output signal (output of 317-318); wherein the multiplexer circuitry (317, 318) is disposed within the slave latch (102, 307) and is configured to select between the storage path circuitry (102, 317) and the drive path circuitry (318).
For claim 13, Figures 3-4 of Inoue teaches wherein: the pass gate (317) of the storage path circuitry (102, 317) and the pass gate (3178 of the drive path circuitry(318) are configured to operate out-of-phase; and the out-of-phase operation comprises opposing activation of the storage path circuitry (102, 317) and the drive path circuitry (318), wherein the multiplexer (317, 318) is configured, during activation of the drive path circuitry (318), to couple the drive path circuitry (318) to an output node (output of 317-318).
For claim 17, Figures 3-4 of Inoue each teaches a method comprising: in response to a first occurrence of a first phase of a clock signal (Timing Signal 104), receiving, at a first latch (101), an input signal (Data Input 105); and in response to a first occurrence of a second phase of the clock signal (104): receiving, at a drive path circuitry (318) of a second latch (102, 307), the input signal from the first latch (101), and transmitting the input signal (105) from the drive path circuitry (318) of the second latch (102, 307), wherein the second latch (102, 307) includes a storage node (input of 115) of a storage path circuitry (102, 317), and wherein the drive path circuitry (318) is distinct from the storage node (input of 115).
For claim 18, Figures 3-4 of Inoue each teaches in response to the first occurrence of the first phase of the clock signal (104), storing, at the first latch (101), the input signal (105); and storing, at the storage path circuitry (102, 317) of the second latch (102, 307), a stored input signal (output of 115), wherein, during the transmitting, the input signal (105) is transmitted via the drive path circuitry (318) of the second latch (102, 307).
For claim 19, Figures 3-4 of Inoue each teaches in response to a second occurrence of the first phase of the clock signal (104), storing, at the storage path circuitry (102, 317) of the second latch (102, 307), the input signal (105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Liu (USP 6,583,656).
For claim 6, Figure 7 of Banik teaches all the limitations of this claim including a clock restructuring circuitry (318, 620). Banik does not teach the clock restructuring circuitry comprising: a third clock gate configured to the generate a third clock inverter signal, wherein: the third clock gate is parallel coupled to the first and second clock gates; the first and the third clock inverter signals comprise a same polarity; and selector signal comprises the third clock inverter signal. However, Figure 1 of Liu teaches a clock restructuring circuitry (14, 12, 10) comprising: a third clock gate (10) configured to the generate a third clock inverter signal (CLKB), wherein: the third clock gate (10) is parallel coupled to the first (14) and second (12) clock gates; the first and the third clock inverter signals (ICLKB and CLKB) comprise a same polarity. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figure 7 of Banik to use the clock restructuring circuitry (14, 12, 10) as taught in Figure 1 of Liu to replace the broad restructuring circuitry (318, 620) for the purpose of generating a differential clock signals so as it can be used in a high-speed system (Liu, Col. 1, lines 17-31). Thus, this combination/modification teaches all the limitations of claim 6 including wherein the selector signal comprises the third clock inverter signal (CLKB).
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Venugopal et al. (USP 11,139,803).
For claim 7, Figure 7 of Banik each teaches all the limitations of this claim including a clock restructuring circuitry (318, 620), wherein the selector signal (output of 318 is a selector for multiplexer 519, 317) comprises the first clock inverter signal (output of 318). Banik does not teach the clock restructuring circuitry comprising: a third clock gate configured to the generate a third clock inverter signal, wherein: the third clock gate is serially coupled to the first and second clock gates; and the first and the third clock inverter signals comprises a same polarity. However, Figure 2 of Venugopal et al. teaches a clock restructuring circuitry (222, 224, 226) comprising: first, second, and third clock gates (222, 224, 226) configured to generate first, second, and third clock inverter signals (CLK_L, CLK2, CLK3_L), wherein: the third clock gate (226) is serially coupled to the first and second clock gates 222, 224); and the first and the third clock inverter signals (CLK_L and CLK3_L) comprises a same polarity. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figure 7 of Banik to use the clock restructuring circuitry (222, 224, 226) as taught in Figure 2 of Venugopal et al. to replace the broad restructuring circuitry (318, 620) for the purpose of achieving a balance of rising and falling edges of the flip-flop (Venugopal et al., Col. 9, lines 4-20). Thus, this combination/modification teaches all the limitations of claim 7.
For claim 16, Figure 7 of Banik each teaches all the limitations of this claim including a clock restructuring circuitry (120) except for the clock restructuring circuitry comprising: first, second, and third clock gates configured to generate first, second, and third clock inverter signals supplied to the slave latch, wherein either: the first, second, and third clock gates are serially coupled; or the first and second clock gates are parallel coupled to the third clock gate. However, Figure 2 of Venugopal et al. teaches a clock restructuring circuitry (222, 224, 226) comprising: first, second, and third clock gates (222, 224, 226) configured to generate first, second, and third clock inverter signals (CLK_L, CLK2, CLK3_L), wherein the first, second, and third clock gates (222, 224, 226) are serially coupled. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figure 7 Banik to use the clock restructuring circuitry (222, 224, 226) as taught in Figure 2 of Venugopal et al. to control the flip-flop for the purpose of achieving a balance of rising and falling edges of the flip-flop (Venugopal et al., Col. 9, lines 4-20).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Banik (USP 5,656,962) in view of Maeno (USP 8,274,319).
For claim 15, Figure 7 of Banik teaches all the limitations of this claim as discussed in the 102 rejection above except for the layout of the circuit wherein “one or more of: a clock signal supplied to the slave latch, a first clock inverter signal supplied to the slave latch, the multiplexer circuitry of the slave latch, and an output buffer coupled to the slave latch are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break”. However, Maeno teaches a flip-flop with a layout wherein one or more of: a clock signal, a first clock inverter signal, the multiplexer circuitry, and an output buffer are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break (see Figures 8-9). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify Figure 7 of the Banik so that the flip-flop has the layout wherein “one or more of: a clock signal supplied to the slave latch, a first clock inverter signal supplied to the slave latch, the multiplexer circuitry of the slave latch, and an output buffer coupled to the slave latch are confined within a first layout region of a floor plan; and the first layout region is separated from a second layout region by a diffusion break”, as taught in Maeno, for the purpose of decreasing the chip size (Maeno, Col. 5, lines 17-30).
Allowable Subject Matter
Claim 20 is allowed.
Claim 20 is allowed because applicant’s argument is found persuasive that the closet prior art of record, Banik (USP 5,656,962), taken alone or in combination, fails to teach or suggest the limitations “wherein: one or more transistor devices of the first and the second latches are activated by the second or the third clock inverter signals; the multiplexer is configured to select between the drive path signal and the storage path signal based on a selector signal; and the selector signal is either a clock signal or the first clock inverter signal” in combination with other limitations as recited therein.
Response to Arguments
Applicant's arguments filed on 05/20/26 have been fully considered but they are not persuasive.
Applicant argues (in “B”) that “ Banik does not disclose a single latch structure in which: a storage path circuitry comprises a storage node configured to retain the output signal, and a drive path circuitry of that same latch is distinct from the storage node. Rather, Banik continues to describe only a storage-oriented slave portion and a separate bypass path external to the slave portion. The clarifying amendment, made herein, therefore directly undercuts the Office Action's repeated rationale that the claims lacked any specific structural relationship”.
However, the above argument is not found persuasive because Banik teaches in Figure 7 “a latch comprising: a drive path circuitry (316-317) configured to transmit an output signal (OUTPUT 208); and a storage path circuitry (313-315, 319, 519, 722) comprising a storage node (input node of 313) configured to retain the output signal (OUTPUT 208); wherein the drive path circuitry (316-317) is distinct from the storage node (input node of 313)”; and that Banik meets all the limitations as recited.
Applicant further argues (in “C”) that “Banik’s bypass path is not distinct-from-storage-node drive path circuitry of the claimed latch. The Office Action continues to map Banik's bypass circuitry (316-317) as the claimed drive path circuitry. However, even if those elements can transmit an output signal, they are not described as a drive path circuitry of a latch that also includes the claimed storage node. Banik's bypass path is structurally separate from the slave storage portion and functions by routing signals around the slave storage portion. That is fundamentally different from the amended claim, which requires a latch having a storage node and a drive path circuitry distinct from that storage node”.
However, this argument is not persuasive because Figure 7 of Banik teaches: a drive path circuitry (316-317) configured to transmit an output signal (OUTPUT 208); and a storage path circuitry (313-315, 319, 519, 722) comprising a storage node (input node of 313) configured to retain the output signal (OUTPUT 208); wherein the drive path circuitry (316-317) is distinct from the storage node (input node of 313).
Applicant further argues (in “D”) that Banik still does not disclose the amended storage-node limitation. The Office Action previously responded that it was "reasonable" to consider Banik's slave-path circuitry as "retaining the output signal". Even if that broad characterization were accepted for prior claim language, it does not satisfy the amended claim, which now expressly requires a storage node comprised by the storage path circuitry. Banik does not identify or even contemplate a storage node of the claimed latch that is structurally distinguished from a drive path circuitry of that same latch in the manner now recited”.
However, this argument is not persuasive because Figure 7 of Banik teaches a latch comprising a drive path circuitry (316-317) configured to transmit an output signal (OUTPUT 208); and a storage path circuitry (313-315, 319, 519, 722) comprising a storage node (input node of 313) configured to retain the output signal (OUTPUT 208); wherein the drive path circuitry (316-317) is distinct from the storage node (input node of 313)”.
Applicant further argues (in “E”) that “Banik's design premise remains the same: speed is obtained by introducing a bypass external to the storage portion, while storage remains in the slave portion. That is inconsistent with amended claim 1, which now expressly requires a storage node within storage path circuitry and a distinct drive path circuitry in the recited latch. The amendment therefore sharpens the distinction previously drawn over Banik”.
However, this argument is not persuasive because Figure 7 of Banik teaches a storage path circuitry (313-315, 319, 519, 722) comprising a storage node (input node of 313), and a the drive path circuitry (316-317) distinct from the storage node (input node of 313)”
Regarding the Inoue’s reference, applicant argues similarly as in Banik that claim 1 now requires: a storage path circuitry comprising a storage node configured to retain the output signal; and a drive path circuitry distinct from the storage node; and that Inoue does not disclose such limitations. However, this argument is not persuasive because Inoue, in Figures 3-4, teaches a latch (102, 307) comprising: a drive path circuitry (318) configured to transmit an output signal (106); and a storage path circuitry (102, 317) comprising a storage node (input of 115) configured to retain the output signal (106), wherein the drive path circuitry (318) is distinct from the storage node (input 115).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-8101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842
Prosecution Insights