DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 5/27/2026 have been entered.
Response to Arguments
Applicant’s arguments regarding Claims 1-9 and 13-20 have been fully considered and are persuasive, therefore the prior art rejections of Claims 1-9 and 13-20 have been withdrawn. However, a new ground of rejection, which was necessitated by Applicant’s amendment, has been found and now follows.
In the interests of compact prosecution, the examiner notes that further description of how the gate insulating layer 201 is part of the photoelectric sensing elements and is also part of the wall structure, as shown in Fig 1 of the instant application would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 15-16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0019009) in view of Lin et al (US 2021/0057607), and in further view of Luo et al (CN 215644493U).
Regarding Claim 1, Wu et al discloses
a photoelectric sensor (photoelectric sensor [0005] shown in Fig 1a), comprising:
a substrate (image identification chip 7 [0052]);
a plurality of photoelectric sensing elements (optical channels 2 [0051]) arranged at a side of the substrate (7); and
at least one wall structure (shown in annotated Fig 1a), wherein one wall structure (shown in annotated Fig 1a) of the at least one wall structure (shown in annotated Fig 1a) is located between two adjacent photoelectric sensing elements (2) of the plurality of photoelectric sensing elements (2) and comprises a first layer (body 1 [0051] inner portion shown in annotated Fig 1a) and a second layer (first light processing layer 5 [0079]) that are stacked together,
wherein the first layer (inner portion 1) is arranged at a side of the second layer (5) away from the substrate (7) and comprises a light-blocking material (first light processing layer 5 may be a light blocking layer made from opaque materials [0090]).
PNG
media_image1.png
686
1103
media_image1.png
Greyscale
Wu et al does not directly disclose
wherein at least one of the first layer or the second layer of the wall structure is arranged in a same layer as at least one layer of one photoelectric sensing element of the plurality of photoelectric sensing elements,
wherein the photoelectric sensing element comprises
a first gate electrode,
an active layer,
a source electrode, and
a drain electrode.
Lin et al, in the related art of semiconductor devices that include photoelectric sensors, discloses
wherein at least one of the first layer (middle portion of 850 [0801] and wall portion of permanent substrate 820 [0799] shown in annotated Fig 9-15) or the second layer of the wall structure (850 [0801] Fig 9-15) is arranged in a same layer (layer 820 [0799] Fig 9-15) as at least one layer of one photoelectric sensing element (shown in annotated Fig 9-15) of the plurality of photoelectric sensing elements (shown in annotated Fig 9-15).
PNG
media_image2.png
782
1196
media_image2.png
Greyscale
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu et al to include wherein at least one of the first layer or the second layer of the wall structure is arranged in a same layer as at least one layer of one photoelectric sensing element of the plurality of photoelectric sensing elements as taught by Lin et al in order to improve display contrast [0801]. Further, a person of ordinary skill in the art would have recognized that having wall structures located between the photoelectric sensing elements and improving contrast would be advantageous in improving the quality of the image displayed by the device (see MPEP 2143.I(D)).
The combination of Wu et al and Lin et al does not directly disclose
wherein the photoelectric sensing element comprises
a first gate electrode,
an active layer,
a source electrode, and
a drain electrode.
Luo et al, in the related art of semiconductor devices that include optical sensors, discloses
wherein the photoelectric sensing element (element shown in Fig 1) comprises
a first gate electrode (gate layer 20 [page 4, lines 1-11]),
an active layer (amorphous silicon layer 40 [page 4, lines 1-11]),
a source electrode (source/drain layer 60 [page 4, lines 1-11] (left)), and
a drain electrode (source/drain layer 60 [page, lines 1-11] (right)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al and Lin et al to include wherein the photoelectric sensing element comprises a first gate electrode, an active layer, a source electrode, and a drain electrode, as taught by Luo et al in order to improve the light utilization rate [page 4, lines 1-11]. Further, a person of ordinary skill in the art would have recognized that increasing the light utilization rate would increase the light sensitivity of the device [page 4, lines 1-11] (see MPEP 2143.I(D)).
Regarding Claim 2, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 1 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the first gate electrode (20 Luo et al) is arranged at a side of the active layer (40 and 50 Luo et al) close to the substrate (substrate 10 [page 4, lines 1-11] Luo et al), and the source electrode (60 (left) Luo et al) and the drain electrode (60 right Luo et al) are arranged at a side of the active layer (40 Luo et al) away from the substrate (10 Luo et al); and
wherein the first layer (inner portion 1 Wu et al) of the wall structure (shown above in annotated Fig 1a Wu et al) is arranged in a same layer (layer 820 [0799] Fig 9-15 Lin et al) as at least one of the first gate electrode (20 Luo et al), the source electrode (60 (left) Luo et al), or the drain electrode (60 (right) Luo et al).
Regarding Claim 3, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 2 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the second layer (5 Fig 1a Wu et al) of the wall structure (shown above in annotated Fig 1a Wu et al) is arranged in a same layer as the active layer (40 Fig 1 Luo et al).
Regarding Claim 4, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 2 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
further comprising: a first insulation layer (top gate insulating layer 30 [page 4, lines 1-11] Luo et al) arranged at a side of the first gate electrode (20 Luo et al) close to the substrate (10 Luo et al), wherein the second layer (5 Fig 1a Wu et al) of the wall structure (shown above in annotated Fig 1a Wu et al) is arranged in a same layer as the first insulation layer (30 Luo et al).
Regarding Claim 5, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 3 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the photoelectric sensing element (element shown in Fig 1 Luo et al) further comprises a gate insulation layer (top gate insulating layer 30 [page 3, lines 23-25] Luo et al), wherein at least part of the gate insulation layer (30 Luo et al) is arranged between the first gate electrode (gate layer 20 [page 4, lines 1-11] Luo et al) and the active layer (amorphous silicon layer 40 [page 4, lines 1-11] Luo et al), the gate insulation layer (30 Luo et al) comprises a first opening (area where the wall (shown above in annotated Fig 1a Wu et al) is located) in which one wall structure of the at least one wall structure (shown above in annotated Fig 1a Wu et al) is located.
Regarding Claim 6, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 3 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the wall structure (shown above in annotated Fig 1a Wu et al) further comprises a third layer (third light processing layer 4 [0085] Fig 1a Wu et al) arranged at a side of the second layer (5 Wu et al) close to the substrate (image identification chip 7 [0052] Wu et al) and arranged in a same layer as the first gate electrode (20 Luo et al).
Regarding Claim 7, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 6 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the third layer (4 Fig 1a Wu et al) is electrically insulated (insulated by the gate insulating layer 30 Luo et al) from the first gate electrode (20 Fig 1 Luo et al).
Regarding Claim 8, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 6 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the first layer (inner portion 1 Wu e t al) and the third layer (4 Wu et al) of the wall structure (shown above in annotated Fig 1a Wu et al) are in contact with each other and connected to each other.
Regarding Claim 15, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 2 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the photoelectric sensing element (element shown in Fig 1 Luo et al) further comprises a connection layer (n-type amorphous silicon layer 50 [page 4, lines 1-11] Fig 1 Luo et al) located at a side of the source electrode (source/drain layer 60 [page 4, lines 1-11] (left) Fig 1 Luo et al) and the drain electrode (source/drain layer 60 [page, lines 1-11] (right) Fig 1 Luo et al) close to the active layer (40 Fig 1 Luo et al); and
wherein the wall structure (shown above in annotated Fig 1a Wu et al) further comprises a fourth layer (outer portion Fig 1 Wu et al) located between the first layer (1 Wu et al) and the second layer (5 Wu et al), wherein the fourth layer (outer portion 1 shown in annotated Fig 1a Wu et al) and the connection layer (50 Fig 1 Luo et al) are arranged in a same layer.
PNG
media_image3.png
736
1183
media_image3.png
Greyscale
Regarding Claim 16, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 2 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the first layer (inner portion 1 Wu e t al) of the wall structure (shown above in annotated Fig 1a Wu et al) comprises a first surface (top surface of layer 1 Fig 1a Wu et al) away from the substrate (image identification chip 7 [0052] Wu et al); and
wherein the active layer (amorphous silicon layer 40 [page 4, lines 1-11] Luo et al) of the photoelectric sensing element (element shown in Fig 1 Luo et al) comprises a center part (shown in annotated Fig 1 Luo et al) and an edge part (shown in annotated Fig 1 Luo et al),
wherein a thickness of the center part (shown in annotated Fig 1 Luo et al) is greater than a thickness of the edge part (shown in annotated Fig 1 Luo et al),
the center part (shown in annotated Fig 1 Luo et al) comprises a second surface (shown in annotated Fig 1 Luo et al) at a side away from the substrate (7 Wu et al), and
a distance H1 between the first surface (shown in annotated Fig 1 Luo et al) and the substrate (7 Wu et al) and a distance H2 between the second surface (shown in annotated Fig 1 Luo et al) and the substrate (7 Wu et al) satisfy: H1≥H2 (shown in annotated Fig 1 Luo et al).
PNG
media_image4.png
874
1045
media_image4.png
Greyscale
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al, Lin et al, and Luo et al to include wherein the distance H1 (distance between the first surface and the substrate) is greater than or equal to H2 (distance between the second surface and the substrate) as taught by Luo et al in order to optimize the location of the grating between the wall structure as to optimize the light path and improve the optical capabilities of the device, and further because it would have been an obvious matter of design choice to optimize the height of the second surface compared to the first surface since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
Regarding Claim 18, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 16 as explained above. The combination of Wu et al, Lin et al, and Luo et al further discloses
wherein the edge part (shown in annotated Fig 1 Luo et al) comprises a third surface (shown in annotated Fig 1 Luo et al) away from the substrate (7 Wu et al), and a distance H3 between the third surface (shown in annotated Fig 1 Luo et al) and the substrate (7 Wu et al) satisfies H1-H2/H2＜H2-H3/H3.
PNG
media_image4.png
874
1045
media_image4.png
Greyscale
Regarding Claim 20, Wu et al discloses an electronic device (electronic terminal [0122] shown in Fig 1a), comprising:
a photoelectric sensor (photoelectric sensor [0005] shown in Fig 1a),
wherein the photoelectric sensor (photoelectric sensor [0005] shown in Fig 1a), comprising:
a substrate (image identification chip 7 [0052]);
a plurality of photoelectric sensing elements (optical channels 2 [0051]) arranged at a side of the substrate (7); and
at least one wall structure (shown in annotated Fig 1a), wherein one wall structure (shown in annotated Fig 1a) of the at least one wall structure (shown in annotated Fig 1a) is located between two adjacent photoelectric sensing elements (2) of the plurality of photoelectric sensing elements (2) and comprises a first layer (body 1 [0051] inner portion shown in annotated Fig 1a) and a second layer (first light processing layer 5 [0079]) that are stacked together,
wherein the first layer (inner portion 1) is arranged at a side of the second layer (5) away from the substrate (7) and comprises a light-blocking material (first light processing layer 5 may be a light blocking layer made from opaque materials [0090]).
PNG
media_image3.png
736
1183
media_image3.png
Greyscale
Wu et al does not directly disclose
wherein at least one of the first layer or the second layer of the wall structure is arranged in a same layer as at least one layer of one photoelectric sensing element of the plurality of photoelectric sensing elements,
wherein the photoelectric sensing element comprises
a first gate electrode,
an active layer,
a source electrode, and
a drain electrode.
Lin et al, in the related art of semiconductor devices that include photoelectric sensors, discloses
wherein at least one of the first layer (middle portion of 850 [0801] and wall portion of permanent substrate 820 [0799] shown in annotated Fig 9-15) or the second layer of the wall structure (850 [0801] Fig 9-15) is arranged in a same layer (layer 820 [0799] Fig 9-15) as at least one layer of one photoelectric sensing element (shown in annotated Fig 9-15) of the plurality of photoelectric sensing elements (shown in annotated Fig 9-15).
PNG
media_image2.png
782
1196
media_image2.png
Greyscale
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu et al to include wherein at least one of the first layer or the second layer of the wall structure is arranged in a same layer as at least one layer of one photoelectric sensing element of the plurality of photoelectric sensing elements as taught by Lin et al in order to improve display contrast [0801]. Further, a person of ordinary skill in the art would have recognized that having wall structures located between the photoelectric sensing elements and improving contrast would be advantageous in improving the quality of the image displayed by the device (see MPEP 2143.I(D)).
The combination of Wu et al and Lin et al does not directly disclose
wherein the photoelectric sensing element comprises
a first gate electrode,
an active layer,
a source electrode, and
a drain electrode.
Luo et al, in the related art of semiconductor devices that include optical sensors, discloses
wherein the photoelectric sensing element (element shown in Fig 1) comprises
a first gate electrode (gate layer 20 [page 4, lines 1-11]),
an active layer (amorphous silicon layer 40 [page 4, lines 1-11]),
a source electrode (source/drain layer 60 [page 4, lines 1-11] (left)), and
a drain electrode (source/drain layer 60 [page, lines 1-11] (right)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al and Lin et al to include wherein the photoelectric sensing element comprises a first gate electrode, an active layer, a source electrode, and a drain electrode, as taught by Luo et al in order to improve the light utilization rate [page 4, lines 1-11]. Further, a person of ordinary skill in the art would have recognized that increasing the light utilization rate would increase the light sensitivity of the device [page 4, lines 1-11] (see MPEP 2143.I(D)).
Claims 9 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0019009) in view of Lin et al (US 2021/0057607), Luo et al (CN 215644493U), and in further view of Cai (US 2023/0180576).
Regarding Claim 9, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 2 as explained above. The combination of Wu et al, Lin et al, and Luo et al does not directly disclose
wherein the plurality of photoelectric sensing elements is arranged in a matrix,
wherein at least two photoelectric sensing elements of the plurality of photoelectric sensing elements are arranged in a first direction, and
at least two photoelectric sensing elements of the plurality of photoelectric sensing elements are arranged in a second direction crossing the first direction, and
wherein the source electrodes of two or more photoelectric sensing elements of the at least two photoelectric sensing elements arranged in the second direction are electrically connected to each other, and
the drain electrodes of two or more photoelectric sensing elements of the at least two photoelectric sensing elements arranged in the second direction are electrically connected to each other.
Cai, in the related art of semiconductor devices that include photoelectric sensing elements, discloses
wherein the plurality of photoelectric sensing elements (photoelectric sensor 100 and pixel units 200 [0101] Fig 4) is arranged in a matrix (shown in Fig 4),
wherein at least two photoelectric sensing elements (100 and 200 Fig 4) of the plurality of photoelectric sensing elements (100 and 200 Fig 4) are arranged in a first direction (horizontal x direction Fig 4), and
at least two photoelectric sensing elements (100 and 200 Fig 4) of the plurality of photoelectric sensing elements (100 and 200 Fig 4) are arranged in a second direction (vertical y direction Fig 4) crossing the first direction (horizontal x direction Fig 4), and
wherein the source electrodes (source 40 [0105] Fig 5) of two or more photoelectric sensing elements (100 and 200 Fig 4) of the at least two photoelectric sensing elements (100 and 200 Fig 4) arranged in the second direction (vertical y direction Fig 4) are electrically connected to each other (shown in the combination of Fig 4 and Fig 5 with second electrode 160 as a common electrode), and
the drain electrodes (drain 50 [0105] Fig 5) of two or more photoelectric sensing elements (100 and 200 Fig 4) of the at least two photoelectric sensing elements (100 and 200 Fig 4) arranged in the second direction (vertical y direction Fig 4) are electrically connected to each other (shown in the combination of Fig 4 and Fig 5 with second electrode 160 as a common electrode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al, Lin et al, and Luo to include wherein the photoelectric sensing elements are arranged in a matrix and the source and drain electrodes of the elements are electrically connected to each other as taught by Cai in order to improve the electrical functioning as well as the type of functioning of the device. Further, a person of ordinary skill in the art would have recognized that having more photoelectric sensors arranged in different direction would improve the electrical and optical functioning of the device (see MPEP 2143.I(D)).
Regarding Claim 13, the combination of Wu et al, Lin et al, Luo et al, and Cai discloses the limitations of claim 9 as explained above. The combination of Wu et al, Lin et al, Luo et al, and Cai further discloses
wherein the at least one wall structure (shown above in annotated Fig 1a Wu et al) comprises a plurality of first wall structures (wall structures shown above in annotated Fig 1a Wu et al) and a plurality of second wall structures (wall structures shown above in annotated Fig 1a Wu et al),
wherein the plurality of first wall structures (shown above in annotated Fig 1a Wu et al) is arranged along the second direction (vertical y direction Fig 4 Cai), and
the plurality of second wall structures (shown above in annotated Fig 1a Wu et al) is arranged along the first direction (horizontal x direction Fig 4 Cai); and
wherein one first wall structure (shown above in annotated Fig 1a Wu et al) of the plurality of first wall structures (shown above in annotated Fig 1a Wu et al arranged in the vertical y direction Fig 4 Cai) comprises the first layer (inner portion 1 shown above in annotated Fig 1a Wu et al), and
one second wall structure (shown above in annotated Fig 1a Wu et al) of the plurality of second wall structures (shown above in annotated Fig 1a Wu et al arranged in the horizontal x direction Fig 4 Cai) comprises the first layer,
wherein the first layer (inner portion 1 shown above in annotated Fig 1a Wu et al) of the first wall structure (shown above in annotated Fig 1a Wu et al) and the first gate electrode (20 Luo et al) of the photoelectric sensing element (element shown in Fig 1 Luo et al) are arranged in a same layer, and
the first layer (inner portion 1 shown above in annotated Fig 1a Wu et al) of the second wall structure (shown above in annotated Fig 1a Wu et al) and the source electrode (60 (left) Luo et al) and the drain electrode (60 (right) Luo et al) of the photoelectric sensing element (element shown in Fig 1 Luo et al) are arranged in a same layer.
Regarding Claim 14, the combination of Wu et al, Lin et al, Luo et al, and Cai discloses the limitations of claim 13 as explained above. The combination of Wu et al, Lin et al, Luo et al, and Cai further discloses
wherein the second wall structure (shown above in annotated Fig 1a Wu et al) is provided between two photoelectric sensing elements (element shown in Fig 1 Luo et al) of the plurality of photoelectric sensing elements (element shown in Fig 1 Luo et al) that are adjacent to each other in the first direction (horizontal direction Fig 4 Cai),
the source electrode (60 (left) Luo et al) of one of the two photoelectric sensing elements (element shown in Fig 1 Luo et al) is adjacent to the second wall structure (shown above in annotated Fig 1a Wu et al), and
the drain electrode (60 (right) Luo et al) of another one of the two photoelectric sensing elements (element shown in Fig 1 Luo et al) is adjacent to the second wall structure (shown above in annotated Fig 1a Wu et al); and
wherein a minimum distance (square matrix shown in Fig 4 Cai) between the second wall structure (shown above in annotated Fig 1a Wu et al) and the source electrode (60 (left) Luo et al) of the one of the two photoelectric sensing elements (element shown in Fig 1 Luo et al) is equal to a minimum distance (square matrix shown in Fig 4 Cai) between the second wall structure (shown above in annotated Fig 1a Wu et al) and the drain electrode (60 (right) Luo et al) of the another one of the two photoelectric sensing elements (element shown in Fig 1 Luo et al).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0019009) in view of Lin et al (US 2021/0057607), Luo et al (CN 215644493U), and in further view of Yu (US 2020/0176506).
Regarding Claim 17, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 16 as explained above. The combination of Wu et al, Lin et al, and Luo et al does not directly disclose
wherein H1-H2≤1 μm.
Yu, in the related art of semiconductor devices that include photoelectric devices, discloses
wherein a distance between an edge of the orthographic projection of the transparent electrode (303 [0036] Fig 3) on the base substrate (100 [0036] Fig 3) and an edge of the orthographic projection of the photosensitive layer (photoelectric layer [0036] Fig 3) on the base substrate (100) is 1-3 microns [0011].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al, Lin et al, and Luo et al to include wherein H1-H2≤1 μm as taught by Yu in order to meet small size design requirements [0039] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that having a small photoelectric sensor would be advantageous in allowing more sensors in a small amount of space which would increase the photo sensing functional capability of the device (see MPEP 2143.I(D)).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2019/0019009) in view of Lin et al (US 2021/0057607), and Luo et al (CN 215644493U), and in further view of Gu et al (CN 108847417).
Regarding Claim 19, the combination of Wu et al, Lin et al, and Luo et al discloses the limitations of claim 1 as explained above. The combination of Wu et al, Lin et al, and Luo et al does not disclose
wherein an included angle a between a side surface of the second layer of the wall structure and a plane of the substrate satisfies 40°≤a≤50°.
Gu et al, in the related art of semiconductor devices that include image sensors, discloses
wherein an included angle a (shown in annotated Fig 3) between a side surface of the second layer (dielectric material 212 [page 7, lines 8-26] Fig 3) of the wall structure (shown in Fig 3) and a plane of the substrate (substrate 20 [page 7, lines 8-26] Fig 3) satisfies 45°≤ a≤ 90°.
PNG
media_image5.png
644
1070
media_image5.png
Greyscale
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wu et al, Lin et al, and Luo et al to include wherein an included angle a between a side surface of the second layer of the wall structure and a plane of the substrate satisfies 40°≤a≤50° as taught by Gu et al in order to increase the incident light that is reflected on the side wall so as to further improve the sensitivity and may also reduce crosstalk [page 6, lines 1-23] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further it would have been an obvious matter of design choice to optimize the shape of the wall since such a modification would have involved a mere change in shape of the component. A change in shape is generally recognized as being within the level of ordinary skill in the art In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(B).
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10:
Regarding Claim 10, the combination of Wu et al, Luo et al, and Cai discloses the limitations of claim 9 as explained above.
The reason for the indication of allowability of Claim 10 is the inclusion of
wherein the first layer of the wall structure is arranged in a same layer as the source electrode and the drain electrode of the photoelectric sensing element, and the at least one wall structure comprises a plurality of first wall structures arranged along the second direction; and wherein one first wall structure of the plurality of first wall structures comprises a first part and a second part, the first layer of the first wall structure of at the first part is electrically connected to the source electrode of one photoelectric sensing element of the plurality of photoelectric sensing elements adjacent to the first part, and the first layer of the first wall structure of at the second part is electrically connected to the drain electrode of one photoelectric sensing element of the plurality of photoelectric sensing elements adjacent to the second part, and wherein the first part and the second part are spaced apart from each other in at least one of the first direction or the second direction.
Specifically, the combination of Wu et al, Luo et al, and Cai does not teach the above features in accordance with the instant application disclosure according to Fig 11 of the instant application, i.e. the first part of the wall and the second part of the wall are not disclosed in the combination as being position in a plan view as shown in annotated Fig 11.
PNG
media_image6.png
634
692
media_image6.png
Greyscale
Further, should a new reference be found that discloses the above limitation, it would not be obvious to a person of ordinary skill in the art to make this modification to the combination of Wu et al, Luo et al, and Cai.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 11 would be allowable based on its dependency on Claim 10.
Claim 12 would be allowable based on its dependency on Claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li et al (US 2019/0252456) which discloses photoelectric sensing technology [0039], and Huang (US 2023/0007991) which discloses a photosensor [0010].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights