DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka et al. (US 2024/02555357) (hereinafter Tomioka) in view of Yeom et al. (US 2019/0353532) (hereinafter Yeom).
Regarding claim 1, Tomioka teaches a temperature sensor, comprising: a temperature detection diode (15), disposed at a position having a target temperature and inserted into a target path between a first node and a second node (see Fig. 1); a current supply circuit (11,12), configured to supply a first evaluation current, a second evaluation current and a third evaluation current to the target path in a forward direction of the temperature detection diode at different timings (see paragraphs 0030-0031 and 0052); a voltage detection circuit (voltmeter), configured to detect a voltage when the first evaluation current, the second evaluation current and the third evaluation current are respectively supplied to the target path as a first evaluation voltage, a second evaluation voltage and a third evaluation voltage (see paragraph 0026-0027 and 0052); and an arithmetic circuit (200), configured to detect the target temperature based on the first evaluation voltage, the second evaluation voltage and the third evaluation voltage (see Figure 1 and paragraphs 0026-0027, 0034 and 0052).
However, Tomioka does not explicitly teach a voltage detection circuit voltmeter, configured to detect a voltage between the first node and the second node.
Yeom teaches a voltage detection circuit, configured to detect a voltage between the first node and the second node (see paragraphs 0003-0005).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to configure the voltage detection circuit as taught by Tomioka to detect a voltage between the first node and the second node as taught by Yeom. One would be motivated to make this combination in order to provide an alternative way to measure temperature by providing a predictable transfer junction that is dependent on temperature.
Regarding claim 2, Tomioka as modified by Yeom teaches all the limitations of claim 1, Tomioka further teaches wherein the arithmetic circuit (200) is configured to detect the target temperature by subtracting the first evaluation voltage, the second evaluation voltage and the third evaluation voltage according to a predetermined calculation formula based on a relationship among the first evaluation current, the second evaluation current and the third evaluation current (difference between forward voltages) (see equation 6 when using three currents as described in paragraph 0052) (see paragraphs 0026-0027, 0033-0038).
Regarding claim 3, Tomioka as modified by Yeom teaches all the limitations of claim 2, Tomioka further teaches the calculation formula is formula (2), the arithmetic circuit (200) is configured to derive ∆VF according to formula (2), and generate a temperature detection signal according to a derivation result of ∆VF, If1, If2, If3 represent the first, second, and third evaluation currents, respectively, VF1, VF2, and VF3 represent the first, second, and third evaluation voltages (see equation 6 when solved for three currents as describe in paragraph 0052) (see paragraph 0026-0027, 0034-0038).
However, Tomioka as modified by Yeom does not explicitly teach wherein each of the first evaluation current, the second evaluation current and the third evaluation current is set to satisfy formula (1), respectively, each of k1, k2 and k3 represents an integer equal to or greater than 1, and
k3 x If3 = k1 x If1 + k2 x If2 (1)
Yeom teaches teach wherein each of the first evaluation current, the second evaluation current and the third evaluation current is set to satisfy formula (1), respectively, each of k1, k2 and k3 represents an integer equal to or greater than 1, and k3 x If3 = k1 x If1 + k2 x If2 (1) (see paragraph 0038 when If1=1X, If2= 2X, If3=3X and K1=1, k2=1, k3 =1).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the first evaluation current, the second evaluation current and the third evaluation current as taught by Tomioka to satisfy formula (1), respectively, each of k1, k2 and k3 represents an integer equal to or greater than 1, and k3 x If3 = k1 x If1 + k2 x If2 (1) as taught by Yeom. One would be motivated to make this combination in order to provide an accurate temperature measurement by canceling base resistance errors in the temperature sensor.
Regarding claim 4, Tomioka as modified by Yeom teaches all the limitations of claim 3, Tomioka further teaches the current supply circuit is configured to perform a first supply operation of supplying the first evaluation current to the temperature detection diode k1 times, perform a second supply operation of supplying the second evaluation current to the temperature detection diode k2 times, and perform a third supply operation of supplying the third evaluation current to the temperature detection diode k3 times, the voltage detection circuit is configured to obtain k1 detected values of the first evaluation voltage by detecting the first evaluation voltage each time upon the first supply operation, obtain k2 detected values of the second evaluation voltage by detecting the second evaluation voltage each time upon the second supply operation, and obtain k3 detected values of the third evaluation voltage by detecting the third evaluation voltage every time upon the third supply operation, and the arithmetic circuit (200) is configured to derive ∆VF using k1 detected values for the first evaluation voltage, k2 detected values for the second evaluation voltage and k3 detected values for the third evaluation voltage based on formula (2) (see equation 6 when K1=1, k2=1, k3=1 and solved for three currents as described in paragraph 0052).
Regarding claim 5, Tomioka as modified by Yeom teaches all the limitations of claim 4, Tomioka further teaches ∆VF satisfies formula (3),
PNG
media_image1.png
65
514
media_image1.png
Greyscale
KB represents Boltzmann constant, q represents amount of charge of electrons, TD represents the target temperature, and
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media_image2.png
64
568
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Greyscale
(see Formulas 1-6; paragraphs 0034-0038 when solve for three currents as disclosed in paragraph 0052).
Regarding claim 7, Tomioka as modified by Yeom teaches all the limitations of claim 1, and further teaches wherein the current detection circuit includes an A/D converter (106), the A/D converter (106) is configured to, by analog/digital converting the voltage between the first node and the second node when the first evaluation current, the second evaluation current and the third evaluation current are supplied to the temperature detection diode, generate a first digital detection value, a second digital detection value and a third digital detection value respectively representing detected values of the first evaluation voltage, the second evaluation voltage and the third evaluation voltage, and the arithmetic circuit (112) is configured to detect the target temperature based on the first digital detection value, the second digital detection value and the third digital detection value (see Yeom; Figure 1 and paragraph 0027).
Regarding claim 8, Tomioka as modified by Yeom teaches all the limitations of claim 2, and further teaches wherein the current detection circuit includes an A/D converter (106), the A/D converter (106) is configured to, by analog/digital converting the voltage between the first node and the second node when the first evaluation current, the second evaluation current and the third evaluation current are supplied to the temperature detection diode, generate a first digital detection value, a second digital detection value and a third digital detection value respectively representing detected values of the first evaluation voltage, the second evaluation voltage and the third evaluation voltage, and the arithmetic circuit (112) is configured to detect the target temperature based on the first digital detection value, the second digital detection value and the third digital detection value (see Yeom; Figure 1 and paragraph 0027).
Regarding claim 9, Tomioka as modified by Yeom teaches all the limitations of claim 3, and further teaches wherein the current detection circuit includes an A/D converter (106), the A/D converter (106) is configured to, by analog/digital converting the voltage between the first node and the second node when the first evaluation current, the second evaluation current and the third evaluation current are supplied to the temperature detection diode, generate a first digital detection value, a second digital detection value and a third digital detection value respectively representing detected values of the first evaluation voltage, the second evaluation voltage and the third evaluation voltage, and the arithmetic circuit (112) is configured to detect the target temperature based on the first digital detection value, the second digital detection value and the third digital detection value (see Yeom; Figure 1 and paragraph 0027).
Regarding claim 10, Tomioka as modified by Yeom teaches all the limitations of claim 4, and further teaches wherein the current detection circuit includes an A/D converter (106), the A/D converter (106) is configured to, by analog/digital converting the voltage between the first node and the second node when the first evaluation current, the second evaluation current and the third evaluation current are supplied to the temperature detection diode, generate a first digital detection value, a second digital detection value and a third digital detection value respectively representing detected values of the first evaluation voltage, the second evaluation voltage and the third evaluation voltage, and the arithmetic circuit (112) is configured to detect the target temperature based on the first digital detection value, the second digital detection value and the third digital detection value (see Yeom; Figure 1 and paragraph 0027).
Regarding claim 11, Tomioka as modified by Yeom teaches all the limitations of claim 1, Tomioka further teaches wherein the arithmetic circuit (200) is configured to generate a temperature detection signal indicating a detection result of the target temperature (see paragraphs 0034).
Regarding claim 12, Tomioka as modified by Yeom teaches all the limitations of claim 2, Tomioka further teaches wherein the arithmetic circuit (200) is configured to generate a temperature detection signal indicating a detection result of the target temperature (see paragraphs 0034).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Yeom and in further view of Tustaniwskyj et al. (US 2011/0013670) (hereinafter Tustaniwskyj).
Regarding claim 13, Tomioka as modified by Yeom teaches all the limitations of claim 1.
However, Tomioka as modified by Yeom does not explicitly teach the target path includes a resistive component, and each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component.
Tustaniwskyj teaches the target path includes a resistive component (306), and evaluation current passes through the temperature detection diode (308) and the resistive component (306) (see Figure 3 and paragraph 0035).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to been obvious to one with ordinary skill in the art to provide the temperature detection diode as taught by the prior combination wherein the target path includes a resistive component as taught by Tustaniwskyj such that each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component. One would be motivated to make this combination in order to provide a more accurate temperature detection.
Regarding claim 14, Tomioka as modified by Yeom teaches all the limitations of claim 2.
However, Tomioka as modified by Yeom does not explicitly teach the target path includes a resistive component, and each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component.
Tustaniwskyj teaches the target path includes a resistive component (306), and evaluation current passes through the temperature detection diode (308) and the resistive component (306) (see Figure 3 and paragraph 0035).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to been obvious to one with ordinary skill in the art to provide the temperature detection diode as taught by the prior combination wherein the target path includes a resistive component as taught by Tustaniwskyj such that each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component. One would be motivated to make this combination in order to provide a more accurate temperature detection.
Regarding claim 15, Tomioka as modified by Yeom teaches all the limitations of claim 3.
However, Tomioka as modified by Yeom does not explicitly teach the target path includes a resistive component, and each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component.
Tustaniwskyj teaches the target path includes a resistive component (306), and evaluation current passes through the temperature detection diode (308) and the resistive component (306) (see Figure 3 and paragraph 0035).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to been obvious to one with ordinary skill in the art to provide the temperature detection diode as taught by the prior combination wherein the target path includes a resistive component as taught by Tustaniwskyj such that each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component. One would be motivated to make this combination in order to provide a more accurate temperature detection.
Regarding claim 16, Tomioka as modified by Yeom teaches all the limitations of claim 4.
However, Tomioka as modified by Yeom does not explicitly teach the target path includes a resistive component, and each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component.
Tustaniwskyj teaches the target path includes a resistive component (306), and evaluation current passes through the temperature detection diode (308) and the resistive component (306) (see Figure 3 and paragraph 0035).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to been obvious to one with ordinary skill in the art to provide the temperature detection diode as taught by the prior combination wherein the target path includes a resistive component as taught by Tustaniwskyj such that each of the first evaluation current, the second evaluation current and the third evaluation current passes through the temperature detection diode and the resistive component. One would be motivated to make this combination in order to provide a more accurate temperature detection.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Yeom and in further view of Sato et al. (US 2019/0113393) (hereinafter Sato).
Regarding claim 17, Tomioka as modified by Yeom teaches all the limitations of claim 1.
However, Tomioka as modified by Yeom does not explicitly teach wherein the temperature detection diode is formed by a bipolar transistor having a collector and a base connected to the collector.
Sato teaches the temperature detection diode is formed by a bipolar transistor (206) having a collector and a base connected to the collector (see Figure 7 and paragraphs 0017, 0044-0045).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify the temperature detection diode as taught by the prior combination with a bipolar transistor having a collector and a base connected to the collector as taught by Sato. One would be motivated to make this combination in order to provide a temperature sensing element that is low-cost, widely available and provide a linear temperature response.
Regarding claim 18, Tomioka as modified by Yeom teaches all the limitations of claim 2.
However, Tomioka as modified by Yeom does not explicitly teach wherein the temperature detection diode is formed by a bipolar transistor having a collector and a base connected to the collector.
Sato teaches the temperature detection diode is formed by a bipolar transistor (206) having a collector and a base connected to the collector (see Figure 7 and paragraphs 0017, 0044-0045).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify the temperature detection diode as taught by the prior combination with a bipolar transistor having a collector and a base connected to the collector as taught by Sato. One would be motivated to make this combination in order to provide a temperature sensing element that is low-cost, widely available and provide a linear temperature response.
Regarding claim 19, Tomioka as modified by Yeom teaches all the limitations of claim 3.
However, Tomioka as modified by Yeom does not explicitly teach wherein the temperature detection diode is formed by a bipolar transistor having a collector and a base connected to the collector.
Sato teaches the temperature detection diode is formed by a bipolar transistor (206) having a collector and a base connected to the collector (see Figure 7 and paragraphs 0017, 0044-0045).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify the temperature detection diode as taught by the prior combination with a bipolar transistor having a collector and a base connected to the collector as taught by Sato. One would be motivated to make this combination in order to provide a temperature sensing element that is low-cost, widely available and provide a linear temperature response.
Regarding claim 20, Tomioka as modified by Yeom teaches all the limitations of claim 3.
However, Tomioka as modified by Yeom does not explicitly teach wherein the temperature detection diode is formed by a bipolar transistor having a collector and a base connected to the collector.
Sato teaches the temperature detection diode is formed by a bipolar transistor (206) having a collector and a base connected to the collector (see Figure 7 and paragraphs 0017, 0044-0045).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify the temperature detection diode as taught by the prior combination with a bipolar transistor having a collector and a base connected to the collector as taught by Sato. One would be motivated to make this combination in order to provide a temperature sensing element that is low-cost, widely available and provide a linear temperature response.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, The closest prior art alone or in combination fails to teach or render obvious the specific limitation of derive (M×∆VF) using (M×k1) detected values for the first evaluation voltage, (M×k2) detected values for the second evaluation voltage and (M×k3) detected values for the third evaluation voltage based on formula (2), and generate the temperature detection signal according to a derivation result of (M×∆VF), in which M represents an integer equal to or greater than 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M SOTO whose telephone number is (571)270-7707. The examiner can normally be reached M-F 8:00am-4:00pm.
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/JANICE M SOTO/ Examiner, Art Unit 2855
/JOHN E BREENE/ Supervisory Patent Examiner, Art Unit 2855
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