DETAILED ACTION
The following claims are pending in this office action: 1-19
Claims 1, 9 and 16 are independent claims.
2. The following claims are amended: 1, 4, 9, 13 and 16
3. The following claims are new: -
4. The following claims are cancelled: -
5. Claims 1-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Previous Rejections and/or Objections Withdrawn
The objections to claims 13 and 16-18 are withdrawn based on the amendments.
Allowable Subject Matter
Claims 16-19 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) (and in the case of claim 19, the objection) set forth in this Office action.
RESPONSE TO ARGUMENTS
Applicant’s arguments in the amendment filed 03/20/2026 have been fully considered but are moot in view of new grounds of rejection.
Applicant notes: Independent claim 1 is amended to recite “that the indirection pointer table contains mappings of address sets to one or more cache sets, and that the pointer table engine updates individual entries in the indirection pointer table by replacing a mapping in the indirection pointer table with a new mapping selected from the freelist of pointers.” This limitation is disclosed by the combination of Qureshi (US Pub. 2021/0336763), Matsuo (US Pub. 2017/0185520), and Duggal (US Pub. 2021/0064376) as explained below and rejected accordingly.
Independent claim 9 is amended in a similar way to claim 1. The amended limitations are disclosed by Qureshi (US Pub. 2021/0336763), Matsuo (US Pub. 2017/0185520), and Duggal (US Pub. 2021/0064376) as explained below and rejected accordingly.
Dependent claims 2-8 and 10-15 depend on independent claims 1 and 9. The amended elements in the claims are disclosed by Qureshi (US Pub. 2021/0336763), Matsuo (US Pub. 2017/0185520), and Duggal (US Pub. 2021/0064376) as explained below, and so any additional features to the dependent claims are rejected accordingly.
Applicant also argues that the Specification and Drawings of the application fully disclose the corresponding structure of the pointer table engine as well as algorithmic steps for how said engine updates the indirection pointer table using the freelist of pointers and pointer indirection. As support, applicant points to para. 0012 that the engine is controller/microcode implemented control logic anchoring the claimed engine to processor and cache-controller hardware structure. Furthermore, Applicant explains that the application discloses registers and tables for the pointer engine.
Merely referencing a specialized computer (e.g., a “bank computer”), some undefined component of a computer system (e.g., “access control manager”), “logic,” “code,” or elements that are essentially a black box designed to perform the recited function, will not be sufficient because there must be some explanation of how the computer or the computer component performs the claimed function” ... “if there is no corresponding structure disclosed in the specification (i.e., the limitation is only supported by software and does not correspond to an algorithm and the computer or microprocessor programmed with the algorithm), the limitation should be deemed indefinite as discussed above, and the claim should be rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See MPEP § 2181.
Nothing in the specification (aside from the means plus function claiming) indicates that the engine is hardware. Particularly, nothing in the paragraphs recited by the applicant recites that the engine is a “system cache controller” and “microcode implemented control logic.” Instead that the controller comprises, or includes as an element, the pointer table engine. In fact, para. 14 contains: “a system cache controller further comprising instructions that implement the pointer table engine.” A person of ordinary skill in the art viewing the specification would understand that that the pointer table engine is intended to be software only, and “does not correspond an algorithm and the computer or the microprocessor programmed with the algorithm.” Here, the applicant appears to use “pointer table engine” as a black box hardware component designed to perform the function, without indicating the hardware component. As such, Applicant’s argument is not persuasive.
Applicant makes also arguments characterizing Qureshi as “with occurring though re-encryption and simultaneous relocation of all cache lines” and that “Qureshi operates on the principle of deterministic redirection of a set of physical line addresses in a cache to a set of encrypted line address in the cache using an encryption key”, noting “the teachings of the references are not sufficient to render the claims prima facie obvious.”
If an applicant disagrees with any factual findings by the Office, an effective traverse of a rejection based wholly or partially on such findings must include a reasoned statement explaining why the applicant believes the Office has erred substantively as to the factual findings. A mere statement or argument that the Office has not established a prima facie case of obviousness will not be considered substantively adequate to rebut the rejection or an effective traverse of the rejection under 37 CFR 1.111(b). See MPEP §2141. The Patent and Trademark Office determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction "in light of the specification as it would be interpreted by one of ordinary skill in the art." In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364[, 70 USPQ2d 1827, 1830] (Fed. Cir. 2004). Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim.” See MPEP 2111.
Here, as explained in the rejection below, Qureshi does not operate on a simple deterministic redirection of a set of PLAs to a set of ELAs simultaneously. Each individual or set of PLAs may be redirected to a different individual ELA or set of ELAs using different keys. In particular para. 0061 states: “The avalanche effect of encryption would cause lines that have some spatial correlation in the PAS (physical address space) to get scattered through the space in EAS (encrypted address space), thus breaking the correlation present ... This scattering would happen in an unpredictable fashion ... For example, lines A and E were mapped to the same set in FIG. 1a, however, in FIG. 3, A and E can be mapped to different sets, and for another key they would get mapped to some other sets [of caches].” Furthermore, Fig. 7 clearly shows mapping of the addresses/set of addresses to different caches over time. Although the ELA can only be visible to the LLC, there is no requirement that a freelist, such as those described in Quershi or Duggal, cannot be used as another step in replacing the mapping, for example, by maintaining a plurality or “freelist” of keys/pointers for replacing the keys/pointers used for encryption/mapping for the benefits recited below. As Applicant mistakes the operation of Qureshi, the arguments that a prima facie case of obviousness is not established/ that the proposed modification is improper as it would change the principle of operation of Qureshi is not persuasive.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 1-19 invokes 112(f).
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder (engine) that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations include: a pointer table engine configured to update/for updating ... (claims 1, 7 and 8); update an individual mapping in the indirection pointer table by a pointer table engine (claims 9, 13 and 15); pointer table engine to initialize an indirection pointer table and determine that the cache request does/does not correspond to a cache miss (claim 16); and point table engine for updating said indirection pointer table (claim 19).
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The instant specifications are silent to the corresponding structure as to how the engine is to perform the functions as described. A description of the outcome of the claimed functions is not a description of the structure.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claim 19 are objected to because of the following informalities:
Claim 19 recites the limitation “said pointer table engine for updated said indirection pointer table” (claim 19, ln. 1-2). Although the pointer table engine has antecedent basis in claim 16, it is not recited to perform the function of “updating said indirection pointer table” in claim 16 and so the phrasing is unclear. Additionally, this appears to be a typo as the other independent claims recites the pointer table engine performing this function. Examiner suggests also including this function in claim 16.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
With respect to claims 1-19 the claim limitations a pointer table engine configured to update/for updating ... (claims 1, 7 and 8); update an individual mapping in the indirection pointer table by a pointer table engine (claims 9, 13 and 15); pointer table engine to initialize an indirection pointer table and determine that the cache request does/does not correspond to a cache miss (claim 16); and point table engine for updating said indirection pointer table (claim 19) invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is silent as to the corresponding structure of the engine recited in the claims. Therefore, the claims 1-19 are indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-9, 11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Qureshi (US Pub. 2021/0336763) (hereinafter “Qureshi”) in view of Matsuo (US Pub. 2017/0185520) (hereinafter “Matsuo”) and in view of Duggal (US Pub. 2021/0064376) (hereinafter “Duggal”).
As per claim 1, Qureshi teaches a system for defending against contention side-channel cache attacks, comprising: ([Qureshi, para. 0007] “The present disclosure relates generally to systems and methods for preventing side-channel attacks ... in a cache”)
one or a plurality of processors; ([Qureshi, para. 0055] “Modern computers use caches to bridge the long latency between the fast processor and slow memory”; [para. 0100] “a request can be received to access a first memory line ... The request can come from different components, such as ... one or more processors)
at least one cache in communication with at least one of said processors; ([Qureshi, para. 0055; Fig. 1a] “computers use caches to bridge the long latency between the fast processor and slow memory, as shown in FIG. 1a”)
a system cache controller; ([Qureshi, para. 0017-0018] “provide a system ... the system comprising: ... a processor [system cache controller] comprising: a plurality of cores; and a cache comprising a plurality of cache locations shared between the plurality of cores... wherein the processor executes one or more instructions that cause ... the system to transmit data stored at the ... cache”; the processor is a cache controller as it controls functions associated with the cache)
an indirection pointer table containing mappings of address sets to one or more cache sets; ([Qureshi, Fig. 3; para. 0061] “randomized mapping [an indirection pointer table] of memory lines to cache locations can be accomplished efficiently by operating the cache on an Encrypted Address Space (EAS) instead of the Physical Address Space (PAS), as shown in FIG. 3 ... encryption would cause lines that have some spatial correlation in the PAS ... such as those mapping to the same set of the cache [cache sets] to get scattered throughout [indirection] the space in EAS”; [para. 0062] “CEASE can employ a block cipher, such as Low-Latency Block-Cipher (LLBC), to convert the b-bit Physical Line-Address (PLA) [containing mappings of address sets] into a b-bit Encrypted Line-Address (ELA) and uses this ELA to access the cache [to one or more cache sets]”; [para. 0059] the randomized mapping is a table as it stores the location of the line the cache is determined randomly i.e. in a cipher lookup table; [para. 0061] the mapping is an indirection as it happens in an unpredictable fashion that misdirects the attacker; [para. 0062] the mapping is a pointer as the encrypted address points to/converts back to the physical address [para. 0098] “respective PLAs of a plurality of PLAs [mappings of address sets] can be mapped to respective cache locations of a plurality of cache locations in a cache [to one or more cache sets]”)
and a pointer table engine configured to update an individual entry in said indirection pointer table by replacing a mapping in the indirection pointer table. ([Qureshi, para. 0073] “the lines ... are changed periodically ... CEASE can use Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping [update an individual entry in said indirection pointer table] the lines [using pointer indirection as the lines ELA are pointers to the physical addresses] based on the new key”; [para. 0109] “the first physical line address [an individual entry in said indirection pointer table] can be converted to a re-encrypted first encrypted line address associated with an updated first encrypted cache location [update an individual entry] using the second key [a remapping/replacing a mapping – see para. 0106: a relocation pointer can be designated to be remapped using the second key ... The relocation pointer can comprise, for example, a cache set]”)
Qureshi does not clearly teach a freelist of pointers corresponding to available cache sets; and update an individual entry in said pointer table by replacing a mapping in the pointer table with a new mapping selected from the freelist of pointers.
However, Matsuo teaches a freelist of pointers corresponding to available cache sets; and ([Matsuo, para. 0041] “The first LRU list L1 includes list elements L1a, L1b, L1c, . . . , L1m. The list elements L1a, L1b, L1c, . . . , L1m are coupled in this order by pointer [a freelist of pointers]”; [para. 0060] “The RAM 102 is provided with cache memory ... C1 for storing data read from the disk device 200 ... The cache C1 is a set of a plurality of memory blocks [cache set] into which a certain storage area in the RAM 102 is divided by a given size ... the memory block is referred to as a cache page or a page”; [para. 0079] “the replacement page determination unit 112 determines a page to be replaced [available cache sets] based on [corresponding to] LRU1 [freelist of pointers]”; [para. 0138] LRU1 is a freelist as the list of pointers are free to be used to replace a cache page)
update an individual entry in said pointer table by replacing a mapping in the pointer table ... from the freelist of pointers. ([Matsuo, para. 0137] “the replacement page determination unit 112 selects a page corresponding to ... pointer nextLRU1 of the ... LRU1 [freelist of pointers] ... The replacement page determination unit 112 sets the selected page as a page to be replaced”; [para. 0139] “The replacement page determination unit 112 initializes [updates] each set value [an individual entry] of the page management structure corresponding to the page to be replaced [replacing a mapping in the pointer table] to the initial value ... the value that is set when the page is in a free state”; [Fig. 8] the page management structure is a pointer table as it points to location of cache pages; the pointer table as an “indirection pointer table” was taught by Qureshi above)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi with the teachings of Matsuo to include a freelist of pointers corresponding to available cache sets; and update an individual entry in said pointer table by replacing a mapping in the pointer table ... from the freelist of pointers. One of ordinary skill in the art would have been motivated to make this modification because by doing to, it is possible to inhibit prefetched data from remaining in the cache, thereby allowing efficient use of the cache. (Matsuo, para. 0155)
Qureshi in view of Matsuo does not clearly teach replacing a mapping in the pointer table with a new mapping selected from the freelist of pointers.
However, Duggal teaches replacing a mapping in the pointer table with a new mapping selected from the freelist of pointers. ([Duggal, para. 0049-0050; Fig. 2] “Mapper 205 includes entries for architectural register to physical register mappings [pointer table] that are currently in use as of the point in time of initial state 200 [a mapping in the pointer table] ... Freelist 220 consists of identifiers (IDs) of physical registers that are available for being assigned to architectural registers”; [para. 0051; Fig. 3] “a new physical register from the free list 320 [a new mapping selected from the freelist of pointers] is assigned to the destination architectural register x0 [replacing a mapping in the pointer table] ... In the example illustrated in FIG. 3, the entry for x0 in mapper 305 is updated to point to physical register 6”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi in view of Matsuo with the teachings of Duggal to include replacing a mapping in the pointer table with a new mapping selected from the freelist of pointers. One of ordinary skill in the art would have been motivated to make this modification because such a method of tracking references to a physical register is more elegant, easier to implement, uses less area and has a higher performance than traditional methods. (Duggal, para. 0052)
As per claim 2, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi also teaches wherein the indirection pointer table is further comprised of hardware pointers. ([Qureshi, para. 0055] “Each line in the memory is identified [pointed to] with a ... Physical Line Address (PLA) [hardware pointers]”; [para. 0068] “a one-to-one mapping [the indirection pointer table] from a [is further comprised of] ... physical address space [hardware pointers]”)
As per claim 6, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi also teaches wherein the system cache controller further comprises said pointer table engine. ([Qureshi, para. 0017-0022] “provide a system ... the system comprising: ... a processor [system cache controller] comprising: ... encrypt, with the block-cipher using the second key, the relocation pointer, such that the one or more cache locations are respectively remapped [said pointer table engine]”; [para. 0073] “Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping the lines based on the new key”)
As per claim 7, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi also teaches wherein said pointer table engine for updating said indirection pointer table uses one level of pointer indirection. ([Qureshi, para. 0073] “the lines ... are changed periodically ... CEASE can use Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping [updating said indirection pointer table] the lines based on the new key [uses one level of pointer indirection]”)
As per claim 8, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi also teaches wherein said pointer table engine for updating said indirection pointer table uses at least one level of pointer indirection. ([Qureshi, para. 0073] “the lines ... are changed periodically ... CEASE can use Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping [updating said indirection pointer table] the lines based on the new key [uses one level of pointer indirection]”; [para. 0075] “By the time the epoch ends, all the lines in the cache can be remapped using the NextKey [another level of pointer indirection]”)
As per claim 9, Qureshi teaches a processor in communication with at least one cache and a cache controller, comprising: ([Qureshi, para. 0055; Fig. 1a] “computers use caches to bridge the long latency between the fast processor and slow memory, as shown in FIG. 1a”; [para. 0017-0018] “provide a system ... the system comprising: ... a processor [system cache controller] comprising: a plurality of cores; and a cache comprising a plurality of cache locations shared between the plurality of cores... wherein the processor executes one or more instructions that cause ... the system to transmit data stored at the ... cache”; the processor is a cache controller as it controls functions associated with the cache)
circuity configured to: ([Qureshi, para. 0017] “wherein the processor executes one or more instructions that cause the system [circuity] to”)
populate an indirection pointer table with a set of mappings from address sets to cache sets in the at least one cache, ([Qureshi, para. 0017] “Physical line addresses (PLAs) of a plurality of PLAs are mapped to respective cache locations of the plurality of cache locations in the cache [a set of mappings from address sets to cache sets in the at least one cache]”; [Fig. 3; para. 0061] “randomized mapping [an indirection pointer table] of memory lines to cache locations can be accomplished efficiently by operating the cache on an Encrypted Address Space (EAS) instead of the Physical Address Space (PAS), as shown in FIG. 3 ... encryption would cause lines that have some spatial correlation in the PAS ... such as those mapping to the same set of the cache [cache sets] to get scattered throughout [indirection] the space in EAS”; [para. 0062] “CEASE can employ a block cipher, such as Low-Latency Block-Cipher (LLBC), to convert [populate] the b-bit Physical Line-Address (PLA) into a b-bit Encrypted Line-Address (ELA), and uses this ELA [indirection pointer table] to access the cache [a set of mappings from address sets to cache sets in the at least one cache”; [para. 0059] the randomized mapping is a table as it stores the location of the line the cache is determined randomly i.e. in a cipher lookup table; [para. 0061] the mapping is an indirection as it happens in an unpredictable fashion that misdirects the attacker; [para. 0062] the mapping is a pointer as the encrypted address points to/converts back to the physical address; [para. 0101] “the first physical line address can be converted to [assigns address] a first encrypted line address associated with the first encrypted cache location [to one or more cache sets]”)
receive an address, ([Qureshi, para. 0100] “a request can be received to access a first memory line associated with the first PLA [an address]”)
identify an address set associated with the address, ([Qureshi, para. 0070] “Each stage can split the input [first PLA – see Fig. 5a] into two parts [an address set]”)
assign said address set to a cache set using the mappings in the indirection pointer table, ([Qureshi, para. 0102] “the first physical line address [address set as explained above] can be converted [assign] to a first encrypted line address associated with the first encrypted cache location [to a cache set] using the first key [the mappings in the indirection pointer table as the key is incorporated to produce the encrypted cache location]”)
update an individual mapping in the indirection pointer table by a pointer table engine using ... at least one level of pointer indirection ([Qureshi, para. 0073] “the lines ... are changed periodically ... CEASE can use Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping [update an individual entry in said indirection pointer table] the lines [using pointer indirection as the lines ELA are pointers to the physical addresses] based on the new key”; [para. 0109] “the first physical line address [an individual entry in said indirection pointer table] can be converted to a re-encrypted first encrypted line address associated with an updated first encrypted cache location [update an individual entry] using the second key [a remapping/replacing a mapping – see para. 0106: a relocation pointer can be designated to be remapped using the second key ... The relocation pointer can comprise, for example, a cache set]”), such that the address set is reassigned to a different cache set. ([Fig. 11] Examiner notes that this is intended use language and remapping/updating already describes the address being assigned a different cache by using a different key, however, Fig. 7 discloses that every time the address is encrypted, the address set is reassigned to a different cache set)
Qureshi does not clearly teach update an individual mapping in the pointer table by a table engine using a pointer selected from a freelist of available pointers.
update an individual mapping in the pointer table by a table engine using a pointer selected from a freelist of available pointers. ([Matsuo, para. 0078] “When a cache miss has occurred, the cache hit determination unit 111 acquires a new page of the cache C1 from the replacement page determination unit 112 and stores the data read from the disk device 200 in this page”; [para. 0137] “the replacement page determination unit 112 selects a page corresponding to ... pointer nextLRU1 of the ... LRU1 ... The replacement page determination unit 112 sets the selected page as a page to be replaced”; [para. 0139] “The replacement page determination unit 112 initializes [updates] each set value [an individual mapping in the pointer table] of the page management structure [the pointer table] corresponding to the page to be replaced ... the value that is set when the page is in a free state [using said freelist of pointers]”; [Fig. 8] the page management structure is a pointer table as it points to location of cache pages; the pointer table as an “indirection pointer table” was taught by Qureshi above)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi with the teachings of Matsuo to include assign said address to a cache set using on a freelist of pointers corresponding to available cache sets, and update said pointer table in the event of a cache miss using said freelist of available pointers. One of ordinary skill in the art would have been motivated to make this modification because by doing to, it is possible to inhibit prefetched data from remaining in the cache, thereby allowing efficient use of the cache. (Matsuo, para. 0155)
Qureshi in view of Matsuo does not clearly teach update the pointer table using a pointer selected from a freelist of available pointers.
However, Duggal teaches update the pointer table using a pointer selected from a freelist of available pointers. ([Duggal, para. 0049-0050; Fig. 2] “Mapper 205 includes entries for architectural register to physical register mappings [pointer table] that are currently in use as of the point in time of initial state 200 ... Freelist 220 consists of identifiers (IDs) of physical registers that are available for being assigned to architectural registers”; [para. 0051; Fig. 3] “a new physical register from the free list 320 [a pointer selected from the freelist of available pointers] is assigned to the destination architectural register x0 [update the pointer table] ... In the example illustrated in FIG. 3, the entry for x0 in mapper 305 is updated to point to physical register 6”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi in view of Matsuo with the teachings of Duggal to include update the pointer table using a pointer selected from a freelist of available pointers. One of ordinary skill in the art would have been motivated to make this modification because such a method of tracking references to a physical register is more elegant, easier to implement, uses less area and has a higher performance than traditional methods. (Duggal, para. 0052)
As per claim 11, the claim language is identical or substantially similar to that of claim 2. Therefore, it is rejected under the same rationale applied to claim 2.
As per claim 13, Qureshi in view of Matsuo and Duggal teaches claim 9.
Qureshi also teaches wherein the cache controller comprises hardware that implements the pointer table engine. ([Qureshi, para. 0017-0022] “provide a system ... the system comprising: ... a processor [system cache controller] comprising: ... wherein the processor [hardware that implements] executes one or more instructions that cause the system to: ... encrypt, with the block-cipher using the second key, the relocation pointer, such that the one or more cache locations are respectively remapped [implement the pointer table engine]”; [para. 0073] “Dynamic-Remapping (CEASER) [pointer table engine], which can accomplish this by periodically changing the key and remapping the lines based on the new key”)
As per claim 14, the claim language is identical or substantially similar to that of claim 7. Therefore, it is rejected under the same rationale applied to claim 7.
As per claim 15, the claim language is identical or substantially similar to that of claim 8. Therefore, it is rejected under the same rationale applied to claim 8.
Claims 3-5, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Qureshi in view of Matsuo and Duggal as applied to claims 1 and 9 above, and further in view of Rupley et al. (US Pub. 2012/0005444) (hereinafter “Rupley”).
As per claim 3, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi in view of Matsuo and Duggal does not clearly teach wherein the freelist is comprised of hardware pointers.
However, Rupley teaches wherein the freelist is comprised of hardware pointers. ([Rupley, para. 0021] “free list 120 stores pointers ... to available ... physical registers”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi in view of Matsuo and Duggal with the teachings of Rupley to include wherein the freelist is comprised of hardware pointers. One of ordinary skill in the art would have been motivated to make this modification because such a technique reduce latencies from register dependencies. (Rupley, para. 0004)
As per claim 4, Qureshi in view of Matsuo and Duggal teaches claim 1.
Qureshi in view of Matsuo and Duggal does not clearly teach further comprising a microcode unit comprising the indirection pointer table and freelist.
However, Rupley teaches further comprising a microcode unit comprising the indirection pointer table and freelist. ([Rupley, para. 0030] “processor 100 that includes a token-controlled micro-architecture [a microcode unit]”; [Fig. 1] The microcode unit comprises register free list 120 [freelist] and alias table 204 [indirection pointer table]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Qureshi in view of Matsuo and Duggal with the teachings of Rupley to include further comprising a microcode unit comprising the indirection pointer table and freelist. One of ordinary skill in the art would have been motivated to make this modification because such a technique would provide the benefit improving utilization of physical registers by allowing microcode registers to be reclaimed for use. (Rupley, para. 0025)
As per claim 5, Qureshi in view of Matsuo, Duggal and further in view of Rupley teaches claim 4.
Qureshi in view of Matsuo and Duggal does not clearly teach wherein the microcode unit further comprises said pointer table engine.
However, Rupley teaches wherein the microcode unit further comprises said pointer table engine. ([Rupley, para. 0030] “processor 100 that includes a token-controlled micro-architecture [a microcode unit]”; [Fig. 1] The microcode unit comprises dispatch controller 106 [pointer table engine]”; [para. 0022] “dispatch controller 106 [pointer table engine] maps architectural registers to unused physical registers of physical register file 118 in dispatch rename alias table 122”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Qureshi, Matsuo, Rupley and Duggal for the same reasons as disclosed above.
As per claim 10, Qureshi in view of Matsuo and Duggal teaches 9.
Qureshi in view of Matsuo and Duggal does not clearly teach wherein the circuitry comprises a microcode unit.
However, Rupley teaches wherein the circuitry comprises a microcode unit. ([Rupley, para. 0030] “processor 100 [circuitry] that includes [comprises] a token-controlled micro-architecture [a microcode unit]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Qureshi, Matsuo, Rupley and Duggal for the same reasons as disclosed above.
As per claim 12, the claim language is identical or substantially similar to that of claim 3. Therefore, it is rejected under the same rationale applied to claim 3.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Srinivasan et al. (US Pub. 2015/0178077) discloses an allocation that may reuse physical resources identified in a freelist to create new mappings in a pointer table.
Jacob (US Pub. 2016/0253123) discloses a free list maintained by a flash controller used to create new mapping information for page data.
Chen (US Patent No. 7,362,765) discloses getting a pointer from a free list and using it to update an address used to map another location.
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/ZHE LIU/Examiner, Art Unit 2493
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