Response to an Amendment
This office action is a response to a communication made on 03/04/2026.
Claims 7 and 9-11 are canceled.
Claims 12 is new.
Claims 1-6, 8 and 12 are pending for this application.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner Remarks
Note: Applicant is advised that independent claim 8 should be amended as similar subject matter of claim 12.
Response to Arguments
Applicant: Applicant’s arguments, see remarks on page 5-7, filed 03/04/2026, applicant argues that, “Yoo in view of Buskens fails to disclose or suggest “continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down” as recited in the amended claim 1.
Examiner: Applicant's arguments filed 03/04/2026 have been fully considered but they are not persuasive. Yoo ¶0033 and ¶0057, teaches when there is data to be transferred to the main processor 110, the sub-processor 120 may transfer a signal corresponding to this case through the data-ready line Data Ready, and the main processor 110 may receive the signal according to a polling method, which is a software method of continuously checking whether or not a signal is received …the sub-processor 120 or the peripheral device 130 checks whether there is data to be additionally transferred. When there is data to be additionally transferred, the sub-processor 120 or the peripheral device 130 may prepare the data for transfer and then transfer the data through the data-ready line Data Ready. On the other hand, the main processor 110 may check whether or not there is data to be transferred from the sub-processor 120 or the peripheral device 130 on the basis of a change of the signal transferred through the data-read line Data ready.
However, Yoo remain silent on continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down.
Buskens teaches continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down because ¶0025-¶0026, teaches the executable managers 114 and 116 (i.e. other sub-processor, start, stop and monitor executables of the distributed software application 102 that run on the processors 110 and 112… to detect failures of software components 124, 126, 127 and 128 within the executables 106, 107 and 108, the executable managers 114 and 116 send status queries (i.e. second line) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128 (i.e. processors), ¶0038, teaches the high availability infrastructure controls management operations on the software components 124, 126, 127 and 128 for the distributed software application 102. For example, the high availability infrastructure controls shutdown of the software components 124, 126, 127 and 128 in the ordered sequence for the distributed software application 102… The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure, ¶0041, teaches the manager component 104 may coordinate the shutdown of the executables 106, 107 and 108 and/or the software components 124, 126, 127 and 128 running on a single processor or divided among a plurality of processors, such as the processors 110 and 112.
For claims 2, 5 and 6 are not persuaded because of the above reason. For more clarification, please see the rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2011/0106979), hereinafter “Yoo” in view of Buskens et al. (US 2005/0278700), hereinafter “Buskens”. Yoo cited in applicant IDS filed 02/02/2024.
With respect to claim 1, Yoo discloses a method for data exchange between a main processor and at least one sub-processor running asynchronously to the main processor, comprising the following steps:
continuously querying a status line for data transmission by the main processor (¶0030, teaches a master in slave out (MISO) line MISO and a master out slave in (MOSI) line MOSI are used for data transfer, ¶0033, teaches continuously checking whether or not a signal is received, ¶0057, teaches the data-ready line (i.e. status line) Data Ready (see FIG. 2) may be connected between the main processor 110 and the sub-processor 120 or the peripheral device 130…informing the main processor 110 that there is data to be transferred);
preparing transmission data of the sub-processor for the main processor (¶0033, teaches a data-ready line Data Ready for transferring a signal indicating that there is data to be transferred from the sub-processor 120 to the main processor 110 may be additionally prepared… the sub-processor 120 may transfer a signal corresponding to this case through the data-ready line (i.e. status line) Data Ready);
changing a status of the status line via the sub-processor (¶0010, teaches switching (i.e. changing) the selected sub-processor or peripheral device to an operable state (i.e. status), ¶0032, teaches the signal input to the interrupt line Intr serves to switch the sub-processor 120 from a sleep state to a wake-up state, and may also serve to initialize an internal state machine of the sub-processor 120, ¶0053);
starting data transmission from the main processor to the sub-processor based on the availability (¶0007, teaches as a multi-master serial bus, an inter-integrated circuit (I2C) is an interface currently capable (i.e. available or availability) of connecting a processor with devices and ensuring extensibility, ¶0030, teaches a master in slave out (MISO) line MISO and a master out slave in (MOSI) line MOSI are used for data transfer, ¶0033, teaches data transfer from the main processor 110 to the sub-processor, ¶0037, teaches the data frame format of a command transferred from the main processor 110 to the sub-processor 120 or the peripheral device 130), and simultaneously transmitting the transmission data from the sub-processor to the main processor (¶0033, teaches When there is data to be transferred from the sub-processor 120 to the main processor 110, a data-ready line Data Ready for transferring a signal indicating that there is data to be transferred from the sub-processor 120 to the main processor 110 may be additionally prepared, ¶0058, teaches the sub-processor 120 or the peripheral device 130 may transfer data to the main processor 110 in a predetermined form).
However, Yoo remain silent on continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down, wherein availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor via a second line.
Buskens discloses continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down (¶0025-¶0026, teaches the executable managers 114 and 116 (i.e. other sub-processor, start, stop and monitor executables of the distributed software application 102 that run on the processors 110 and 112… to detect failures of software components 124, 126, 127 and 128 within the executables 106, 107 and 108, the executable managers 114 and 116 send status queries (i.e. second line) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128 (i.e. processors), ¶0038, teaches the high availability infrastructure controls management operations on the software components 124, 126, 127 and 128 for the distributed software application 102. For example, the high availability infrastructure controls shutdown of the software components 124, 126, 127 and 128 in the ordered sequence for the distributed software application 102… The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure, ¶0041, teaches the manager component 104 may coordinate the shutdown of the executables 106, 107 and 108 and/or the software components 124, 126, 127 and 128 running on a single processor or divided among a plurality of processors, such as the processors 110 and 112);
wherein availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor via a second line (¶0025-¶0026, teaches the executable managers 114 and 116 (i.e. other sub-processor, start, stop and monitor executables of the distributed software application 102 that run on the processors 110 and 112… to detect failures of software components 124, 126, 127 and 128 within the executables 106, 107 and 108, the executable managers 114 and 116 send status queries (i.e. second line) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128 (i.e. processors), ¶0038, teaches the high availability infrastructure controls management operations on the software components 124, 126, 127 and 128 for the distributed software application 102. For example, the high availability infrastructure controls shutdown of the software components 124, 126, 127 and 128 in the ordered sequence for the distributed software application 102… The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yoo’s continuously checking whether or not a signal is received, and the sub-processor or the peripheral device checks whether there is data to be additionally transferred with continuously checking an availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via a second line, the checking including continuously checking, via the second line, whether one of the sub- processor and the main processor is shut down and wherein availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor via a second line of Buskens, in order to support detection when the primary path is down and the second line still operates (Buskens).
With respect to claim 3, Yoo in view Buskens discloses the method according to claim 1, wherein a protocol version is transmitted and aligned before the first data transmission (Yoo, ¶0010, teaches at least one sub-processor or at least one peripheral device connected with the main processor according to an SPI (i.e. protocol version) method and performing an operation corresponding to a command transferred (i.e. transmitted) from the main processor), ¶0052, teaches the initialization may be performed before a first valid byte is transferred from the main processor 110).
With respect to claim 4, Yoo in view Buskens disclose the method according to claim 3, wherein the protocol version is transmitted until a match has been confirmed via the main processor and the sub-processor (Yoo, ¶0010, teaches at least one sub-processor or at least one peripheral device connected with the main processor according to an SPI (i.e. protocol version is match) method and performing an operation corresponding to a command transferred (i.e. transmitted) from the main processor, ¶0026, teaches the sub-processors 120 and the peripheral devices 130 may be connected (i.e. match) with the main processor 110 by serial communication. According to an exemplary embodiment of the present invention, the serial communication may be in accordance with a serial peripheral interface (SPI) method, ¶0028, teaches FIG. 2 illustrates a case in which the main processor 110 and the sub-processor 120 are connected (i.e. match) according to an SPI communication method, the main processor 110 and the peripheral device 130 also can be connected according to the same communication method).
With respect to claim 8, Yoo discloses a device configured for data exchange between a main processor and at least one sub-processor running asynchronously to the main processor, the device comprising:
the main processor (Fig. 1, main processor 110);
the sub-processor (Fig. 1, Sub-processors 120);
a data transmission line between the main and sub-processor (¶0030, teaches a master in slave out (MISO) line MISO and a master out slave in (MOSI) line MOSI are used for data transfer);
a status line via which a readiness of the sub-processor to transmit data can be communicated to the main processor (¶0057, teaches the data-ready line (i.e. status line) Data Ready (see FIG. 2) may be connected between the main processor 110 and the sub-processor 120 or the peripheral device 130…informing the main processor 110 that there is data to be transferred); and
wherein the device is configured to:
prepare transmission data of the sub-processor for the main processor (¶0033, teaches a data-ready line Data Ready for transferring a signal indicating that there is data to be transferred from the sub-processor 120 to the main processor 110 may be additionally prepared… the sub-processor 120 may transfer a signal corresponding to this case through the data-ready line (i.e. status line) Data Ready);
change a status of the status line via the sub-processor (¶0010, teaches switching (i.e. changing) the selected sub-processor or peripheral device to an operable state (i.e. status), ¶0032, teaches the signal input to the interrupt line Intr serves to switch the sub-processor 120 from a sleep state to a wake-up state, and may also serve to initialize an internal state machine of the sub-processor 120, ¶0053);
start data transmission from the main processor to the sub-processor based on the availability (¶0007, teaches as a multi-master serial bus, an inter-integrated circuit (I2C) is an interface currently capable (i.e. available or availability) of connecting a processor with devices and ensuring extensibility, ¶0030, teaches a master in slave out (MISO) line MISO and a master out slave in (MOSI) line MOSI are used for data transfer, ¶0033, teaches data transfer from the main processor 110 to the sub-processor, ¶0037, teaches the data frame format of a command transferred from the main processor 110 to the sub-processor 120 or the peripheral device 130), and simultaneously transmit the transmission data from the sub-processor to the main processor (¶0033, teaches When there is data to be transferred from the sub-processor 120 to the main processor 110, a data-ready line Data Ready for transferring a signal indicating that there is data to be transferred from the sub-processor 120 to the main processor 110 may be additionally prepared, ¶0058, teaches the sub-processor 120 or the peripheral device 130 may transfer data to the main processor 110 in a predetermined form).
However, Yoo remain silent on continuously check the availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via the at least one further line, the checking including continuously checking, via the at least one further line, whether one of the sub-processor and the main processor is shut down, at least one further line with which availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor, wherein the device is configured to: continuously query the status line for data transmission by the main processor.
Buskens discloses continuously check the availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via the at least one further line, the checking including continuously checking, via the at least one further line, whether one of the sub-processor and the main processor is shut down (¶0025-¶0026, teaches the executable managers 114 and 116 (i.e. other sub-processor, start, stop and monitor executables of the distributed software application 102 that run on the processors 110 and 112… to detect failures of software components 124, 126, 127 and 128 within the executables 106, 107 and 108, the executable managers 114 and 116 send status queries (i.e. second line) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128 (i.e. processors), ¶0038, teaches the high availability infrastructure controls management operations on the software components 124, 126, 127 and 128 for the distributed software application 102. For example, the high availability infrastructure controls shutdown of the software components 124, 126, 127 and 128 in the ordered sequence for the distributed software application 102… The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure, ¶0041, teaches the manager component 104 may coordinate the shutdown of the executables 106, 107 and 108 and/or the software components 124, 126, 127 and 128 running on a single processor or divided among a plurality of processors, such as the processors 110 and 112);
at least one further line with which availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor (¶0025-¶0026, teaches the executable managers 114 and 116 (i.e. other sub-processor, start, stop and monitor executables of the distributed software application 102 that run on the processors 110 and 112… to detect failures of software components 124, 126, 127 and 128 within the executables 106, 107 and 108, the executable managers 114 and 116 send status queries (i.e. second line) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128 (i.e. processors), ¶0038, teaches the high availability infrastructure controls management operations on the software components 124, 126, 127 and 128 for the distributed software application 102. For example, the high availability infrastructure controls shutdown of the software components 124, 126, 127 and 128 in the ordered sequence for the distributed software application 102… The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure);
wherein the device is configured to: continuously query the status line for data transmission by the main processor (¶0026, teaches the executable managers 114 and 116 send status queries (i.e. query the status lines) to the software components 124, 126, 127 and 128 and expect to receive status responses from the software components 124, 126, 127 and 128, ¶0038, teaches The high availability infrastructure is able to continue processing while switching between active and standby components in the high availability infrastructure
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yoo’s continuously checking whether or not a signal is received, and the sub-processor or the peripheral device checks whether there is data to be additionally transferred with continuously check the availability of one of the sub-processor and the main processor by the other of the sub-processor and the main processor via the at least one further line, the checking including continuously checking, via the at least one further line, whether one of the sub-processor and the main processor is shut down, at least one further line with which availability of one of the sub-processor and the main processor is continuously checked by the other of the sub-processor and the main processor of Buskens, in order to support detection when the primary path is down and the second line still operates (Buskens).
Claim(s) 2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Buskens, and further in view of Li (US 2022/0407660).
With respect to claim 2, Yoo in view of Buskens discloses the method according to claim 1, Yoo, ¶0010, teaches switching (i.e. changing) the selected sub-processor or peripheral device to an operable state (i.e. status). However, Yoo remain silent on wherein the change of the status is carried out via a change in a polarity of the status line.
Li discloses wherein the change of the status is carried out via a change in a polarity of the status line (¶0042, teaches the second processor may set (i.e. change) the slave acknowledge interface to a low-level (i.e. polarity) state).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yoo’s switching (i.e. changing) the selected sub-processor or peripheral device to an operable state (i.e. status) in view of Buskens’s system with a change in a polarity of the status line of Li, in order to ensure compatibility across different systems and efficiency of processor communication and data transmission can be improved (Li, ¶0050).
With respect to claim 6, Yoo in view of Buskens discloses the method according to claim 1, Yoo ¶0057, teaches the data-ready line (i.e. status line) Data Ready (see FIG. 2) may be connected between the main processor 110 and the sub-processor 120 or the peripheral device 130…informing the main processor 110 that there is data to be transferred, ¶0060, teaches after reading all result values transferred from the sub-processor 120 or the peripheral device 130, the main processor 110 may reset a selection signal transferred through the SS line SS, thereby completing communication. However, Yoo in view of Buskens remain silent on wherein an initial value for the status line is set to low before a first data transmission or after a reset.
Li discloses wherein an initial value for the status line is set to low before a first data transmission or after a reset (¶0042, teaches the second processor may set (i.e. change) the slave acknowledge interface to a low-level state ¶0061, teaches the master interrupt interface to be the first value (i.e. initial value) before the resetting, ¶0087, teaches the low level representing the reset master acknowledge signal are taken as an example, when receiving the reset slave interrupt signal and completing the reading of the uplink package, the first processor sets the master acknowledge interface from a high-level state to a low-level state).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yoo’s values transferred from the sub-processor 120 or the peripheral device 130, the main processor 110 may reset a selection signal transferred through the SS line SS in view of Buskens’s system with an initial value for the status line is set to low before a first data transmission or after a reset of Li, in order to ensure clear communication, efficiency of processor communication and data transmission can be improved and synchronization between sender and receiver (Li, ¶0050).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Buskens, and further in view of Bristow et al. (US 5142470), hereinafter “Bristow”.
With respect to claim 5, Yoo in view of Buskens discloses the method according to claim 1, Yoo, ¶0058, teaches the sub-processor 120 or the peripheral device 130 may transfer data to the main processor 110 in a predetermined form. However, Yoo in view of Buskens remain silent on wherein a transmission end is ascertained via a predefined number of transmitted data.
Bristow discloses wherein a transmission end is ascertained via a predefined number of transmitted data (Col-10, II. 40-44, teaches Both the primary and secondary IOP stop processing everything that comes after the freeze command (messages can be accepted from any source on the link, BUS A 22, but are not processed after detecting the freeze command), Col-11, II. 49-54, teaches the primary and secondary input/output processor’s (IOPs) have predetermined knowledge of the number of records, format of the records, . . . . On the last read transaction of the DUMP command, the primary IOP indicates the last read to the controller 30 indicating the end of the data base information).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Yoo’s the sub-processor or the peripheral device may transfer data to the main processor in a predetermined form in view of Buskens’s system with transmission end is ascertained of Bristow, in order to help with accurate data parsing, reduces errors and ambiguity (Bristow, Col-10, II. 40-44 and Col-11, II. 49-54).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM MAHMUD whose telephone number is (571)270-0385. The examiner can normally be reached Mon-Fri 8.00-5.00pm.
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/G.M/Examiner, Art Unit 2458
/UMAR CHEEMA/Supervisory Patent Examiner, Art Unit 2458
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