DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election of Group 1, Claims 1-11, drawn to a method, has been acknowledged. Claims 1-20 remain pending. Claims 12-20 have been withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device Including Shielding Doped Region and Well Region and Manufacturing Method Thereof.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al’654 (US 2022/0367654).
Regarding Claim 1, Chen et al’654 discloses a method of manufacturing (method of forming [0071]) a semiconductor device (MOSFET [0071]), comprising:
providing a substrate (substrate 101 [0072] Fig 11A-B);
forming a first trench (recess 1202 [0075] Fig 12A-C) in the substrate (101 Fig 12A-C), a top width of the first trench (1202 Fig 12A-C) being greater (shown in Fig 12A-B) than a bottom width of the first trench (1202 Fig 12A-C);
forming a well region (middle portion of well region 102 [0075] Fig 12A-C) and a source region (side portions of well region 102 Fig 12A-C) at a side of the first trench (1202 Fig 12A-C), the source region (side portions of well region 102 Fig 12A-C) being on the well region (middle portion of well region 102 Fig 12A-C);
forming a hard mask stack (gate dielectric layer 120, gate dielectric layer 122, and first masking structure 1602 [0088] Fig 16 A-C) lining a surface of the substrate (101 Fig 16 A-C);
forming a second trench (shown in Fig 17A-B) in the hard mask stack (120, 122, 1602 Fig 17 A-C), the bottom of the second trench (shown in Fig 17A-B) being over a corner of the first trench (1202 Fig 17A-C);
performing an ion implantation process (ion implantation process [0080]) to form a shielding doped region (lightly doped regions 304 [0037] Fig 17 B-C) at a region of the substrate nearing the corner of the first trench (1202 Fig 17A-C);
removing (shown in Fig 18A-C) the hard mask stack (120, 122, 1602 Fig 17A-C);
forming a gate dielectric layer (third gate dielectric layer 124 [0039] Fig 18A-C) lining the surface of the substrate (101 Fig 18A-C), the gate dielectric layer (124 Fig 18A-C) covering the shielding doped region 304 Fig 18A-C); and
forming a gate (gate electrode 108 [0039] Fig 20A-C) in the first trench (1202 Fig 18A-C).
Regarding Claim 6, Chen et al’654 discloses the limitations of claim 1 as explained above. Chen et al’654 further discloses
wherein forming a first trench (1202 Fig 18A-C) in the substrate (101 Fig 18A-C) comprises:
forming two stepped dielectric layer stacks (120, 122, 1602 Fig 17A-C) spaced apart by a distance on the substrate (101 Fig 18A-C); and
etching the substrate (101 Fig 18A-C) through the two stepped dielectric layer stacks (120, 122, 1602 Fig 17A-C) to form the first trench (1202 Fig 18A-C) in the substrate (101 Fig 18A-C).
Regarding Claim 9, Chen et al’654 discloses the limitations of claim 1 as explained above. Chen et al’654 further discloses
forming a sacrificial oxide layer (portion of first interconnect dielectric layer 114a, which may be silicon oxide [0102], that is over 108 Fig 23A-B) on the substrate (101 Fig 23A-B) after forming the first trench (1202 Fig 18A-C): and
removing (shown in Fig 24A-B) the sacrificial oxide layer (portion of 114a that is over 108 Fig 23A-B).
Regarding Claim 10, Chen et al’654 discloses the limitations of claim 1 as explained above. Chen et al’654 further discloses
wherein the hard mask stack stack (gate dielectric layer 120, gate dielectric layer 122, and first masking structure 1602 [0088] Fig 16 A-C) comprises a first hard mask sublayer (120 Fig 16A-C), a second hard mask sublayer (1602 Fig 16A-C) and a third hard mask sublayer (122 Fig 16A-C) from bottom to top, the first hard mask sublayer (120 Fig 16A-C) and the third hard mask sublayer (122 Fig 16A-C) are made of a third material (120 and 122 may comprise the same or similar materials [0027], may be silicon dioxide [0078]), and the second hard mask sublayer (1602 Fig 16A-C) is made of a fourth material (1602 may be a photoresist material [0085]) different (silicon dioxide is different from a photoresist material) from the third material (silicon dioxide).
Regarding Claim 11, Chen et al’654 discloses the limitations of claim 10 as explained above. Chen et al’654 further discloses
wherein a bottom of the second trench (shown in Fig 17A-B) is on an upper surface (shown in Fig 17A-B) of the first hard mask sublayer (120 Fig 17A-B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al’654 (US 2022/0367654) in view of Chen et al’483 (TW I293483 B).
Regarding Claim 2, Chen et al’654 discloses the limitations of claim 1 as explained above. Chen et al’654 does not directly disclose
wherein forming a first trench in the substrate comprises: forming a hard mask layer on the substrate;
forming a patterned photoresist layer over the hard mask layer;
performing a first etching process on the hard mask layer via the patterned photoresist layer, to form an inverted trapezoidal opening in the hard mask layer; and
performing a second etching process on the substrate via the hard mask layer, to form the first trench in the substrate.
Chen et al’483, in the related art of semiconductors that include MOS transistors, discloses
wherein forming a first trench (shown in Fig 1D) in the substrate (substrate 12 [page 2, lines 14-49] Fig 1A-D) comprises:
forming a hard mask layer (hard mask layer 14A and anti-reflective coating layer 14B [page 2, lines 14- 49] Fig 1A-D) on the substrate (substrate 12 [page 2, lines 14-49] Fig 1A-D);
forming a patterned photoresist layer (patterned photoresist layer 16 [page 3, lines 138] Fig 1A) over the hard mask layer (14A-B Fig 1A-D);
performing a first etching process (first etch process [page 2, lines 14-49]) on the hard mask layer (14A-B Fig 1A-D) via the patterned photoresist layer (Fig 1A), to form an inverted trapezoidal opening (shown in Fig 1D) in the hard mask layer (14A-B Fig 1A-D); and
performing a second etching process (second etch process [page 2, lines 14-49]) on the substrate (12 Fig 1A-D) via the hard mask layer (14A-B Fig 1A-D), to form the first trench (shown in Fig 1D) in the substrate (12 Fig 1A-D).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen et al’654 to include wherein forming a first trench in the substrate comprises: forming a hard mask layer on the substrate; forming a patterned photoresist layer over the hard mask layer; performing a first etching process on the hard mask layer via the patterned photoresist layer, to form an inverted trapezoidal opening in the hard mask layer; and performing a second etching process on the substrate via the hard mask layer, to form the first trench in the substrate as taught by Chen et al’483 in order to control undesirable current leakage problems [page 2, lines 14-49]. Further, a person of ordinary skill in the art would have recognized that avoiding current leakage would be advantageous in optimizing the electrical functioning of the device while avoiding undesirable damage would improve the reliability and durability of the device (see MPEP 2143.I(D)).
Regarding Claim 4, Chen et al’654 discloses the limitations of claim 1 as explained above. Chen et al’654 does not directly disclose
wherein the forming a first trench in the substrate comprises:
forming a hard mask layer on the substrate;
forming a patterned photoresist layer over the hard mask layer;
performing a first etching process on the hard mask layer via the patterned photoresist layer, to form an opening in the hard mask layer,
wherein the opening has a vertical side wall; and
performing a second etching process on the substrate via the hard mask layer, to form the first trench in the substrate.
Chen et al’483, in the related art of semiconductors that include MOS transistors, discloses
wherein forming a first trench (shown in Fig 1D) in the substrate (substrate 12 [page 2, lines 14-49] Fig 1A-D) comprises:
forming a hard mask layer (hard mask layer 14A and anti-reflective coating layer 14B [page 2, lines 14- 49] Fig 1A-D) on the substrate (substrate 12 [page 2, lines 14-49] Fig 1A-D);
forming a patterned photoresist layer (patterned photoresist layer 16 [page 3, lines 138] Fig 1A) over the hard mask layer (14A-B Fig 1A-D);
performing a first etching process (first etch process [page 2, lines 14-49]) on the hard mask layer (14A-B Fig 1A-D) via the patterned photoresist layer (Fig 1A), to form an opening (shown in Fig 1D) in the hard mask layer (14A-B Fig 1A-D); and
wherein the opening (shown in Fig 1D) has a vertical side wall (shown in Fig 1D); and
performing a second etching process (second etch process [page 2, lines 14-49]) on the substrate (12 Fig 1A-D) via the hard mask layer (14A-B Fig 1A-D), to form the first trench (shown in Fig 1D) in the substrate (12 Fig 1A-D).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen et al’654 to include wherein the forming a first trench in the substrate comprises: forming a hard mask layer on the substrate; forming a patterned photoresist layer over the hard mask layer; performing a first etching process on the hard mask layer via the patterned photoresist layer, to form an opening in the hard mask layer, wherein the opening has a vertical side wall; and performing a second etching process on the substrate via the hard mask layer, to form the first trench in the substrate as taught by Chen et al’483 in order to control undesirable current leakage problems [page 2, lines 14-49]. Further, a person of ordinary skill in the art would have recognized that avoiding current leakage would be advantageous in optimizing the electrical functioning of the device while avoiding undesirable damage would improve the reliability and durability of the device (see MPEP 2143.I(D)).
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al’654 (US 2022/0367654) in view of Chen et al’483 (TW I293483 B), and in further view of Kato et al (US 2007/0048954).
Regarding Claim 3, the combination of Chen et al’654 and Chen et al’483 discloses the limitations of claim 2 as explained above. The combination of Chen et al’654 and Chen et al’483 does not directly disclose
wherein performing a first etching process comprises: adjusting at least one of a plurality of etching parameters of the first etching process, the etching parameters comprise etching gas concentration and etching energy, and
during the second etching process, a plurality of etching parameters of the second etching process remain consistent.
Kato et al, in the related art of semiconductor devices that include methods of etching, discloses
wherein performing a first etching process (first etching process [0070]) comprises: adjusting at least one of a plurality of etching parameters of the first etching process [0070], the etching parameters comprise etching gas concentration (gas flow [0070]) and etching energy (ion incident energy [0070]), and
during the second etching process (second etching process [0076]), a plurality of etching parameters of the second etching process [0076] remain consistent (more stable etching treatment [0076]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen et al’654 and Chen et al’483 to include
wherein performing a first etching process comprises: adjusting at least one of a plurality of etching parameters of the first etching process, the etching parameters comprise etching gas concentration and etching energy, and during the second etching process, a plurality of etching parameters of the second etching process remain consistent as taught by Kato et al in order to obtain a better shape of the trench [0077]. Further, a person of ordinary skill in the art would have recognized that having more control over the etching process to obtain a better shape would be advantageous in optimizing the electrical performance and durability of the device (see MPEP 2143.I(D)).
Regarding Claim 5, the combination of Chen et al’654 and Chen et al’483 discloses the limitations of claim 4 as explained above. The combination of Chen et al’654 and Chen et al’483 does not directly disclose
wherein during the first etching process, a plurality of etching parameters of the first etching process remain consistent, the plurality of etching parameters comprise etching gas concentration and etching energy, and
performing a second etching process comprises: adjusting at least one of a plurality of etching parameters of the second etching process.
Kato et al, in the related art of semiconductor devices that include methods of etching, discloses
wherein during the first etching process (first etching process [0070]), a plurality of etching parameters of the first etching process [0070] remain consistent (the etching rate is not changed [0077]), the plurality of etching parameters comprise etching gas concentration (gas flow [0070]) and etching energy (ion incident energy [0070]), and
performing a second etching process (second etching process [0076]) comprises: adjusting at least one of a plurality of etching parameters (alternatively, a better shape of the trench by be obtained by changing other parameters [0077] of the second etching process) of the second etching process [0076].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen et al’654 and Chen et al’483 to include
wherein during the first etching process, a plurality of etching parameters of the first etching process remain consistent, the plurality of etching parameters comprise etching gas concentration and etching energy, and performing a second etching process comprises: adjusting at least one of a plurality of etching parameters of the second etching process as taught by Kato et al in order to obtain a better shape of the trench [0077]. Further, a person of ordinary skill in the art would have recognized that having more control over the etching process to obtain a better shape would be advantageous in optimizing the electrical performance and durability of the device (see MPEP 2143.I(D)).
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7: The prior art does not anticipate or render obvious, alone or in combination, that “wherein forming two stepped dielectric layer stacks spaced apart by a distance on the substrate comprises: forming a dielectric layer stack on the substrate, wherein the dielectric layer stack comprises a plurality of first dielectric layers and a plurality of second dielectric layers stacked alternately, the plurality of first dielectric layers are made of a first material, and the plurality of second dielectric layers are made of a second material different from the first material; forming a photoresist layer on the dielectric layer stack, and patterning the photoresist layer; patterning a topmost layer of the second dielectric layer and a topmost layer of the first dielectric layer through the photoresist layer; forming a plurality of first spacers on a plurality of side walls of the topmost layer of the second dielectric layer and the topmost layer of the first dielectric layer; patterning a second layer of the second dielectric layer and a second layer of the first dielectric layer via the plurality of first spacers; removing the plurality of first spacers; forming a plurality of second spacers on a plurality of side walls of the second layer of the second dielectric layer and the second layer of the first dielectric layer; and patterning a third layer of the second dielectric layer and a third layer of the first dielectric layer via the plurality of second spacers, to form the two stepped dielectric layer stacks,” in the combination required by the claim.
Claim 8 would be allowable based on its dependency on Claim 7.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamaoka et al (US 2003/0181067) which discloses a method of fabricating a semiconductor device including a low dielectric constant insulating film [0002], and Panda et al (US 2003/0211686) which discloses a method of etching a deep trench with high aspect ratios [0005].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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