Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant' s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application CN 2021/10918978 filed on 11 August, 2021. The foreign application is not in English. The certified copy of the foreign priority application CN 2021/10918978 has been received.
To be entitled to the filing date of the foreign priority application CN 2021/10918978 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119(a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0003], “during the circuit is being manufactured” should read “while the circuit is being manufactured”.
In paragraph [0020], the applicant states, “In some embodiments, the trivalent elements in the step S1, the step S3, the step S7, the step S8, and the step S9 include boron; and the pentavalent elements in the step S1, the step S3, the step S7, the step S8, and the step S9 are selected from arsenic and phosphorus.” However, steps S1 and S8, as described in paragraphs [0011] and [0018], respectively, do not involve trivalent elements, and steps S3, S7, and S9, as described in paragraphs [0013], [0017], and [0019], respectively, do not involve pentavalent elements.
Appropriate correction is required.
Claim Objections
Claim 4 and 6 objected to because of the following informalities:
Claim 4 recites the redundant limitation, “until the total thickness of the intrinsic epitaxial layer reaches the range of 30 um to 70 um.”
In claim 6, line 8, “patter” should be “pattern”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “adjustable resistors”. However, while the specification mentions control electrodes attached to each resistor, there is no statement of how the resistors can be adjusted, thus rendering the claim indefinite.
Claims 2-9 are also rejected due to their dependence on claim 1, as they inherit the deficiencies of claim 1 as described above. Claims 3 and 5-9 are also rejected on the grounds detailed below.
Claim 3 recites the limitations, “wherein the trivalent elements in the step S1, the step S3, the step S7, the step S8, and the step S9 include boron” and “the pentavalent elements in the step S1, the step S3, the step S7, the step S8, and the step S9 are selected from arsenic and phosphorus.” However, steps S1 and S8, as recited in claim 2, which this claim is dependent on, do not involve trivalent elements, and steps S3, S7, and S9, as recited in claim 2, do not involve pentavalent elements. Therefore, there is insufficient antecedent basis for these limitations in the claim.
Claim 5 recites the limitations, “the gate oxide layer” in line 1, “the step S5” in line 1, and “the gate polysilicon” in line 2. There is insufficient antecedent basis for these limitations in the claim, as the claim depends on claim 1, which does not recite these limitations.
Claim 6 recites the limitations, “the source regions” in line 3 and “the body regions” in line 7. There is insufficient antecedent basis for these limitations in the claim, as the claim depends on claim 1, which does not recite these limitations. In addition, this claim recites steps S10-S14 although steps S1-S9 are not recited either in this claim or in claim 1.
Claim 7 recites the limitations, “the tungsten bolt” in lines 3-4, “the photoresist” in line 5, “the source regions” in line 10, and “the gate region” in line 12. There is insufficient antecedent basis for these limitations in the claim, as the claim depends on claim 1, which does not recite these limitations. In addition, this claim recites a step S15 although steps S1-S14 are not recited either in this claim or in claim 1.
Claim 8 is also rejected due to its dependence on claim 7, as it inherits the deficiencies of claim 7 as described above.
Claim 9 recites the limitation “the photoresist” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim, as the claim depends on claim 1, which does not recite these limitations. In addition, this claim recites a step S16 although steps S1-S15 are not recited either in this claim or in claim 1.
Claim 10 recites the limitation, “adjustable resistors”. However, while the specification mentions control electrodes attached to each resistor, there is no statement of how the resistors are adjusted, thus rendering the claim indefinite.
For examination purposes, the following will be assumed:
An adjustable resistor, as recited in claims 1 and 10, can be any resistor whose resistance can be adjusted, regardless of the means by which such adjustment is accomplished.
The applicant meant to limit the trivalent elements in steps S3, S7, and S9, and the pentavalent elements in steps S1 and S8, in claim 3.
Claims 5 and 6 are meant to depend on claim 2, rather than claim 1.
Claim 7 is meant to depend on claim 6, rather than claim 1.
Claim 9 is meant to depend on claim 7, rather than claim 1.
The applicant may overcome these rejections by
Reciting a means by which the adjustable resistors may in fact be adjusted either in the text of the claims or in the specification,
Rewriting claim 3 so that the trivalent and pentavalent elements are only stated to be present in those steps recited in claim 2 that they occur in,
Rewriting claims 5 and 6 to depend on claim 2,
Rewriting claim 7 to depend on claim 6, and
Rewriting claim 9 to depend on claim 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
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Fig. 3 of Feil, reproduced above with annotations added by the examiner.
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Fig. 12B of Feil, reproduced above with annotations added by the examiner.
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Fig. 12C of Feil, reproduced with annotations added by the examiner.
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Fig. 1 of Satou, reproduced above with annotations added by the examiner.
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Reproduction of Fig. 2 of Satou.
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Fig. 4 of Mizan, with annotations added by the examiner.
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Fig. 4 of Chi, reproduced above with annotation added by the examiner.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Feil et. al., Pub. No. US 2019/0326277, hereafter referred to as Feil, in view of Satou et. al., Pub. No. WO 2012/165649, hereafter referred to as Satou, Mizan et. al., Pub. No. US 2023/0198252, hereafter referred to as Mizan, and Chi et. al., Pub. No. US 2023/0326962, hereafter referred to as Chi.
Regarding claim 1, Feil teaches “having adjustable resistors” (Feil [0057]; Fig. 3, first resistor 32, Fig. 12B, conductors 321), “wherein the gates” (Feil [0048]; Fig. 12C, gate electrodes 25) “and the sources” (Feil [0048]; Fig. 12C, sources 22) “are in one-to-one correspondence with each other” (Feil Figs. 12B and 12C), “the method comprising: … preparing a unit cell” (Feil, Figs. 12B and 12C) “and the adjustable resistors” (Feil [0025], [0031], and [0056]; Fig. 3, first resistor 32, Fig. 12B, conductors 321; also see [0057]: “A resistance of the first resistor 32 can be adjusted by suitably adjusting lengths of the conductors 321, more specifically, by a distance between the positions at which the conductors 321 are connected to the third and fourth metallizations 63, 64.”); and “a step B: preparing contact holes” (Feil [0052-0056]; Fig. 12B, vias 316, 3431, 3221, and 3222), and “a step C: preparing metal wires” (Feil [0048]; Fig. 12B, second through fourth metallizations 62-64, Fig. 12C, source electrode 46), but does not teach “A method of manufacturing a super-junction power device”, “connected in parallel between gates and sources”, “and more than one adjustable resistors are connected in parallel between each of the gates and the corresponding one of the sources”, “a step A… connected in parallel between the source and the gate of the super-junction power device”, and “a step D: preparing a passivation layer.” Feil does, however, teach a semiconductor power transistor device.
Satou, on the other hand, teaches a super-junction semiconductor power device (Satou p. 9, lines 16-17: “The half bridge circuit 1 is formed of two N-channel type SJ (super-junction)-MOSFETs (power MOSFETs) 3H and 3L…”; Fig. 1, super-junction MOSFET 3H).
The super-junction transistor of Satou can be incorporated as a substitute for the power transistors of Feil.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use the super-junction transistors of Satou as the power transistors of Feil because super-junction transistors are a type of power transistor and it would be a simple substitution of one element for another. The combination of Feil and Satou teaches “A method of manufacturing a super-junction power device”.
However, the combination of Feil and Satou just described does not teach “connected in parallel between gates and sources”, “and more than one adjustable resistors are connected in parallel between each of the gates and the corresponding one of the sources”, “a step A… connected in parallel between the source and the gate of the super-junction power device”, and “a step D: preparing a passivation layer.”
Mizan, on the other hand, teaches resistors connected in parallel (Mizan [0046]; Fig. 4, resistors R1 and R2) between a gate and a source (Mizan [0046]; Fig. 4, gate driver input and source) on a standard field-effect transistor (Mizan [0015]; Fig. 4, transistor Qmain).
The parallel resistors of Mizan can be incorporated into the combination of Feil and Satou described above as two parallel adjustable resistors, as taught by Feil, connecting each gate electrode to a corresponding source, with contacts prepared for each resistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use parallel resistors in place of the single resistor in the combination of Feil and Satou because resistors in parallel are electrically equivalent to a single resistor, and it would be a simple substitution of two resistors in parallel for a single resistor. The combination of Feil, Satou, and Mizan teaches “connected in parallel between gates and sources”, “and more than one adjustable resistors are connected in parallel between each of the gates and the corresponding one of the sources”, “a step A… connected in parallel between the source and the gate of the super-junction power device”.
However, the combination of Feil, Satou, and Mizan just described does not teach “a step D: preparing a passivation layer.”
Chi, on the other hand, teaches a manufacturing process for a super junction power device (Chi [0005]; Fig. 4) that includes “a step D: preparing a passivation layer” (Chi [0070]; Fig. 4, interlayer dielectric layer 110).
The preparation of a passivation layer taught by Chi can be incorporated into the combination of Feil, Satou, and Mizan described above as the addition of a passivation layer to the combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to deposit a passivation layer on the combined device of Feil, Satou, and Mizan because the presence of a passivation layer serves to protect the underlying device from oxidation, and is a simple combination of the disclosures of Chi and of the combination of Feil, Satou, and Mizan.
Regarding claim 10, the combination of Feil, Satou, Mizan, and Chi as applied to claim 1 above teaches “A super-junction power device” (Satou p. 9, lines 16-17; Fig. 1, super-junction MOSFET 3H) “having adjustable resistors” (Feil [0025], [0031], and [0056-0057]; Fig. 3, first resistor 32, Fig. 12B, conductors 321) “connected in parallel between a gate and a source” (Mizan [0046]; Fig. 4, resistors R1 and R2, gate driver input, and source). Note that, since this claim is a product-by-process claim, only the product itself has patentable weight (See MPEP 2113 I: “"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)”), i.e., the further limitation, “obtained by performing the manufacturing method according to claim 1”, has no patentable weight.
Allowable Subject Matter
Claims 2-9 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claim limitations of:
Claim 2, which teaches the limitations, “a step S3: defining, by performing a photolithographic process, a pattern of columnar doping regions on the first mask to form the columnar doping regions; doping, by ion implantation, trivalent elements into the intrinsic epitaxial layer; removing the first mask by dry etching and wet etching”, “a step S4: repeating the step S1, the step S2, and the step S3 until a total thickness of the intrinsic epitaxial layer is in a range of 30 um to 70 um”, “a step S6: … defining … a pattern of the adjustable resistors connected in parallel between the gate and the source, wherein a resistance value of the adjustable resistor connected in parallel connected between the gate and the source is adjustable within a range from 5 kOhms to 20 kOhms; wherein an adjustment of the resistance value of the adjustable resistors is achieved by defining the pattern of the adjustable resistors connected in parallel to have a width of 1-10 um, and providing two to five adjustable resistors connected in parallel between one gate and one source”, “a step S8: … blocking, by the third mask, a polysilicon resistor from being doped by the second impurities; removing the third mask by dry etching and wet etching; …”, and “a step S9: obtaining highly-doped ohmic contact regions by implanting the trivalent elements to the upper surface of the intrinsic epitaxial layer; implanting the trivalent elements into the polysilicon resistor to obtain the unit cell and the adjustable resistors connected in parallel between the gate and the source.”
Claims 3 and 4 depend on claim 2, and thus also contain the same allowable material.
Claims 5-9 are assumed to depend on claim 2 (see discussion of 35 U.S.C. 112 above), and thus are also assumed to contain the same allowable material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In particular, Wang et. al., Pub. No. US 2023/0093383, is considered pertinent, although not relied upon for any prior art rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN H LOKE can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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