Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 11-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over AKHAVAN et al. (20230046277), hereafter called AKHAVAN, in view of Al-Hemyari et al. (20220391570), hereafter called Al-Hemuyari.
Regarding claim 1, AKHAVAN discloses claimed invention except having flipped source/voltage follower circuit as claimed. AKHAVAN (Figs. 6 and 8) discloses an amplifier (600), comprising: a first capacitive element (C1) coupled to a first output (Von) of the amplifier (600); a first switch (T5) coupled between the first capacitive element (C1) and a voltage rail (Vdd); a transconductance amplifier (T1 and T2)
Al-Hemuyari (Fig. 4) discloses an amplifier circuit (400) comprising: a transconductance amplifier (M1/M1P) including a first flipped voltage/source follower formed by transistors ((MFVF1 and MB1), (MFVF2, MB2)).
Accordingly, it would have been obvious in view of the reference, taken as a whole, to have modified the circuit of AKHAVAN to have included a flipped source/voltage follower, as taught by Al-Hemuyari. Such a modification would have imparted the advantageous benefit of reduced/decreased impedance at the source node of the transconductance amplifier, see para. [0051], as taught by Al-Hemuyari to AKHAVAN reference, thereby suggesting the obviousness of such a modification.
Regarding claim 2, wherein the transconductance amplifier comprises an input transistor (T1) coupled between the second switch and the first flipped source follower circuit.
Regarding claim 3, wherein a gate of the input transistor is coupled to a first input (vip) of the amplifier.
Regarding claim 4, Al-Hemuyari (Fig. 4), wherein the first flipped source follower circuit ((MFVF1 and MB1), (MFVF2, MB2)) is coupled to a second input (Vi+) of the amplifier, the first input and the second input forming a differential input pair for the amplifier.
Regarding claim 7, AKHAVAN (Fig. 6), further comprising: a second capacitive element (c2) coupled to a second output (vop) of the amplifier; a third switch (T6) coupled between the second capacitive element and the voltage rail (Vdd); and a fourth switch (T4) coupled between the second capacitive element (C2) and the transconductance amplifier.
Regarding claims 11 and 12, wherein claimed configuration is inherently seen in the operation of the AKHAVAN’s circuit, see Fig. 6, paras. [0053]-[0065]: the first switch is configured to be closed during a charging phase of the amplifier to charge the first capacitive element; and the second switch is configured to be closed during a discharging phase of the amplifier to discharge the first capacitive element.
Regarding claim 13, see claims 1, 11, and 12 above.
Regarding claim 14, wherein: charging the first capacitive element (C1) comprises closing a first switch (T5) coupled between a voltage rail (vdd) and the first capacitive element; and discharging the first capacitive element comprises closing a second switch (T3) coupled between the first capacitive element and the transconductance amplifier (T1), see AKHAVAN (Fig. 6), paras. [0053]-[0065].
Regarding claim 15, further comprising: charging a second capacitive element (C2) coupled to a second output (Vop) of the amplifier during the charging phase; generating a second current via the transconductance amplifier, the transconductance amplifier further including a second flipped source follower circuit (MFVF2, MB2), see Fig. 4 of Al-Hemuyari; and discharging the second capacitive element using the second current during the discharging phase, see AKHAVAN (Fig. 6), paras. [0053]-[0065].
Regarding claim 16, wherein: charging the second capacitive element (c2) comprises closing a second switch (T6) coupled between a voltage rail (vdd) and the second capacitive element (C2); and discharging the second capacitive element (C2) comprises closing a second switch (T4) coupled between the second capacitive element and the transconductance amplifier (T2), see AKHAVAN (Fig. 6), paras. [0053]-[0065].
Regarding claim 17, wherein further comprising activating the transconductance amplifier (T1, T2), wherein the discharging phase occurs a time period after the transconductance amplifier is activated, which is considered inherent in the operation of AKHAVAN (Fig. 6), paras. [0053]-[0065].
Regarding claim 20, see claims 1 and 12 above, and further AKHAVAN (Fig. 2) also discloses at least one processor (270m, 288m) and memory (282m/282x).
Allowable Subject Matter
Claims 5, 6, 8-10, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5 and 6, prior art(s) does not disclose the first flipped source follower circuit comprises: a first current source (MIBP); a source follower transistor (MSFP) coupled between the first current source and an output (450) of the first flipped source follower circuit (404), the output of the first flipped source follower circuit being coupled to a source of the input transistor (MIP); and a feedback transistor (MFBP) having a gate coupled to a drain of the source follower transistor (MSFB) and having a drain coupled to a source of the source follower transistor (MSFP).
Regarding claim 8, prior art(s) does not disclose a fifth switch (MSB) coupled between the first output and the second output of the amplifier.
Regarding claims 9 and 10, prior art(s) does not close a second flipped source follower circuit (MFVF2, MB2), and wherein the first flipped source follower circuit and the second flipped source follower circuit share a common current source.
Regarding claim 18, prior art(s) does not disclose sourcing, via a current source, a third current to power the first flipped source follower circuit and the second flipped source follower circuit, wherein the first current and the second current are generated based on the third current.
Regarding claim 19, prior art(s) does not disclose electrically shorting the first output to the second output during the charging phase.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamamoto et al. (20220368299), which is considered to be the closest prior art to the subject matter of claim 1. However, it does not disclose flipped source follower as claimed.
ROH et al. (20230057178) disclose flipped source follower. However, it does not disclose transconductance amplifier as claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JESSICA HAN can be reached on (571) 272-2078. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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