DETAILED ACTION
Claims 1, 13 are amended. Claims 5, 14 are canceled.
Claims 1-4, 6-13, 15-20 are pending.
Priority: August 08, 2023
Assignee: Samsung
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/9/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-4, 6-13, 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1, 13 are rejected for reciting limitations that are unclear, ambiguous and indefinite.
Amended Claim 1 recites, ‘a coherence directory comprising ….addresses for cache of the plurality of computing elements’.
Fig. 1 of the spec shows that each core has its own cache. But the limitation does not recite how the coherence directory stores the addresses of each cache. Therefore the recitation, ‘addresses for cache of the ….computing elements’ is unclear.
The limitation has been copied from the spec. However, it is improper to ignore the incorrect English in the claim just to match an intended, but incorrectly written, limitation in the spec.
Amended Claim 13 also has an issue. Amended Claim 13 recites, ‘sending…., a probe to cache of the plurality of cores….’. Claim 13 does not recite the 1:1 core-cache relationship.
Hence claims 1,13 are rejected for reciting limitations that are unclear, ambiguous and indefinite.
Note: This issue was mentioned in the previous O/A. But it is unresolved.
Hence it is clarified and maintained.
2.Amended Claims 1, 13 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Amended Claim 1 recites, ‘a coherence directory controller configured to send a probe…..in a computation cycle of the….computing elements’.
The spec does not recite this limitation. In Para-0010, the spec recites, ‘….send the probe when the computing elements are busy’.
Spec, Para-0030 recites, ‘where there are periods of computation where the cores or accelerator computes are busy….’.
‘Periods of computation’ refers to time intervals during which processing occurs, rather than a single ‘computation cycle’ or clock cycle. While both are time related, a period includes multiple cycles, whereas a cycle is a single unit of clock time.
Since ‘periods of computation’ is not ‘a computation cycle’, the recitation ‘a computation cycle of the….computing elements’ is unclear. In addition, there is no recitation how to determine ‘a computation cycle of the ….computing elements’.
Claim 5, submitted as part of the original disclosure, recites Para-0010 of the spec. It is unclear why an original correct limitation has been canceled to recite an inconsistent limitation.
Accordingly, claim 1 is rejected for reciting a limitation that is unclear, inconsistent and indefinite. Claim 13 has a similar issue. For examination the spec is used.
3.Amended claims 1,13 are rejected for reciting limitations that are unclear, incorrect, and indefinite.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Amended Claim 1 recites, ‘send a probe….’ And further recites, ‘wherein, based on the probe and an acknowledgement message….’.
The spec does not recite these limitations. The spec recites sending the probe with a purpose, but the amendment does not.
For example, spec, Fig. 2, Para-0043 recites, ‘the method 200 includes a task 210 of sending a command or message (e.g., a probe)…..to determine if a particular address in the coherence directory is in any of the caches of the core(s) and/or accelerator(s)’.
The spec further recites receiving an acknowledgement message in response to sending the address check probe. The amendment does not.
For example, spec, Fig. 2, Para-0044 recites, ‘the method 200 includes a task 220 of receiving an acknowledgement indicating whether or not the address transmitted in task 210 is in any of the caches of the core(s) and/or accelerator(s)’.
Sending a purposeless probe (e.g. ‘Hello’) and receiving an ack message (e.g. ‘Yes’), is unsubstantiated by the spec. Hence, the amendment is incorrect.
The amendment does not disclose Fig. 2 of the spec. Misrepresenting the steps of Fig. 2 prevents the controller from performing the cleanup operation, which is a key feature of the disclosure.
Claim 1, submitted as part of the original disclosure, recites Fig. 2, Paras:0043,0044 of the spec. So it is unclear why an original correct limitation has been amended to recite an incorrect limitation.
Hence amended claim 1 is rejected for reciting limitations that are unclear, incorrect, and indefinite. Claim 13 has a similar issue. The dependent claims are also rejected for failing to cure the deficiency from their respective parent claim by dependency.
4.Claim 10 is rejected for reciting a limitation that is unclear, ambiguous, and indefinite.
Claim 10 recites, ‘….further comprising main memory connected to the cache’.
Fig. 1, spec:Para-0040 recites, ‘….to determine if a particular address in the coherence directory 108 is in any of the caches 105, 106 of the core(s) 103 and/or accelerator(s) 104’.
As shown in Fig. 1, each core has its own cache. Therefore in the recitation, ‘main memory connected to the cache’, it is unclear which ‘cache’ is being referred. Hence claim 10 is rejected for being unclear, ambiguous and indefinite.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-4, 6-13, 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Amended claim 1 is rejected for reciting a limitation for reciting a limitation that lacks written description support in the spec.
Amended Claim 1 recites, ‘a coherence directory controller configured to send a probe ……in a free cycle of the network-on-chip and in a computation cycle of the plurality of computing elements’.
Spec, Para-0030 recites the inventive concept and the main goal of the disclosure. Para-0030 recites ‘opportunistically cleaning’ the directory 108 by controller 109, when the ‘NoC is idle’ and the ‘computing elements are busy’. These are time-based events. Since each event has two states, busy or idle, each event state must be positively determined.
Sending the probe by the controller to perform the ‘opportunistic cleaning’ requires that the controller determine the opportunity/time/window when the NoC is idle and computing elements are busy.
However, the spec does not disclose that the controller can determine the time window when the ‘NoC is idle’ and ‘computing elements are busy’, when the probe is sent. Neither does the spec disclose that ‘another component’ determines the two events and notifies the controller, and then the controller sends the probe. In other words, the spec does not recite that the controller can determine, directly or indirectly, any or both events, when the probe is sent.
Sending the probe is one of key factors that enables the disclosure. And since sending the probe is dependent on the two events, to enable the full scope of the disclosure and support the inventive concept, it is required to disclose how the two events are detected and confirmed to have happened.
The lack of written description in the spec demonstrates that the applicant's possession of the claimed subject matter, especially with respect to determination of NoC idle state and busy computing elements state, to perform ‘opportunistic cleaning’, at the time of filing, was incomplete.
Accordingly, claim 1 is rejected for reciting a limitation that lacks written description support. Claim 13 has a similar issue. The dependent claims are also rejected for failing to cure the deficiency from their respective parent claim by dependency.
2.Amended claim 1 is rejected for reciting a limitation that is unsupported in the spec.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Amended claim 1 recites, ‘wherein…., the coherence directory controller is configured to clean the coherence directory such that the plurality of addresses stored in the coherence directory match with addresses stored in the cache of the….elements’.
The spec does not recite the limitation.
As mentioned above, the probe is purposeless. More importantly, the spec w.r.t. Fig. 2, Para-0045 recites, ‘in response to the acknowledgement of task 220 indicating that the address transmitted in task 210 is not in any of the caches of the cores…., the method 200 includes a task 230 of cleaning the coherence directory to delete (e.g., scrub) that address entry from the coherence directory.’
In Fig. 2, step 230 is the last step. The final outcome of the cleaning is undisclosed in the spec.
In other words, the spec does not disclose that the cleaning the coherence directory by the controller results in the addresses stored in the coherence directory match with addresses stored in the cache of the computing elements.
In summary, the limitation is unsupported by the spec and the figures. It is an unverified extrapolation. Hence the limitation recites new matter and claim 1 is rejected for the same reason. Claim 13 also has the same issue. The dependent claims are also rejected for failing to cure the deficiency from their respective parent claim by dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 11, 13, 15, 19 are rejected under AIA 35 U.S.C. 103as being unpatentable over Salisbury et al (20160350220) in view of Hagersten et al (20200364144) and Morton et al (20070055826).
As per Claim 1, Salisbury discloses a cache-coherent computer system node (Salisbury, [0064,0066 - Fig. 1 shows a data processing apparatus with data handling nodes 10, 12, 14, 16, 18, 20 and interconnect circuitry 30 connected to the nodes. The apparatus/C-C system node can be implemented as a single integrated chip]) comprising:
a network-on-chip (Salisbury, [0052 - A cache coherent data communication device, such as a network-on-chip/NoC or a cache coherent interconnect comprising a cache coherency controller]);
a plurality of computing elements connected in a fully cache-coherent manner in communication with the network-on-chip (Salisbury, [0067 - Fig. 1 is a memory system comprising: a cache coherent data communication device/NoC and a group of one or more cache memories each connected to the cache coherent data communication device]; [0068 – In Fig. 1, nodes such as 12, 14 are processing elements/CPUs having their own respective caches]);
a coherence directory comprising a plurality of addresses for cache of the plurality of computing elements (Salisbury, [0006 - A directory for memory addresses cached by a group of cache memories connectable in a coherent cache structure, wherein each of the cache memories are caching those memory addresses]; [0003 - An m-way associative structure is provided for such a directory]),
a plurality of coherence states of the plurality of addresses (Salisbury, [0008 - The control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control]; [0122 – In Fig. 8, step 810, snoop filter 300 creates a mask which is a representation of the status/state of each cache memory/tag-address detected at step 800]),
and a plurality of tracking vectors (Salisbury, [0091 – In Fig. 5, the snoop directory entry 500 comprises two portions: a tag 510/address and a snoop vector 520]; [0089 - Fig. 4 shows a snoop filter directory 310 organized as an m-way associative group of n×m entries]; [0041 - The snoop vector returned from the snoop filter for the original access indicates caching agents still enabled in the coherency domain]) of the plurality of addresses (Salisbury, [0090 - The directory is m-way associative so that multiple memory addresses map to an associative set of m directory entries]; [0102 - The snoop vectors show each directory entry comprising information derived from the respective cached memory address and information indicating, for each cache memory in the group of cache memories, whether that cache memory is currently caching that memory address]);
a coherence directory controller (Salisbury, [0071 – Fig. 3 shows the operation of a cache coherency controller including a snoop filter]) configured to send a probe (Salisbury, [0080 - A snoop operation consists of sending a message to a cache memory indicated by the directory, to be caching a memory address being accessed by another cache memory and receiving a response indicating if the cache memory is actually caching that memory address]) to the plurality of computing elements in a free cycle ([See 112(a)]) of the network-on-chip and in a computation cycle ([See 112(b)]) of the plurality of computing elements (Salisbury, [See Fig. 1]; [0016 - A group of one or more cache memories each connected to the cache coherent data communication device/NoC]; [0074 – Fig. 3 shows transaction router 320 forming part of the data routing circuitry 60, thereby implying monitoring of data associated with the NoC]; [0082 - If a snoop operation is needed to enquire as to the current status of the data at one or more caches, then the snoop filter 300 carries out that enquiry as a unicast or multicast communication, thereby implying that the caches are busy; Since the snoop operation does not involve data transfer, it implies that the snoop operation occurs in a ‘free cycle’ in the NoC because it is a clock cycle where a NoC link is not currently being used to transfer data]),
wherein based on the probe and an acknowledgement message (Salisbury, [0104 - In Fig. 6, step 620, the cache agent notifies the cache coherency controller 302/snoop filter of the eviction, thereby implying the acknowledgement indicating that the address is not in the cache]), the coherence directory controller is configured to clean the coherence directory (Salisbury, [0043 - Cleaning the directory of entries relating to cache memories no longer under cache coherency control]) such that the plurality of addresses stored in the coherence directory match ([See 112(a)]) with addresses stored in the cache of the plurality of computing elements (Salisbury, [0003 - The snoop filter maintains a directory indicating which memory addresses are held by which caches in the system, thereby implying the ‘match’]; [0104 – In Fig. 6, step 630 the snoop filter deletes the directory entry corresponding to that cache line at that cache, and sets the relevant bit of the snoop vector of that cache line to zero]; [0107 - Fig. 7 shows an operation to release an entry and store a newly created entry in snoop directory]; [0149 – In Fig. 12, step 1220, involves removing some cache memory addresses from the group which are currently caching that memory address and/or adding a cache memory address to the group currently caching that memory address. The directory entry is updated at step 1225 if it is different to the previous directory entry for that memory address, thereby maintaining the ‘match’]).
Hagersten clarifies the architecture, NoC free cycle/idle state and busy state of computing elements as follows,
a network-on-chip (Hagersten, [Fig. 6: NoC 650]);
a plurality of computing elements connected in a fully cache-coherent manner in communication with the network-on-chip (Hagersten, [0057 – In Fig. 6, the nodes are connected together with each other through network on chip/NoC 650 circuit. NoC 650 also connects the nodes to the directory/DIR 660/controller, global LLC 670 and memory 660. DIR plays a central role in the coherence protocol that keep the contents of the caches and the CLBs coherent and consistent, thereby implying that the nodes/elements are connected in a fully cache-coherent way with the NoC]);
a coherence directory controller (Hagersten, [0057 – In Fig. 6, DIR 660/CDC plays a central role in the coherence protocol that keep the contents of the caches and the CLBs coherent and consistent]) configured to send a probe (Hagersten, [0023 - A coherence message/probe which is sent activates the blocking function to block other coherence messages if the other coherence messages are for the same address region as the coherence message]) to the plurality of computing elements (Hagersten, [0023 - The coherence of values of data units stored in the caches is maintained by a distributed cache coherence protocol which sends coherence messages on the network, thereby implying that the coherence protocol involves a a coherence directory controller]) in a free cycle of the network-on-chip (Hagersten, [0171 - Fig. 15: step 1506, block some coherence messages from being sent on the network, thereby implying that NoC is idle/free cycle because there is less network traffic]) and in a computation cycle of the plurality of computing elements (Hagersten, [0171 – In Fig. 15, step 1504, coherence of values of data units stored in the caches is maintained by a distributed cache coherence protocol which sends coherence messages on the network, thereby implying that the computing elements are busy during the computation cycle]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the blocking function of Hagersten into the cache coherence of Salisbury for the benefit of blocking some
coherence messages from being sent on the network. A coherence message which is sent activates the blocking function to block other coherence messages if the other coherence messages are for the same address region as the coherence message thereby reducing the number of NoC transactions (Hagersten, 0023).
Morton clarifies the coherence directory address match as follows,
wherein, based on the probe and an acknowledgement message (Morton, [0015 - Fig. 2 shows a cluster with processors]; [0124-0126 - The eviction of a cache coherence directory entry of a clean line in a cache requires that the cache invalidate its copy. The transaction involves: 1. The copy of the line in the cache is invalidated via the probe, and the eviction is notified when the invalidation is complete/ack message from cache]), the coherence directory controller (Morton, [cache coherence controller+home memory controller/HMC]) is configured to clean the coherence directory (Morton, [0112 - If a directory entry to be purged indicates that the cached line is in the clean state, then the mechanism invalidates the memory line in each of the remote caches in which the line is cached]; [0129 - When the cache coherence directory associated with the cache coherence controller in a cluster determines that it needs to evict an entry which corresponds to one or more remotely cached clean memory lines, it generates a validate block request for the HMC. The HMC then generates invalidating probes to all the local nodes in the cluster. The local nodes invalidate their copies of the memory line and send confirming responses/ack messages to the HMC indicating that the invalidation took place]; [0131 - The cache coherence directory then transmits a ‘source done’ to the MC/HMC in response to which the memory line is freed up for subsequent transactions, thereby implying the cleanup of the memory line(s)]; [0144 - In Fig. 17, the eviction manager 1702 is part of the cache coherence directory 1701 which is a functional block within the cache coherence controller 1700]) such that the plurality of addresses stored in the coherence directory (Morton, [0082 – In Fig. 7, coherence directory 701 includes state information 713, dirty data owner information 715, and an occupancy vector 717 associated with the memory lines 711/addresses]) match with addresses stored in the cache of the plurality of computing elements (Morton, [0107 - The coherence directory is an associative memory which associates the memory line addresses with their remote cache locations, thereby indicating the ‘match’]; [0091 - Cache coherence controller updates the coherence directory during various transactions, thereby implying the match after the cleanup]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the cache coherence controller/PFU of Morton into the cache coherence of Salisbury, Hagersten for the benefit of using a coherence directory where global memory line state information is maintained and accessed by a memory controller or a cache coherence controller in a particular cluster. The coherence directory tracks and manages the distribution of probes as well as the receipt of responses (Morton, Para-0080).
As per Claim 6, the rejection of claim 1 is incorporated, and Salisbury discloses,
wherein the coherence directory controller (Salisbury, [0009,0010 - A cache coherency controller/CCC stores a directory 310 indicating memory addresses cached by a group of cache memories connectable in a coherent cache structure]) is configured to send the probe not in response to a command from the plurality of computing elements (Salisbury, [0082 - When a potential snoop operation is initiated, snoop filter 300 consults directory 310 to detect whether the information in question is held in one or more of the caches. If a snoop operation is indeed needed to enquire as to the current status of the data at one or more caches, then the snoop filter 300 can carry out that enquiry as a unicast or multicast communication, thereby implying that the CCC sends the probe not in response to a command from the plurality of computing elements]).
As per Claim 11, the rejection of claim 1 is incorporated, and Salisbury, discloses,
an interconnect (Salisbury, [Fig. 1: interconnect circuitry 30]),
wherein the coherence directory controller (Salisbury, [0006 - A cache coherency controller comprising a directory for memory addresses cached by a group of cache memories connectable in a coherent cache structure]) is configured to send the probe (Salisbury, [0080 - A snoop operation sends a message to a cache memory which is indicated, by the directory, to be caching a memory address being accessed by another cache memory]) over the interconnect (Salisbury, [0064 – In Fig. 1, the interconnect circuitry comprises a plurality of interfaces 40, 42, 44, 46, 48, 50 each associated with a respective one of the data handling nodes, and data routing circuitry 60 for controlling and monitoring data handling transactions as between the various data handling nodes]).
As per Claim 13, it is similar to claims 1-4 and therefore the same rejections are incorporated.
As per Claim 15, it is similar to claim 6 and therefore the same rejections are incorporated.
As per Claim 19, it is similar to claim 11 and therefore the same rejections are incorporated.
Claims 2-4, 7, 9, 12, 16, 18, 20 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Salisbury et al (20160350220) in view of Hagersten et al (20200364144), Morton et al (20070055826) and Daya et al (‘SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering’, IEEE, 2014, Pgs. 1-13) and
As per Claim 2, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the plurality of computing elements is homogenous and comprises a plurality of cores (Daya, [Pg. 7, Col. 1, Sec. 4 - In Fig. 5, the 36-core fabricated multicore processor is arranged in a grid of 6×6 tiles]; [Pg. 2, Col. 1, Abstract,Para-3 - Scorpio architecture comprises 36 Freescale e200 Power Architecture cores]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using Scorpio, an ordered mesh NoC architecture with a separate fixed-latency, buffer-less network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered (Daya, Abstract).
As per Claim 3, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the plurality of computing elements is homogenous and comprises a plurality of accelerators (Daya, [Pg. 7, Col. 2, Table 1 - FPGA controller 1× Packet-switched flexible data-rate controller]; [Pg. 5, Col. 1, Para-2 - Allow requests to fork through multiple router output ports in the same cycle, thus providing efficient hardware broadcast support]; [Pg. 7, Col. 2, Para-4.1, Para-2 - Snooping hardware is present at both L1 and L2 caches]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using Scorpio, an ordered mesh NoC architecture with a separate fixed-latency, buffer-less network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered (Daya, Abstract).
As per Claim 4, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the plurality of computing elements is heterogeneous (Daya, [Pg. 3, Col. 2, Sec. 3, Para-2 - The broadcast coherence requests from different source nodes may arrive at the network interface controllers/NIC of each node in any order]) and comprises a combination of a plurality of cores (Daya, [Pg. 7, Col. 1, Sec. 4 - In Fig. 5, the 36-core fabricated multicore processor is arranged in a grid of 6×6 tiles]; [Pg. 2, Col. 1, Abstract,Para-3 - Scorpio architecture comprises 36 Freescale e200 Power Architecture cores]) and a plurality of accelerators (Daya, [Pg. 7, Col. 2, Table 1 - FPGA controller/accelerator 1× Packet-switched flexible data-rate controller]; [Pg. 5, Col. 1, Para-2 - Allow requests to fork through multiple router output ports in the same cycle, thus providing efficient hardware broadcast support]; [Pg. 7, Col. 2, Para-4.1, Para-2 - Snooping hardware/accelerator is present at both L1 and L2 caches]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using Scorpio, an ordered mesh NoC architecture with a separate fixed-latency, buffer-less network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered (Daya, Abstract).
As per Claim 7, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the probe is incorporated into a standard coherence protocol (Daya, [Pg. 7, Table 1 - Coherence protocol MOSI]; [Pg. 7, Col. 2, Sec. 4.2 - The standard MOSI protocol is adapted to reduce the writeback frequency and to disallow the blocking of incoming snoop requests/probes]; [Pg. 3, Col. 2, Sec. Notification Network - For every coherence request/snoop/probe sent on the main network, a notification message encoding the source node’s ID/SID is broadcast on the notification network to notify all nodes that a coherence request from this source node is in-flight and needs to be ordered]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using the standard MOSI protocol to reduce the writeback frequency and to disallow the blocking of incoming snoop requests. To achieve this, an additional O_D state instead of a dirty bit per line is added to permit on-chip sharing of dirty data (Daya, Pg. 7, Col. 2, Last Para).
As per Claim 9, the rejection of claim 7 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the coherence directory controller is configured to send the probe utilizing an existing probe/snoop channel (Daya, [Pg. 7, Col. 2, Table-1 - Channel width 137 bits (Ctrl packets – 1 flit, data packets – 3 flits)]; [Pg. 5, Col. 2, Para-1 - To prevent the deadlock scenario, one reserved virtual channel/rVC is added to each router and NIC, reserved for the coherence request/probe with SID equal to ESID of the NIC attached to that router]) of the standard coherence protocol (Daya, [Pg. 7, Col. 2, Sec. 4.2:Coherence Protocol - The standard MOSI protocol is adapted to reduce the writeback frequency and to disallow the blocking of incoming snoop requests]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using the standard MOSI protocol to reduce the writeback frequency and to disallow the blocking of incoming snoop requests. To achieve this, an additional O_D state instead of a dirty bit per line is added to permit on-chip sharing of dirty data (Daya, Pg. 7, Col. 2, Last Para).
As per Claim 12, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a cache-coherent system.
Daya further discloses,
wherein the coherence directory controller is configured to send the probe intermittently (Daya, [Pg. 3, Col. 2, Sec. 3, Para-2:Notification Network - Synchronized time windows are maintained, greater than the latency bound, at each node in the system. The notification messages are synchronized and sent only at the beginning of each time window, thus guaranteeing that all nodes received the same set of notification messages at the end of that time window; Here ‘synchronized time windows’ implies sending the probe/message intermittently. Since the claim does not define ‘send the probe intermittently’, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable mesh NoC of Daya into the cache coherence of Salisbury, Hagersten, Morton for the benefit of using Scorpio, an ordered mesh NoC architecture with a separate fixed-latency, buffer-less network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered (Daya, Abstract).
As per Claim 16, it is similar to claim 7 and therefore the same rejections are incorporated.
As per Claim 18, it is similar to claim 9 and therefore the same rejections are incorporated.
As per Claim 20, it is similar to claim 12 and therefore the same rejections are incorporated.
Claims 8, 10, 17 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Salisbury et al (20160350220), Hagersten et al (20200364144), Morton et al (20070055826), Daya et al (‘SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering’, IEEE, 2014, Pgs. 1-13), and Tune (20140281180).
As per Claim 8, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton, Daya disclose the MOSI protocol, an extension of the basic MSI cache coherency protocol.
Tune further discloses the MESI protocol which is also an extension of the basic MSI protocol,
wherein the standard coherence protocol is a MESI protocol (Tune, [0041 - The action of snoop requests in managing data coherence within a system such as in Fig. 1 for coherency control, e.g. MESI, MOESI, ESI, MEI etc., using snoop requests are employed]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the MESI coherency protocol of Tune into the cache coherence of Salisbury, Hagersten, Morton, Daya for the benefit of using MESI for the snoop requests to determine which is the most up-to-date copy of the cache line available and return this to the original requesting cache memory. This snoop request may also invalidate some of the existing copies of the cache line as appropriate (Tune, 0041).
As per Claim 10, the rejection of claim 1 is incorporated, and Salisbury, Hagersten, Morton disclose a main memory.
Tune clarifies,
main memory connected to the cache (Tune, [0040 – In Fig. 1, snoop control circuitry 10 is connected to the level 2 cache memories 8 and serves to receive memory access requests issued to main memory 12 when a cache miss occurs within one of the level 2 cache memories; Please note: Fig. 1 of the spec shows the main memory connected to the cache via the interconnect]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the main memory of Tune into the cache coherence of Salisbury, Hagersten, Morton for the benefit of include a main memory from which the plurality of main cache memories cache data (Tune, 0022).
Daya further clarifies,
main memory connected to the cache (Daya, [Pg. 8, Col. 1, Sec. 4.3 - coherency between L1s, L2s and main memory]; [Pg. 8, Col. 2, Sec. Directory baselines - The ownership bit indicates if the main memory has the ownership; that is, none of the L2 caches own the requested line and the data should be read from main memory]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the main memory of Daya into the cache coherence of Salisbury, Hagersten, Morton, Tune for the benefit of reading the data from the main memory if none of the L2 caches own the requested line (Daya, Pg. 8, Col. 2, Para-Last).
As per Claim 17, it is similar to claim 8 and therefore the same rejections are incorporated.
Response to Arguments
The Applicant's arguments filed on December 09, 2025 have been fully considered, but they are not persuasive. The broad amendments stretch the claim scope beyond what is originally disclosed, resulting in inconsistencies, 112(a)’s and 112(b)’s.
Applicant argues: ‘Because the specification does not describe it as essential for the coherence directory controller to determine the free cycle of the network-on-chip or ….the computation cycle of the compute elements (cores and/or accelerators), these features are not essential and are properly omitted from the claims’. (Rem, Pg. 7)
Response: This argument is incorrect.
Amended claim 1 recites, ‘a coherence directory controller configured to send a probe to….computing elements in a free cycle of the network-on-chip and in a computation cycle of the ….computing elements’. Therefore determining the ‘features’ are not omitted from claim 1.
Claim 1 recites that the probe is sent by the controller to the caches with the intention of cleaning the coherence directory, at a determined time i.e. when the NoC is idle and computing elements are busy.
But the spec does not recite that the controller (or any other component) can determine the time/window when the NoC is idle and the computing elements are busy, when the probe is sent.
The title, Paras-0030,0041,0046 of the spec recite the main advantage of the disclosure. For example, Para-0030 recites, ‘Cleaning the coherence directory during free cycles of the NOC is useful in high-performance computing (HPC) applications where there are periods of computation where the cores or accelerator computes are busy, but the NOC is idle’.
More importantly, Para-0030 recites, ‘During these idle periods the opportunistic cleaning can happen in the background’. Here the ‘opportunity’ or time/window to clean the directory arises when it is determined that the ‘NoC is idle’ and the ‘computing elements are busy’.
Therefore, the controller 109 must determine the ‘opportunity’ when the NoC is idle and the computing elements are busy, and use the ‘opportunity’ to send the probe and eventually clean the directory.
Since the two events are time-based events with two states, idle/busy, the disclosure does not work as intended if the ‘opportunity’ cannot be correctly determined by the controller (directly or indirectly). As a result, the spec does not teach ‘opportunistic cleaning’.
In summary, the spec is a ‘high-level’ document, and lacks the necessary structural, algorithmic, or procedural details to disclose ‘opportunistic cleaning’, the key goal of the disclosure.
The applicant is claiming a result, ‘opportunistic cleaning’, based on two time-based events, that they haven't technically shown is achievable.
Applicant further argues: ‘As described in the present application, "the coherence directory 108 is configured to opportunistically clean itself ….during idle periods of the NOC …. (Paragraph [0041]). (Rem, Pg. 8)
Response: This argument is incorrect.
Amended claim 1 correctly recites, ‘the coherence directory controller is configured to clean the coherence directory’.
As shown in Fig. 1 of the spec, the coherence directory 108 is a passive storage area that stores information/data. For example, Para-0039 of the spec recites, ‘the system 100 includes a coherence directory 108 that contains a list of data addresses of the cached data,….’.
The spec does not recite that the coherence directory 108 has any active circuitry/logic that can make the coherence directory 108 ‘opportunistically clean itself’. The spec fails to provide any corresponding structure/steps, specific algorithms, or working examples to demonstrate the ‘opportunistic self-cleaning’. And as mentioned above, the spec does not teach ‘opportunistic cleaning’ at all.
That said, the coherence directory 108 is passive storage and the coherence directory controller 109 is active logic that cleans coherence directory 108.
Applicant further argues, ‘Accordingly, Salisbury discloses that the agent 335, 345 (which is part of the cache memory 330, 340, respectively) initiates the cache coherency controller 302 to perform the cleaning of the coherence directory’. (Rem, Pg. 10)
Response: This argument is incorrect.
Neither the claim nor the spec recite why the controller sends the probe/snoop (Invalidation message for cleanup).
It is well-known in the prior art that some reasons to send a probe, with reference to the disclosure could be related to managing directory overflow, invalidate obsolete copies, handling silent evictions, forcing write-backs, fix inconsistent states etc.
The combination of Salisbury,Hagersten,Daya disclose that while the controller sends the probe/invalidation message to the caches, usually to force them to give up or invalidate a shared or exclusive copy, caches/agents also communicate changes in their state to the directory to assist in directory maintenance. This further proves that the cited prior art discloses communication between the controller and the computing elements when the computing elements are busy and the NoC is idle (there is no data transfer), so that the controller can send the probe to clean the directory and maintain coherence.
The combination of Salisbury,Hagersten,Daya wherein Salisbury, Fig. 6, Para-0104 recites, ‘At a step 600, a cache eviction is initiated. There are various established reasons for requiring a cache eviction, ….in response to an instruction from the cache coherency controller’. Therefore Salisbury discloses that the eviction is in response to an instruction/probe from the controller.
Applicant further argues, ‘Therefore, the cleaning operation disclosed in Salisbury does not occur opportunistically in a free cycle of the NoC and in a computational cycle of the cache memories 330, 340 because the performance of the computation cycle would preclude the cache memories 330, 340 from communicating with the cache coherency controller 302 to signal the need for a cleaning operation’. (Rem, Pg. 10).
Response: This argument is hypothetical because it relies on features, functions, and technical effects undisclosed in the spec.
There is no disclosure of any ‘signaling’ mechanism involving communication between the controller and another component. As mentioned above and in the 112(a), the spec does not disclose any time-based determination capability such as ‘signal the need for a cleaning operation’ by any component, be it the controller, the coherence directory, the NoC, cores, accelerators, caches etc., and communicate the ‘need’ to the controller to start the cleaning operation. The spec does not disclose ‘opportunistic cleaning’ because it cannot determine the time window when the NoC is idle and the computing elements are busy.
There is no disclosure to determine ‘a computational cycle of the caches’. There is no disclosure to determine ‘the performance of the computation cycle’. There is no disclosure determining ‘if the performance of the computation cycle can allow or prevent the caches from communicating with the controller’.
That said, the argument is not relevant because claim 1 recites, ‘wherein, based on the probe and an acknowledgement message, the coherence directory controller is configured to clean the coherence directory’. Therefore as required by claim 1, the combination of Salisbury, Hagersten disclose the requirement. Please see the O/A.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132