Prosecution Insights
Last updated: August 18, 2026
Application No. 18/432,669

MULTILAYER CAPACITOR

Non-Final OA §103
Filed
Feb 05, 2024
Priority
Apr 05, 2023 — RE 10-2023-0045008
Examiner
RAMASWAMY, ARUN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
680 granted / 804 resolved
+16.6% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
21 currently pending
Career history
838
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
59.9%
+19.9% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 804 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 7, 2026, has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Sato et al. (US Publication 2012/0019099) is relied upon herein to disclose the thickness and width of the component body. . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-8, 11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2013/0194715) in view of Hideyuki (JP6171220B2) and in further view of Sato et al. (US Publication 2012/0019099). In re claim 1, Kim discloses a capacitor body comprising: a first internal electrode (31 – Figure 2, ¶44) and a second internal electrode (32 – Figure 2, ¶44) alternately stacked while being spaced apart from each other, and a dielectric layer (11 – Figure 2, ¶45) interposing the first internal electrode and the second internal electrode (Figure 2), wherein the first internal electrode, the second internal electrode, and the dielectric layer are stacked in a first direction (‘T’ direction – Figure 1, Figure 2), and the capacitor body includes a first surface (S1 – Figure 1, Figure 2, ¶42) and a second surface (S4 – Figure 1, Figure 2, ¶42) facing the first surface in a second direction perpendicular to the first direction (Figure 1, Figure 2), and first (21 – Figure 2, ¶39) and second external electrodes (22 – Figure 2, ¶39) connected to the first internal electrode (31 – Figure 2) and the second internal electrode (32 – Figure 2), respectively, and the first and second external electrodes are disposed on the first surface and the second surface (Figure 2), respectively. Kim further discloses the first internal electrode (31 – Figure 2) has a first end portion (portion of 31 contacting 21 – Figure 2) and the second internal electrode (32 – Figure 2) has a second end portion (portion of 32 contacting 22 – Figure 2). Kim does not disclose wherein the first internal electrode comprises a first end portion protruding from the first surface by 0.5 μm to 5 μm, and wherein the second internal electrode comprises a second end portion protruding from the second surface by 0.5 μm to 5 μm. Hideyuki discloses wherein the first internal electrode comprises a first end portion protruding from the first surface by 0.5 μm to 5 μm (Summary of the Invention ¶10), and wherein the second internal electrode comprises a second end portion protruding from the second surface by 0.5 μm to 5 μm (Summary of the Invention ¶10), and It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. Kim does not disclose wherein the capacitor body has a preset thickness in the first direction, a preset length in the second direction, and a preset width in a third direction perpendicular to the first direction and the second direction, and Wherein the preset thickness of the capacitor body is smaller than the preset width. Sato discloses wherein the capacitor body (10 – Figure 1, ¶27) has a preset thickness in the first direction (‘T’ direction – Figure 1), a preset length in the second direction (‘L’ direction – Figure 1), and a preset width (‘W’ direction – Figure 1) in a third direction perpendicular to the first direction and the second direction (Figure 1), and wherein the preset thickness of the capacitor body is smaller than the preset width (¶74). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the component dimensions and external electrode structure as described by Sato to provide for an electronic component with a reduction in size with improved reliability (¶11: Sato). In re claim 2, Kim inv view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim does not disclose wherein the first end portion and the second end portion are disposed to be offset from each other in the second direction of the capacitor body and alternately protrude from first and second surfaces of the capacitor body, respectively. Hideyuki further discloses wherein the first end portion (protrusion portions of 3 on left surface of 10 – Figure 1) and the second end portion (protrusion portions of 3 on right surface of 10 – Figure 1) are disposed to be offset from each other in the second direction of the capacitor body (10 – Figure 1, Figure 2) and alternately protrude from first and second surfaces of the capacitor body (left and right surfaces of 10 – Figure 1, Figure 2), respectively. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. In re claim 3, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim further discloses a first external electrode (21 – Figure 2) is electrically connected to the first end portion (end portion 31 – Figure 2 ); and the second external electrode (22 – Figure 2) is electrically connected to the second end portion (end portion of 32 – Figure 2). In re claim 4, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 3, as explained above. Kim further discloses wherein the first external electrode (21 – Figure 2) comprises: a first conductive layer disposed on the first surface (S1 – Figure 1, Figure 2) and connected to the first internal electrode (¶42-44); and a first internal plating layer disposed to cover the first conductive layer (¶43), and wherein the second external electrode (22 – Figure 2) comprises: a second conductive layer disposed on the second surface (S4 – Figure 1, Figure 2) and connected to the second internal electrode (¶42-44); and a second internal plating layer disposed to cover the first conductive layer (¶43). In re claim 5, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 4, as explained above. Kim further discloses wherein the capacitor body further includes a third surface and a fourth surface (S3, S6 – Figure 1, Figure 2, ¶42) facing each other in the first direction (‘T’ direction – Figure 1, Figure 2), the first conductive layer comprises: a first connection portion (portion of 21 on S1 – Figure 1, Figure 2) located on the first surface and connected to the first end portion (Figure 2); and a first band portion (portion of 21 on S3, S6 – Figure 1, Figure 2) extending to at least a portion of the third surface (S3 – Figure 1, Figure 2), and the second conductive layer comprises: a second connection portion (portion of 22 on S4 – Figure 1, Figure 2) located on the second surface (S4 – Figure 1, Figure 2) and connected to the second end portion (Figure 2); and a second band portion (portion of 22 on S3, S6 – Figure 1, Figure 2) extending to at least a portion of the third surface (S3 – Figure 1, Figure 2). In re claim 7, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim does not disclose wherein the second end portion comprises a second plating layer. Hideyuki discloses wherein the second end portion comprises a plating layer (Description of the Preferred Embodiments ¶13-14. The internal electrodes can be formed through a plating process.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. In re claim 8, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 7, as explained above. Kim further discloses the second internal electrode layer comprises at least one of nickel (Ni), copper (Cu), tin (Sn), and palladium (Pd) (¶15). Kim does not disclose the second end portion is a second plating layer. Hideyuki discloses the internal electrode is plated, and, thus, the second end portion comprises a second plating layer (Description of the Preferred Embodiments ¶13-14. The internal electrodes can be formed through a plating process.). The combination of Kim and Hideyuki discloses wherein the second end portion is a second plating layer that includes palladium (Pd). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. In re claim 10, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim does not disclose wherein a thickness of the capacitor body in the first direction is smaller than or equal to 150 μm. Sato discloses wherein a thickness of the capacitor body in the first direction is smaller than or equal to 150 μm (¶74). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the component dimensions and external electrode structure as described by Sato to provide for an electronic component with a reduction in size with improved reliability (¶11: Sato). In re claim 11, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 7, as explained above. Kim further discloses wherein each of the first and second internal electrodes (31, 32 – Figure 2) includes a plurality of internal electrodes (Figure 2). In re claim 19, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim further discloses wherein the first internal electrode includes Nickel (Ni), copper (Cu), or both, and palladium (Pd) (¶15). Kim does not disclose wherein the first end portion comprises a first plating layer, and wherein the first plating layer includes palladium (Pd). Hideyuki discloses the internal electrode is plated, and, thus, the first end portion comprises a first plating layer (Description of the Preferred Embodiments ¶13-14. The internal electrodes can be formed through a plating process.). The combination of Kim and Hideyuki discloses wherein the first plating layer includes palladium (Pd). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2013/0194715) in view of Hideyuki (JP6171220B2) and in further view of Sato et al. (US Publication 2012/0019099) and in further view of Kim ‘559 et al. (US Publication 2020/0312559). In re claim 6, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 4, as explained above. Kim does not disclose the first external electrode further comprises a first external plating layer disposed to cover the first internal plating layer; and the second external electrode further comprises a second external plating layer disposed to cover the second internal plating layer. Kim ‘559 discloses the first external electrode (130 – Figure 3, ¶39) further comprises a first external plating layer (133 – Figure 3, ¶57) disposed to cover the first internal plating layer (132 – Figure 3, ¶57); and the second external electrode (140 – Figure 3, ¶39) further comprises a second external plating layer (143 – Figure 3, ¶39) disposed to cover the second internal plating layer (142 – Figure 3, ¶39). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the multiple plating layers improve corrosion resistance and mounting characteristics. In re claim 18, Kim in view of Hideyuki and in further view of Sato and in further view of Kim ‘559 discloses he multilayer capacitor of claim 6, as explained above. Kim does not disclose wherein the first external plating layer includes an end portion that covers (i) an end of the first conductive layer, and (ii) contacts the capacitor body, wherein the first external plating layer overlaps both the first internal electrode and the second internal electrode. Kim ‘559 discloses wherein the first external plating layer (133 – Figure 3) includes an end portion that covers (i) an end of the first conductive layer (131 – Figure 3, ¶58) , and (ii) contacts the capacitor body (110 - Figure 3, ¶37), wherein the first external plating layer (133 – Figure 3) overlaps both the first internal electrode and the second internal electrode (121, 122 – Figure 3, ¶49). Kim does not disclose wherein the first surface is etched. Hideyuki discloses the first surface is etched (Description of the Embodiments ¶6). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the protruding portions of Hideyuki to increase the adhesion between the internal electrode and external electrode of the electronic device. Kim does not disclose wherein the first surface is laser etched. However, this claim is considered to be a product by process claim since the claim language is directed to the step required to form the protruding internal electrodes. Therefore, this step has been given no patentable weight since it has been held that the determination of patentability in a product-by-process claim is based on the product itself, even though the claim may be limited and defined by the process. That is, the product in such a claim is unpatentable if it is the same as or obvious from the product of the prior art, even if the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 697, 227 USPQ 964, 966 (Fed. Cir. 1985). A product-by-process limitation adds no patentable distinction to the claim, and is unpatentable if the claimed product is the same as a product of the prior art. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2013/0194715) in view of Hideyuki (JP6171220B2) and in further view of Sato et al. (US Publication 2012/0019099) and in further view of Choi (US Publication 2015/0109718). In re claim 9, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim does not disclose wherein a surface roughness of the capacitor body is in a range of 0.2 μm to 1 μm. Choi discloses wherein a surface roughness of the capacitor body is in a range of 0.2 μm to 1 μm (Claim 12, Table 4). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the component body surface roughness characteristics of Choi to improve the mechanical strength of the device when embedded in a printed circuit board (¶115-116: Choi). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication 2013/0194715) in view of Hideyuki (JP6171220B2) and in further view of Sato et al. (US Publication 2012/0019099) and in further view of Chae et al. (US Publication 2015/0022943). In re claim 10, Kim in view of Hideyuki and in further view of Sato discloses the multilayer capacitor of claim 1, as explained above. Kim does not disclose wherein a thickness of the capacitor body in the first direction is smaller than or equal to 150 μm. Chae discloses wherein a thickness of the capacitor body in the first direction is smaller than or equal to 150 μm (¶46). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the dielectric layer thickness, and thus thickness of the component body, to achieve a device having desired capacitance and miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US Publication 2014/0185189) [¶16], Figure 1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571) 270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Feb 05, 2024
Application Filed
Oct 02, 2025
Non-Final Rejection mailed — §103
Dec 30, 2025
Response Filed
Feb 11, 2026
Final Rejection mailed — §103
May 07, 2026
Request for Continued Examination
May 11, 2026
Response after Non-Final Action
Jun 03, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
97%
With Interview (+12.4%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 804 resolved cases by this examiner. Grant probability derived from career allowance rate.

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