DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 19, 2026 has been entered.
Response to Amendment
Applicant’s Amendment filed February 19, 2026 has been fully considered and entered.
Response to Arguments
Applicant's arguments filed March 7, 2026 have been fully considered but they are not persuasive.
Applicant traverses the rejections of claims 1-9 and 11 under 35 U.S.C. 103 over Chang in view of Raghunathan. Claim 1 has been amended to recite the features of previously pending claim 2. Specifically, claim 1 has been amended to recite that the redistribution layer includes a passivation layer and a dielectric material layer. Claim 1 has also been amended to recite that the passivation layer is disposed on each of the layer of mold compound material, the photonics chip, and the optical waveguide.
Applicant states that In rejecting previously pending claim 2, the Office admits that Chang does not disclose the redistribution layer, including the passivation layer, formed over the optical waveguide. Therefore, the Applicant understands that the Office has asserted a teaching of the passivation layer by Raghunathan. However, the Office has not indicated how Raghunathan supposedly teaches or suggests the passivation layer as recited in previously pending claim 2, and now recited in currently amended claim 1. The Applicant submits that Raghunathan does not teach or suggest the passivation layer as recited in amended claim 1. In fact, the term "passivation layer" does not even appear in Raghunathan.
As explained in the rejection set forth previously and repeated below, Chang discloses that the redistribution layer includes a passivation layer (322) and a dielectric material layer (324), the passivation layer (322) disposed on each of the layer of mold compound material (106), the photonics chip (102). Chang fails to teach that the redistribution layer, including the passivation layer, is formed over the optical waveguide.
Raghunathan teaches that the an electrical redistribution layer (354, 326) may extend over the optical die (322) and waveguide (336). Thus, it would be obvious to form the redistribution layer of Chang, including the passivation layer, over the optical waveguide.
The pertinent question is not whether the cited prior art specifically uses the term “passivation layer”, but rather what is a passivation layer and does the prior art disclose or teach that?
Passivation layer is a well-known, commonly used term in the art. For reference, E. Kohn (“Harsh environment materials”, Y.B. Gianchandani, O. Tabata, H. Zappe (Eds.), “Comprehensive Microsystems”, Elsevier, Oxford (2008), pp. 131-181) has been provided. Passivation layers are discussed in section 1.06.5.3.3. Passivation layers are protective layers that are generally disposed over active semiconductor surfaces and which are known to be formed by dielectric layers. Some example materials are given.
Looking to the present application, paragraph [0085] simply tells us that a passivation layer (410) is formed over the mold compound (404), photonics chip (101A) and optical waveguide (402) and that it may be formed of polyimide material, a nitride material, an epoxy material, or other materials. There is no other description of the passivation layer. The limited description does not conflict with the commonly understood description and it’s clear that dielectric materials meet the requirements. Haven not been given any special description or definition, it appears that applicant is relying on the common knowledge of passivation layers to support the disclosure.
Chang discloses a dielectric passivation layer (322; see paragraph 37) over the photonics chip (102), and molding compound (106). Raghunathan teaches that a redistribution layer includes electrical contacts (326, 354) within dielectric material layers (342; see paragraph 41), which maybe include a build-up of multiple dielectric layers (see paragraph 41). Thus, Raghunathan discloses a passivation layer (dielectric layer) over the chip and waveguide.
Applicant states that per MPEP 2142, "The Supreme Court in KSR Int'lCo. v. Teleflex Inc., 550 U.S. 398, 418, 82 USPQ2d 1385, 1396 (2007) noted that the analysis supporting a rejection under 35 U.S.C. 103 should be made explicit. The Federal Circuit has stated that "rejections on obviousness cannot be sustained with mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness." In re Kahn, 441 F.3d15 977, 98 78 USPQ2d 1329, 1336 (Fed. Cir. 2006); see also KSR, 550 U.S. at 418, 82 USPQ2d at 1396 (quoting Federal Circuit's statement in Kahn with approval)."
Please see the discussion above regarding what a passivation layer is understood to be. The examiner notes that since the specification of the present application did not provide a detailed definition of what the present passivation layer is, and the term passivation layer is well-known and commiserate in scope with a protective dielectric layer, the examiner did not provide a further explanation or even contemplate that one was needed. However, a reference has been provided above to illustrate that passivation layers are standard in the art and are known to be formed of dielectric material.
The Applicant submits that the Office has not provided articulated reasoning with rational underpinning to explain how Raghunathan supposedly teaches or suggests the passivation layer as was recited in previously pending claim 2, and is now recited in currently amended claim 1. The Applicant submits that the combination of Chang and Raghunathan does not teach or suggest the passivation layer as recited in amended claim 1, particularly in combination with the other features of amended claim I when considered as a whole. Therefore, the combination of Chang and Raghunathan does not teach or suggest all features of amended claim 1, as required to render the claim prima facie obvious under 35 U.S.C. 103. The Office is requested to withdraw the rejection of amended claim 1 under 35 U.S.C. 103.
The examiner disagrees. The office action pointed to the dielectric layers of the cited prior art that are positioned above the chip and the waveguide as the passivation layers. Applicant has not explained why the dielectric layers are not passivation layers.
Applicant states that because a dependent claim incorporates all features of its independent claim, the dependent claim is patentable for at least the same reasons as its independent claim. Therefore, without conceding the issue of patentability for other reasons, the Applicant submits that each of dependent claims 3-11 is patentable for at least the same reasons as its independent claim.
The examiner disagrees for the reasons discussed above.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0006304 A1) in view of Raghunathan et al. (US 2019/0302379 A1).
Regarding claims 1, 3-7, 11; Chang et al. discloses a vertical integrated photonics chiplet assembly (see Figure 3M), comprising:
a layer of mold compound material (molding compound 106);
a photonics chip (integrated photonic structure, IPS, 102) disposed within the layer of mold compound material (106), the photonics chip (102) including optical coupling devices (mode converter 121) positioned at a side surface of the photonics chip (102; see Figure 3M);
a redistribution layer (the redistribution layer includes layers 322, 323, 324, and 324; see Figures 3G and 3M) formed over a top surface of the layer of mold compound material (106) and over the photonics chip (102);
an external device (processor die 112, EIC 114) connected to a top surface of the redistribution layer (322/323/324/325), the redistribution layer including electrically conductive contacts (325) and electrically conductive interconnect lines (323) that electrically connect the photonics chip (102) to the external device (112, 114); and
an electrically conductive path (the electrical conductive path formed by TSVs 108 connected to the conductive layer 323 and contact pads of the redistribution layer 322/323/324/325) extending from the external device (112, 114) through an entire vertical thickness of both the redistribution layer (322/323/324/324) and the layer of mold compound material (106), the electrically conductive path including an electrically conductive contact pad (the bottom portions of TSVs 108 form an electrically conductive contact pad) exposed at a bottom surface of the mold compound material (106);
wherein the redistribution layer includes a passivation layer (322) and a dielectric material layer (324), the passivation layer (322) disposed on each of the layer of mold compound material (106), the photonics chip (102);
further comprising: a dielectric material layer (306) disposed on a surface of the layer of mold compound material (106) that is opposite the layer of mold compound material from the redistribution layer (322/323/324/325);
further comprising: at least one electrically conductive pillar (108; see Figures 3G and 3M) formed through the layer of mold compound material (106); and at least one electrically conductive contact pad (electrical pad formed by surface of 323 touching pillar 108) disposed on the layer of mold compound material (106) and respectively electrically connected to the at least one electrically conductive pillar (108), each of the at least one electrically conductive contact pad (electrical pad formed by surface of 323 touching pillar 108) exposed through a corresponding opening in the dielectric material layer (322/324);
wherein the external device (112 and/or 114) is a system-on-chip semiconductor chip (see paragraph 23);
wherein the external device (112 and/or 114) is an electro-optical semiconductor chip (see paragraph 23);
further comprising: a dielectric underfill material disposed between the external device and the redistribution layer (see paragraph 45).
Chang does not disclose:
an optical waveguide disposed within the layer of mold compound material, the optical waveguide optically coupled to the optical coupling devices positioned at the side surface of the photonics chip;
the redistribution layer, including the passivation layer, formed over the optical waveguide; or
the external device being flip-chip connected;
wherein the photonics chip and the optical waveguide are positioned in a side-by-side contacting manner within the layer of mold compound material.
Raghunathan et al. teaches that a vertical integrated photonics chiplet assembly (100, 200, 370; see Figures 1, 2 and 3H) may include an optical die (322) and a waveguide (336) encapsulated in a material layer (342; see Figure 3H), the waveguide (336) located between the optical die (322) and a fiber (372), wherein the optical die (322) and the optical waveguide (336) are positioned in a side-by-side contacting manner within the encapsulation material layer (342); and an electrical redistribution layer (354, 326) over the optical die (322) and waveguide (336) and external devices (electrical components 214 and 216) flip-chip connected (see paragraph 26 and 44) thereto.
Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to incorporate an optical waveguide disposed within the layer of mold component (106) of Chang et al. and located between the photonics chip (102) and the fiber (124), wherein the photonics chip and the optical waveguide are positioned in a side-by-side contacting manner within the layer of mold compound material, the optical waveguide coupled to the optical coupling devices (121) positioned at the side surface of the photonics chip (102) for the purpose of providing additional optical routing and/or waveguide-based modulation elements in a known manner, to form the redistribution layer, including the passivation layer, over the optical waveguide for the purpose of controlling optical routing and/or waveguide-based modulation elements provided formed by the optical waveguide, and to flip-chip mount the electrical chips (112 and 114) for the purpose of using a standard, commonly known alternative connection method, since all of these elements are taught by Raghunathan et al., and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding claim 8; Chang et al. further discloses that the photonics chip (102) is electrically connected electrical devices (112 and 114), but does not specifically disclose that the photonics chips is electrically connected to an electrical supply within the external device, wherein the photonics chip is electrically connected to reference ground potential within the external device. Raghunathan et al. teaches that the interconnects may provide electrical pathways for signals between electric components (integrated circuits) and input/output connections on the package to and from the electronic components, including signals connections, power deliver and ground connections (see paragraph 23). The examiner notes that the provision of power and ground connections is routinely required for successful operation of optoelectronic components in photonic integrated circuits. Thus, before the effective filing date of the present invention, a person would have found it obvious to provide the photonic chips such that the chip is electrically connected to an electrical supply within the external device, wherein the photonics chip is electrically connected to reference ground potential within the external device for the purpose of providing electrical power to the device for operation and grounding the device to avoid damage to the device or a user, since this is a known prior art arrangement and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding claim 9; Chang further discloses that an array of fibers (124A, 124B) may be provided for connection to multiple waveguides (see Figure 6A). Additionally, the examiner notes that fiber optic array units, commonly abbreviated FAUs, are known to a person of ordinary skill in the art. Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to further provide an optical fiber array including a plurality of optical fibers optically coupled to the optical coupling devices positioned at the side surface of the photonics chip (102) of Chang et al. for the purpose of transmitting and receiving a desired number of optical signals to and/or from a desired number of optical waveguides, since this is a known prior art arrangement and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0006304 A1) in view of Raghunathan et al. (US 2019/0302379 A1), and in further view of Nakama et al. (US 2002/0131700 A1).
Regarding claim 10; Chang et al. and Raghunathan et al. suggest the vertical integrated photonics chiplet assembly as recited in claim 9 (see the rejections of claims 1-9 above), but does not disclose that the optical fiber array includes optical lensing components for focusing light into the optical coupling devices positioned at the side surface of the photonics chip. Nakama et al. teaches that an optical fiber array unit (see Figure 1) may be provided with lensing components (11) for focusing light (see Figure 1). Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to further incorporate an optical fiber array including optical lensing components for focusing light into the optical coupling devices positioned at the side surface of the photonics chip in the invention of Chang et al. for the purpose of minimizing optical loss and improving coupling efficiency, since this is a known prior art arrangement and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE R CONNELLY whose telephone number is (571)272-2345. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874