Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 07/28/2026 have been fully considered but they are not persuasive.
Applicant argues that paragraph [0171] of Ippolito is directed to a temperature independent curvature corrected reference voltage and does not teach a correction voltage complementary to absolute temperature. The examiner respectfully disagrees. Ippolito teaches the voltage drop VBE across the second diode connected transistor (T2) having a CTAT characteristics (see paras. [0070], [0110]) that exhibits a non-linear temperature dependence (see para. [0097]), and a voltage difference deltaVBE, comp of the voltage drops across the second (T2) and third (T3) diode-connected transistors (see para. 123) scaled by a gain factor β is chosen to correct the curvature (see paras. [0169] – [0170]). The reference voltage VREF_LIN = VBE + Vβ + VPTAT (see para. [0151]) is constant for any value of temperature (see para. [0171]), and VPTAT is linearly dependent on absolute temperature (see paras. [0069], [0147]). The sum VBE + Vβ is therefore necessarily a constant minus a linear PTAT term, which is a corrected voltage complementary to absolute temperature that has negligible non-linearity across temperature.
Applicant further argues that paragraphs [0192] and [0389] – [0391] do not disclose the bitstream controlled operation. Ippolito teaches that the value Vx is VPTAT when bs= “0” and –(VBE + Vβ) when bs = “1” (see para. [0192]), that the integrator (452) integrates Vx (see para. [0194]), and that the switching arrangement (50, 51) causes either the sum Vβ + VBE or VPTAT to be provided to the integrator (452) depending on the updated bitstream value (see paras. [0222], [0228]). In FIG. 7 this is performed by the network of switched capacitors (52), which samples the selected signals and transfer the charge onto combination nodes (520a, 520b) coupled to the integrator (452) (see paras. [0245], [0255] – [0256], [0263] – [0265]). Applicant’s statement that this is “different” identifies no structural or functional difference from the claimed operation.
Regarding claims 8 and 15, Applicant relies on the same arguments. Claims 8 and 15 do not recite a corrected voltage having negligible non-linearity across temperature, and claim 15 recites only a first voltage, a second voltage, and a correction voltage.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, 8 – 12, 15 and 18 – 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ippolito et al. (US 2019/0316973 A1 – hereafter “Ippolito”).
As per claim 1, Ippolito teaches the following:
A sigma-delta modulated analog to digital converter (451) (see para [0362]), comprising:
voltage generation circuitry configured to generate a voltage proportional to absolute temperature (see para [0368]), an uncorrected voltage complementary to absolute temperature (see para [0070]), and a correction voltage that when added to the uncorrected voltage complementary to absolute temperature yields a corrected voltage complementary to absolute temperature that has negligible non-linearity across temperature (see para [0171]);
a switched capacitor circuit configured to selectively sample voltages produced by the voltage generation circuitry and provide the sampled voltages to inputs of an integrator (see para [0391]);
a quantization circuit configured to quantize outputs of the integrator to produce a bitstream (see para [0200]);
wherein the switched capacitor circuit cooperates with the integrator under control of the bitstream to cause the integrator to integrate the voltage proportional to absolute temperature, or add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce the corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature, depending upon a most recent bit of the bitstream (see para [0192]);
and a low pass filter and decimator configured to filter and decimate the bitstream produced by the quantization circuit to produce a voltage indicative of a temperature of a chip into which the sigma-delta modulated analog to digital converter is placed (see paras [0096], [0176]).
As per claim 2, Ippolito teaches the following:
The sigma-delta modulated analog to digital converter of claim 1, wherein the switched capacitor circuit cooperates with the integrator under control of the bitstream to: when the most recent bit of the bitstream is a first value, cause the integrator to integrate the voltage proportional to absolute temperature; and when the most recent bit of the bitstream is a second value, add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce the corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature (see paras [0192], [0389] – [0390]).
As per claim 3, Ippolito teaches the following:
The sigma-delta modulated analog to digital converter of claim 2, wherein the first value is a logical zero and the second value is a logical one (see para [0192] where the formula for
V
x
where bitstream values “bs” are equal to zero and one, [0295], [0313]).
As per claim 4, Ippolito teaches the following:
The sigma-delta modulated analog to digital converter of claim 1, wherein the voltage generation circuitry includes bipolar junction transistors configured to generate the voltage proportional to absolute temperature and the uncorrected voltage complementary to absolute temperature through differential current densities (see para [0049] – [0050], [0067], [0070]).
As per claim 5, Ippolito teaches the following:
The sigma-delta modulated analog to digital converter of claim 4, wherein the voltage generation circuitry generates the correction voltage by adjusting the differential current densities through additional bipolar junction transistors to compensate for non-linearities in the uncorrected voltage complementary to absolute temperature (see para [0115] – [0116], [0171]).
As per claim 6, Ippolito teaches the following:
The sigma-delta modulated analog to digital converter of claim 1, wherein the switched capacitor circuit includes adjustable capacitances to scale the sampled voltages according to a given ratio to compensate for variations in temperature measurement across different temperature ranges (see para [0257], [0249]).
As per claim 8, Ippolito teaches the following:
A method, comprising:
generating a voltage proportional to absolute temperature (see para [0398]);
generating an uncorrected voltage complementary to absolute temperature (see para [0070]);
generating a correction voltage (see para [0400]);
selectively sampling the voltage proportional to absolute temperature, the uncorrected voltage complementary to absolute temperature, and the correction voltage, and providing those sampled voltages to inputs of an integrator (see para [0391]);
quantizing outputs of the integrator to produce a bitstream (see para [0404]);
causing the integrator to integrate the voltage proportional to absolute temperature, or causing the integrator to add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce a corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature, depending upon a most recent bit of the bitstream (see para [0192]);
and filtering and decimating the bitstream to produce a voltage indicative of a temperature of a chip on which the method is performed (see para [0206]).
As per claim 9, Ippolito teaches the following:
The method of claim 8, wherein the integrator is caused to integrate the voltage proportional to absolute temperature when the most recent bit of the bitstream is a first value, and caused to add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce the corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature when the most recent bit of the bitstream is a second value (see paras [0192], [0389] – [0390]).
As per claim 10, Ippolito teaches the following:
The method of claim 9, wherein the first value is a logical zero and the second value is a logical one (see para [0192] where the formula for
V
x
where bitstream values “bs” are equal to zero and one).
As per claim 11, Ippolito teaches the following:
The method of claim 8, wherein the correction voltage, when added to the uncorrected voltage complementary to absolute temperature, yields the corrected voltage complementary to absolute temperature as having negligible non-linearity across temperature (see para [0171], [0350]).
As per claim 12, Ippolito teaches the following:
The method of claim 8, further comprising adjusting the sampling of the voltage proportional to absolute temperature and the corrected voltage complementary to absolute temperature based on a ratio of sampling capacitors to enhance accuracy (see para [0257] – [0258]).
As per claim 15, Ippolito teaches the following:
A temperature sensing circuit, comprising:
a switched capacitor circuit configured to selectively sample voltages produced by voltage generation circuitry and provide the sampled voltages to inputs of an integrator (see para [0391]);
and a quantization circuit configured to quantize outputs of the integrator to produce a bitstream (see para [0200]);
wherein the switched capacitor circuit cooperates with the integrator under control of the bitstream to cause integration of a first voltage, or cause addition of a correction voltage to a second voltage to produce a corrected voltage and then integrate the corrected voltage, depending on a most recent bit of the bitstream (see para [0192], [0389] – [0390]).
As per claim 18, Ippolito teaches the following:
The temperature sensing circuit of claim 15, wherein the switched capacitor causes integration of the first voltage when the most recent bit of the bitstream is a first value and causes integration of the corrected voltage when the most recent bit of the bitstream of a second voltage (see paras [0192], [0389] – [0390]).
As per claim 19, Ippolito teaches the following:
The temperature sensing circuit of claim 18, wherein the first value is a logical zero and the second value is a logical one (see para [0192] where the formula for
V
x
where bitstream values “bs” are equal to zero and one).
As per claim 20, Ippolito teaches the following:
The temperature sensing circuit of claim 15, wherein the voltage generation circuitry is configured to generate the first voltage as a voltage proportional to absolute temperature and the second voltage as an uncorrected voltage complementary to absolute temperature, utilizing bipolar junction transistors configured with certain current densities to achieve temperature sensitivity (see para [0049] – [0050]).
As per claim 21, Ippolito teaches the following:
The temperature sensing circuit of claim 20, further comprising a differential arrangement of bipolar junction transistors through which the correction voltage is generated, each biased with currents that are scaled versions of a reference current, ensuring the correction voltage effectively compensates for non-linearities in the second voltage over a range of temperatures (see para [0115] – [0117]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ippolito in view of Thiagarajan et al. (US 8,040,266 B2 – hereafter “Thiagarajan”).
Regarding claim 7, the claim recites “The sigma-delta modulated analog to digital converter of claim 1, wherein the integrator includes multiple stages to improve resolution by integrating the sampled voltages over a series of integration phases.
Ippolito fails to teach the integrator includes multiple stages to improve resolution by integrating the sampled voltages over a series of integration phases.
Thiagarajan teaches a programmable sigma-delta analog-to-digital convertor having a variable stage integration unit comprising a selectable number of integration stages, wherein the operational order of the integration unit is set according to the number of integrators selected to integrate the analog input signal over a series of integration phrases (see col. 5, lines 9 – 15).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Ippolito in view of Thiagarajan to implement multiple integration stages in the sigma-delta analog-to-digital convertor temperature sensor in order to increase the integration order of the modulator and improve the resolution of the temperature measurement output.
Regarding claim 13, the claim recites “The method of claim 8, further comprising using a multi-stage integrator as the integrator to perform the integration of the sampled voltages, wherein each stage of the integrator contributes to improving signal-to-noise ratio of the bitstream.”
Ippolito fails to teach a multi-stage integrator to perform the integration of the sampled voltages, wherein each stage of the integrator contributes to improving signal-to-noise ratio of the bitstream.
Thiagarajan teaches a programmable sigma-delta analog-to-digital convertor having a variable stage integration unit comprising a selectable number of integration stages, wherein including multiple integration in the sigma-delta modulator and improves the signal-to-noise ratio (see col. 1, lines 25 – 35).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Ippolito in view of Thiagarajan to increase the number of integrator stages in a sigma-delta converter temperature sensor in order to improve the signal-to-noise ratio of the bitstream output and thus improve temperature measurement accuracy.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ippolito in view of Thiagarajan in further view of Makinwa et al. (US 2013/0214952 A1 – hereafter “Makinwa”).
Regarding claim 14, the claim recites “The method of claim 13, further comprising utilizing feedback loops in each stage of the integrator to reduce impact of quantization noise and provide for stable operation.”
Ippolito in view of Thiagarajan fails to teach the utilization of feedback loops in each stage of the integrator to reduce impact of quantization noise and provide for stable operation.
Makinwa teaches a sigma-delta analog-to-digital convertor wherein feedback loops in the integrator stages function as a narrowband, low-noise detector and wherein the design choice of feedback loop parameters ensures stable feedback-loop operation thereby reducing quantization noise through noise shaping (see para [0007], [0010] – [0011]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Ippolito in view of Thiagarajan in further view of Makinwa to utilize feedback loops in each stage of the multi-stage integrator in in order to reduce the impact of quantization noise and provide stable operation of the sigma-delta modulator.
Allowable Subject Matter
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Manuel Castellon whose telephone number is (571)272-4575. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Breene can be reached at 571-272-4107. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MANUEL SALVADOR CASTELLON JR/Examiner, Art Unit 2855
/NATALIE HULS/Primary Examiner, Art Unit 2855
Prosecution Insights