DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments provided on 01/02/2026 have been fully considered and are not found to place the application in a condition for allowance.
Regarding the amended limitations of claim 1, the applicant asserts that Lin does not teach that Tini and Toxide “have different active layer materials from one another” wherein the first pixel transistor (Toxide of Lin) includes an oxide semiconductor active layer and fifth pixel transistor (Tini of Lin) includes a low-temperature polysilicon active layer. Note that Lin teaches in ¶ 55, that Toxide includes an oxide semiconductor active layer: “transistor Toxide is formed using semiconducting oxide (e.g., a transistor with a channel formed from semiconducting oxide such as indium gallium zinc oxide or IGZO)”. Lin further teaches that silicon transistors are formed from an LTPS material. The Office agrees that Lin does not specifically teach that the active layer materials of Tini and Toxide are different. However, upon further search and consideration, this limitation is not found to place the application in a condition for allowance. The following Action provides further details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 14-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., US 2020/0226978 A1, hereinafter “Lin”, in view of Cha et al., US 2021/0158751 A1, hereinafter “Cha”, and further in view of Zhang et al., US 2022/0157239 A1, hereinafter “Zhang”.
Regarding claim 1, Lin teaches a display device (fig. 1, element 10, ¶ 39) comprising: a display panel (fig. 2, element 14, ¶ 14) having a plurality of sub-pixels defined thereon (fig. 2, elements 22, ¶ 43); and at least one gate driver (fig. 2, element 18) comprising a scan driver and an emission control driver configured to control the plurality of sub-pixels (¶ 50), wherein the plurality of sub-pixels comprise: a light-emitting element (fig. 17a, ¶ 57, element 304); a driving transistor (fig. 17a, Tdrive) configured to control the light-emitting element (¶ 56); at least one switching transistor (fig. 17A, see different switching transistors connected to Tdrive) coupled to the driving transistor; a third pixel transistor (fig. 17A, Tem1) configured to transmit a high potential power voltage (VDDEL) to the driving transistor; a fourth pixel transistor (fig. 17A, Tem2) connected between the driving transistor and the light-emitting element; a capacitor (fig. 17A, Cst) connected between a node of the high potential power voltage and a gate electrode of the driving transistor; a fifth transistor (fig. 17A, Tini) connected between the gate electrode of the driving transistor and a node of a first initialization voltage (fig. 17A, Tini between Vini and gate of Tdrive); a sixth pixel transistor (fig. 17A, Tar) connected to an anode of the light-emitting element; and a seventh pixel transistor (fig. 17A, Tobs) connected to a source electrode of the driving transistor, wherein the at least one switching transistor is an oxide semiconductor transistor or a low-temperature poly-silicon transistor (fig. 17A, Toxide), wherein the at least one switching transistor includes a first pixel transistor connected between the gate electrode and a drain electrode of the driving transistor (fig. 17A, Toxide) and a second pixel transistor configured to transmit a data voltage to the driving transistor (fig. 17A, Tdata, ¶ 64), wherein the driving transistor, the third pixel transistor, the fourth pixel transistor, the sixth pixel transistor and the seventh pixel transistor are implemented as p-type transistors (see fig. 17A) and the second pixel transistor is implemented as an n-type transistor so that the data voltage increases when a kickback occurs due to the turn-off of the second pixel transistor (¶ 55-56 wherein Tdata may be implemented as an n-type transistor; note that by configuring Tdata as an n-type transistor, the gate voltage of the transistor transitions from high to low voltage which produces a kickback voltage based on which the outputted data voltage increases according to kickback phenomenon), and wherein the first pixel transistor and the fifth pixel transistor are both n-type transistors (fig. 17A, see Toxide and Tini, ¶ 110), the first pixel transistor including an oxide semiconductor active layer (¶ 110).
Lin does not specifically teach that the at least one gate driver includes a same type of p-type transistor as a p-type transistor of the plurality of sub-pixels.
Cha teaches that the at least one gate driver includes a same type of p-type transistor as a p-type transistor of the plurality of sub-pixels (¶ 89, wherein the transistors in the gate drivers include P-type LTPS transistors and are formed in the same process as that of the pixel circuits).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Lin in view of Cha. The references teach display devices including pixel circuits and scan driving units. Cha further teaches that the transistors are formed in the same process for the pixel circuits and the scan drivers, motivating one of ordinary skill to combine the teachings of Lin in view of Cha in order to simplify the manufacturing process of producing the display devices while reducing the costs associated with such processes.
Lin and Cha do not specifically teach that the first and fifth transistors have different active layer materials from one another and the fifth pixel transistor includes a low-temperature polysilicon active layer.
Zhang, however, clearly teaches that the first and fifth transistors have different active layer materials from one another and the fifth pixel transistor includes a low-temperature polysilicon active layer while the first pixel transistor includes an oxide semiconductor active layer (¶ 61: “the initialization transistor T2 is a silicon transistor, and the compensation transistor T3 is an oxide transistor”).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Lin and Cha, further in view of Zhang. Lin clearly teaches that different types of transistors (such as oxide and silicon p-type and n-type transistors) may be used in a pixel circuit. Zhang teaches a pixel circuit similar to that of Lin and further clearly teaches that the initialization transistor and compensation transistor, while both N-type (see ¶ 62 of Zhang), may be formed of different materials. One would have been motivated to make such a combination because Zhang clearly teaches that such a configuration improves the compensation effect of the driving transistor thus ensuring the stable light emission of the light emitting device (¶ 61).
Regarding claim 14, Lin teaches that the first pixel transistor and the fifth pixel transistor are configured to be turned on at different periods (fig. 17B, see different timings of SC1 and SC4).
Regarding claim 15, Lin teaches that the second pixel transistor is configured to be turned on by a scan signal (Tdata is turned on by scan signal SC2).
Regarding claim 17, Lin teaches that the sixth pixel transistor is configured to transmit an anode reset voltage to the anode (Tar transmits Var which is an anode reset voltage).
Regarding claim 18, Lin teaches that the seventh pixel transistor is configured transmit a second initialization voltage to the source electrode of the driving transistor (Tobs transmits VOBS which is a second initialization voltage, see ¶ 111).
Regarding claim 19, Lin teaches that the sixth pixel transistor and the seventh pixel transistor are configured to be turned on simultaneously (fig. 17A, both are connected to SC3).
Regarding claim 20, Lin teaches that the third pixel transistor and the fourth pixel transistor are configured to be turned on simultaneously (fig. 17A, both are connected to EM).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621