DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Final.
This action is responsive to the following communication: the response filed on 06-25-2026.
Claim Rejections - 35 USC § 112
Claim rejections under USC § 112 during the Non-Final Office Action are withdrawn, in light of the remarks filed on 06-25-2026 by Applicant(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 11/307,773 (hereinafter, “Ring”) in view of U.S. Patent No. 11/921,558 (hereinafter “Udhayan”) and further view of U.S. Publication No. 2023/0254259 (hereinafter “Aravinthan”).
As per claims 1, 3, 20, Ring discloses a system comprising a first one or more circuits to:
receive a packet via a port; (ingress ports by which data packets are received; Fig. 6)
process a packet to identify a second one or more circuits (inter alia: store packets 605 in temporary memory structures referred to as buffers while the packets 605 are waiting to be processed; [Col 18 lines 44-67]. In other words, buffer and queues; Col 18 lines 44-47 ) for determining a forwarding decision for the packet; (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
in response to identifying the second one or more circuits, enable the second one or more circuits to the second one or more circuits; and (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
provide the packet to the second one or more circuits, wherein the second one or more circuits process the packet (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] ) to determine the forwarding decision for the packet. (The forwarding logic 620 of device 600 may process a packet 605 over one or more stages; [Col 18 lines 44-67]
Ring does not distinctly discloses applying apply power to one or more circuits.
However, Udhayan explicitly discloses that. In particular, it discloses the following:
process a header of the packet to identify receive a packet via a port; (incoming network traffic via “PCIe root port 522”; Fig’s 1, 5), a second one or more circuits (Col 9 lines 14-49 state: “the network traffic metadata may be used to identify particular incoming network traffic as being of real-time or non-real-time workloads. Some examples of non-real-time workloads may include file transfer, cloud synchronization, cloud file download, which with this identification can be scheduled on power efficient cores”. In other words, the system may be “be used to provide hardware guided scheduling to identify appropriate core types on which to schedule workloads.” (Col 6 lines 37-41. Another example, the system may select “heterogenous architecture scheduling may be based at least in part on workflow to schedule on performance core and efficient cores”. Col 8 lines 25-27) determining a forwarding decision for the packet; ( Col 1 lines 40-52 states “scheduler may become aware of network traffic and base power management policy and/or scheduling decisions based at least in part on this information”.
in response to identifying the one or more circuits, enable the second one or more circuits by applying power to the second one or more circuits; and (Col 7 Lines 33-36 state: “PCU 514 may control power consumption of the cores based at least in part on hardware guided scheduling (HGS) information 516 and/or energy performance preference (EPP) information 518, along with network traffic metadata.” Alternatively, “SoC power savings may be realized by selecting an appropriate CPU frequency specific to the type of workflow”; Col 8 lines 21-24)
provide the packet to the second one or more circuits. (CPUs, performance core and efficient cores, buffer, cache; Fig’s 6, 9)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring and Udhayan because both references are in the same field of endeavor. Udhayan’s teaching of selectively controlling the power of circuits would enhance Ring's system by enhancing energy efficiency capability and a performance capability to the computer system.
Ring as modified does not distinctly disclose a header
However, Aravinthan discloses that. In particular it discloses the following:
receive a packet via a port; (network ingress port scheduler; Fig. 9)
process a header (processing transport/ULP header; ¶s [0094]-[0105]) of the packet to identify, a second one or more circuits for processing the packet to to determining a forwarding decision for the packet; (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
in response to identifying the second one or more circuits, enable the second one or more circuits; and (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
provide the packet to the second one or more circuits, wherein the second one or more circuits process the packet to determine the forwarding decision for the packet. (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring as modified and Aravinthan because all references are in the same field of endeavor. Aravinthan’s teaching of splitting data packets into portions by reading destination of a packet in the header would enhance Rings' as modified system by allowing the system to process them more efficiently, thus improving computer’s performance.
As per claim 2, Ring as modified discloses a system wherein each of the one or more circuits comprises hardware to perform a logic algorithm associated with forwarding the packet. (Udhayan: Fig. 4 illustrates scheduling associated with traffic classification by using the “hardware and perform necessary actions”. Also, Fig 5 illustrates network packet classifier perform withing the NIC 530) & (Aravinthan: algorithm for scheduling data packets to the appropriate hosts and accelerators; Fig 9 )
As per claims 4, 15, Ring as modified discloses a system wherein identifying the second one or more circuits comprises identifying one or more services required for processing the packet based on the header of the packet. (Udhayan: Network traffic metadata may include information carried in “real-time transport protocol (RTP) headers”; Col 2 lines 17-20) & (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” )
As per claims 5, 16,Ring as modified discloses a system wherein the second one or more circuits are identified based at least in part on a flow associated with the packet. (Udhayan: “packet flow” Col 7 line 66 or “heterogenous architecture scheduling may be based at least in part on workflow’ Col 8 lines 25) & (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” )
As per claims 6, 17, Ring as modified discloses a system wherein the one or more circuits include a first circuit associated with ingress packet processing and a second circuit (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )the first circuit comprising at least a portion of a control plane and the second circuit comprising at least a portion of a packet modifier. (Fig 9 illustrates port scheduler, controlling hosts, embedded management processor, GPUs, FPGAs. These circuits are responsible for forwarding packets to endpoint destination)
As per claims 7, 18, Ring as modified discloses a system wherein the second one or more circuits comprise one or more components and/or data structures of a control plane associated with ingress packet processing, and wherein processing the packet comprises performing ingress processing. (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”. Moreover, at least Fig. 9 illustrates network ingress/egress pipeline and port scheduler, controlling hosts, embedded management processor. These circuits are responsible for forwarding packets to endpoint destination)
As per claims 8, 19, Ring as modified discloses a system wherein the one or more circuits are further to: identify, based on the packet, a third one or more circuits associated with egress processing for processing the packet; enable the third one or more circuits associated with egress processing; and perform egress processing of the packet by applying power to the third one or more circuits; and provide the packet to the third one or more circuits to perform egress processing of the packet. (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”. Moreover, at least Fig. 9 illustrates network ingress/egress pipeline ) & (Udhayan: Col 7 Lines 33-36 state: “PCU 514 may control power consumption of the cores based at least in part on hardware guided scheduling (HGS) information 516 and/or energy performance preference (EPP) information 518, along with network traffic metadata.” Alternatively, “SoC power savings may be realized by selecting an appropriate CPU frequency specific to the type of workflow”; Col 8 lines 21-24)
As per claim 9, Ring as modified discloses a system wherein the second one or more circuits comprise one or more of, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), network interface card (NIC), port logic circuit, serializer/deserializer (SerDes) circuit, and clock tree circuit. (Udhayan: Fig’s 6,8-9 ) & & (Ring: sram; Fig 6. Fpga ; col 16 lines 5-16) & (Aravinthan Fig. 9 illustrates an FPGA, ASIC ¶ [00116] )
As per claim 10, Ring as modified discloses a system wherein the second one or more circuits comprise a subset of the RAM. (Udhayan: DRAM 260 or cache; Fig 2) & , (Ring: sram; Fig 6)
As per claim 11, Ring as modified discloses a system wherein the second one or more circuits comprise one or more components and/or data structures of a packet modifier circuit associated with egress packet processing. (Aravinthan: Fig. 9 illustrates network ingress/egress pipeline ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] (Aravinthan: Fig 9 illustrates port scheduler, controlling hosts, embedded management processor, GPUs, FPGAs. These circuits are responsible for forwarding packets to endpoint destination) )
As per claim 12, Ring as modified discloses a system wherein the one or more circuits comprise one or more of, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), network interface card (NIC), port logic circuit, serializer/deserializer (SerDes) circuit, and clock tree circuit. (Udhayan: at least NIC 530; Fig 5) & (fpga; ¶[0092]) (Ring: sram; Fig 6. Fpga ; col 16 lines 5-16) & (Aravinthan Fig. 9 illustrates an FPGA, ASIC ¶ [00116] )
Claim(s) 3, 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 11/307,773 (hereinafter, “Ring”) in view of U.S. Patent No. 11/921,558 (hereinafter “Udhayan”) and further view of U.S. Publication No. 2023/0254259 (hereinafter “Aravinthan”) and further view of U.S. Publication No. 2020/0073469 (hereinafter Sadowski).
As per claims 3, 14, Udhayan as modified does not distinctly discloses a system wherein the one or more circuits are further to: determine a first circuit of the second one or more circuits is inactive over a predetermined amount of time; and
in response to determining the first circuit of the second one or more circuits is inactive over the predetermined amount of time, disable the first circuit.
However, Sadowski discloses the following:
a system wherein the one or more circuits are further to: determine a first circuit of the one or more circuits is inactive over a predetermined amount of time; and in response to determining the first circuit of the one or more circuits is inactive over the predetermined amount of time, disable the first circuit. (a processor core in a CPU can be power gated if the processor core has been idle for more than a predetermined time interval ¶ [0001] A power management technique for power gating can “include an operating state, a halt state, a stopped clock state, a sleep state with all internal clocks stopped, a sleep state with reduced voltage, and a power down state “.¶ [0017]-[0019])
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring as modified and Sadowski because both references are in the same field of endeavor. Sadowski’s teaching of transitioning a processing circuit to a different power state based on the operating condition would enhance Udhayan's system by limiting power consumption during idle times.
Remarks
Response to Arguments
Applicant's arguments filed on 06-25-2026 in regard to the newly added features have been fully considered by the cited rejection above. On the other hand, Applicant's arguments on regards to previously presented features have been fully considered but they are not persuasive to the extent that is applicable to the claims.
I. Rejections under 35 U.S.C. §103
Independent Claims 1, 13 and 20
Claims 1, 13, 20 were rejected during the outstanding Non-Final rejection under 35 U.S.C. § 103 over U.S. Patent No. 11/307,773 (hereinafter, “Ring”) in view of U.S. Patent No. 11/921,558 (hereinafter “Udhayan”) and further view of U.S. Publication No. 2023/0254259 (hereinafter “Aravinthan”).
During examination of patent application, claims are given their broadest reasonable interpretation under the BRI standard. Furthermore, under the BRI, words of the claim must be given their plain meaning. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Limitations appearing in the specification but not recited in the claim are not read into the claim. In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-551 (CCPA 1969)” (MPEP p 2100-8, c 2, I 45-48; p 2100-9, c 1, l 1-4).
As per claim 1, Applicants assert that the cited prior art allegedly fails to disclose at least “identifying available buffers in which to store packets while the packets are waiting to be processed is not equivalent to and does not suggest identifying circuits for determining a forwarding decision for a packet..”
The Office finds Applicants arguments not persuasive because they do not provide how and why forwarding received packets to at least a scheduler, buffers, GPUs, FPGAs ..etc as taught by at least Aravinthan is not similar to the broad claimed expression of forwarding packets to one or more circuits as currently claimed. Similarly, the other prior art described such forwarding of received packets for processing.
Applicants further argue that the forwarding logic 620 cannot be equated to second one or more circuits because Ring does not disclose applying power to the forwarding logic 620. The Office disagrees because Applicants acknowledges on his remarks that the forward logic 20 is “able to process certain number of packets”. Therefore, it would be apparent for one of ordinary skill to conclude that for the processing logic 20 to process such packets power is applied. How would a circuit operate without power as Applicants are alleging?
Applicants further argue the teachings of Udhayan of “selecting an appropriate CPU frequency specific to the type of workflow" is not the same as enabling one or more by applying power to the one or more circuits. However, Applicant provides no reasons why these teachings are not same. A distinction that is based on conclusory statement without any factual basis cannot stand to show non-obviousness. As noted in the previous outstanding action, Udhayan discloses how the scheduler, buffers, GPUs and FPGAs are configured to perform computer operations associated with data packets. That alone would suggest to a PHOSITA that these circuits have be enabled with power to perform such computer operations because they cannot be done without power being provide. The teaching of adjusting the CPU frequency simply means that the system is enabling a power that is higher. Indeed, even applicants own specification acknowledges that by stating “activating additional processing hardware may include enabling a clock or increasing a frequency of a clock for a logic area “. Therefore, clearly Udhayan teaches the expression that is currently claimed.
For at least the above reasons the rejections are believed to be proper and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
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