DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under t the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 13 and 20 are independent claims. Claims 2-12, and 14-19 are dependent claims.
This action is responsive to the following communication: the response filed on 02-09-2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 serves as an exemplary and recites the following:
1. (Currently Amended) A system comprising a first one or more circuits to:
receive a packet via a port; identify, based on the packet, a second one or more circuits for processing the packet to generate a forwarding decision for the packet;
in response to identifying the second one or more circuits, enable the second one or more circuits to process the packet and generate the forwarding decision for the packet by applying power to the second one or more circuits; and
provide the packet to the second one or more circuits, wherein the second one or more circuits process the packet and generate the forwarding decision for the packet.
MPEP § 2151.01 states, in part that “to satisfy the written description, the specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor has possession of the claimed invention at the time of the filling”.
The underlined portions directed to claim 1 above were amended by Applicant in response to the outstanding Office Actions. Reviewing these amendments, the Office respectfully submits that the specification fails to disclose the expression that includes “generate the forwarding decision for the packet” as currently claimed. Stated differently, although the Specification does disclose language where circuits are responsible for processing packets, the Specification however lacks any teaching for the expression directed to generate the forwarding decision for the packet, let alone the specific sequence where the expression is generated in response to the “identifying” and “provide[ing]” steps. Indeed, a key word search of Applicant’s specification for the expression yields no results.
Therefore, in view of above findings, Applicant failed to identify, in the remarks sections, where and how the specification supports the amended claims. Because the newly added limitations lack explicit support in the original disclosure, the specification does not sufficiently demonstrate that the applicant possessed the claimed subject matter. Courts have long held that “the vast majority of written description problems arise when the patentee amends or adds claims with limitations not found in the original claim set and using language that does not directly map to specification disclosure” . In Re Cisco Systems v. Cirrex (Fed. Cir. 2017)
Claims 13, 20 are rejected under the same rational already described in claim 1.
Dependent claims are based on already rejected independent claims and are rejected for their dependency because said claims do not cure the deficiencies presented in the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 11/307,773 (hereinafter, “Ring”) in view of U.S. Patent No. 11/921,558 (hereinafter “Udhayan”) and further view of U.S. Publication No. 2023/0254259 (hereinafter “Aravinthan”).
As per claims 1, 3, 20, Ring discloses a system comprising a first one or more circuits to:
receive a packet via a port; (ingress ports by which data packets are received; Fig. 6)
identify, based on the packet, a second one or more circuits (inter alia: store packets 605 in temporary memory structures referred to as buffers while the packets 605 are waiting to be processed; [Col 18 lines 44-67]. In other words, buffer and queues; Col 18 lines 44-47 ) for processing the packet to generate a forwarding decision for the packet; (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
in response to identifying the second one or more circuits, enable the second one or more circuits to the second one or more circuits; and (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
provide the packet to the second one or more circuits, wherein the second one or more circuits process the packet (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] ) and generate the forwarding decision for the packet. (The forwarding logic 620 of device 600 may process a packet 605 over one or more stages; [Col 18 lines 44-67]
Ring does not distinctly discloses applying apply power to one or more circuits.
However, Udhayan explicitly discloses that. In particular, it discloses the following:
receive a packet via a port; (incoming network traffic via “PCIe root port 522”; Fig’s 1, 5)
identify, based on the packet, a second one or more circuits for processing the packet (Col 9 lines 14-49 state: “the network traffic metadata may be used to identify particular incoming network traffic as being of real-time or non-real-time workloads. Some examples of non-real-time workloads may include file transfer, cloud synchronization, cloud file download, which with this identification can be scheduled on power efficient cores”. In other words, the system may be “be used to provide hardware guided scheduling to identify appropriate core types on which to schedule workloads.” (Col 6 lines 37-41. Another example, the system may select “heterogenous architecture scheduling may be based at least in part on workflow to schedule on performance core and efficient cores”. Col 8 lines 25-27) to generate a forwarding decision for the packer; ( Col 1 lines 40-52 states “scheduler may become aware of network traffic and base power management policy and/or scheduling decisions based at least in part on this information”.
in response to identifying the one or more circuits, enable the second one or more circuits by applying power to the second one or more circuits; and (Col 7 Lines 33-36 state: “PCU 514 may control power consumption of the cores based at least in part on hardware guided scheduling (HGS) information 516 and/or energy performance preference (EPP) information 518, along with network traffic metadata.” Alternatively, “SoC power savings may be realized by selecting an appropriate CPU frequency specific to the type of workflow”; Col 8 lines 21-24)
provide the packet to the second one or more circuits. (CPUs, performance core and efficient cores, buffer, cache; Fig’s 6, 9)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring and Udhayan because both references are in the same field of endeavor. Udhayan’s teaching of selectively controlling the power of circuits would enhance Ring's system by enhancing energy efficiency capability and a performance capability to the computer system.
Ring as modified does not distinctly disclose in response to identifying the second one or more circuits, enable the second one or more circuits to process the packet and generate the forwarding decision for the packet.
However, Aravinthan discloses that. In particular it discloses the following:
receive a packet via a port; (network ingress port scheduler; Fig. 9)
identify, based on the packet, a second one or more circuits for processing the packet to generate a forwarding decision for the packet; (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
in response to identifying the second one or more circuits, enable the second one or more circuits to process the packet and generate the forwarding decision for the packet; and (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
provide the packet to the second one or more circuits, wherein the second one or more circuits process the packet and generate the forwarding decision for the packet. (¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring as modified and Aravinthan because all references are in the same field of endeavor. Aravinthan’s teaching of splitting data packets into portions would enhance Rings' as modified system by allowing the system to process them more efficiently, thus improving computer’s performance.
As per claim 2, Ring as modified discloses a system wherein each of the one or more circuits comprises hardware to perform a logic algorithm associated with generating the forwarding decision for the packet. (Udhayan: Fig. 4 illustrates scheduling associated with traffic classification by using the “hardware and perform necessary actions”. Also, Fig 5 illustrates network packet classifier perform withing the NIC 530) & (Aravinthan: algorithm for scheduling data packets to the appropriate hosts and accelerators; Fig 9 )
As per claims 4, 15, Ring as modified discloses a system wherein identifying the second one or more circuits comprises identifying one or more services required for forwarding the packet based on a header of the packet. (Udhayan: Network traffic metadata may include information carried in “real-time transport protocol (RTP) headers”; Col 2 lines 17-20) & (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” )
As per claims 5, 16,Ring as modified discloses a system wherein the second one or more circuits are identified based at least in part on a flow associated with the packet. (Udhayan: “packet flow” Col 7 line 66 or “heterogenous architecture scheduling may be based at least in part on workflow’ Col 8 lines 25) & (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” )
As per claims 6, 17, Ring as modified discloses a system wherein the one or more circuits include a first control plane circuit associated with ingress packet processing and a second control plane circuit (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing” ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
As per claims 7, 18, Ring as modified discloses a system wherein the second one or more circuits are control plane circuits associated with ingress packet processing, and wherein processing the packet comprises performing ingress processing. (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”. Moreover, at least Fig. 9 illustrates network ingress/egress pipeline )
As per claims 8, 19, Ring as modified discloses a system wherein the one or more circuits are further to: identify, based on the packet, a third one or more circuits associated with egress processing for processing the packet; enable the third one or more circuits associated with egress processing; and perform egress processing of the packet with the third one or more circuits associated with egress processing. (Aravinthan: ¶s [0096]-[0097] state “splitting a network packet into partial packets, e.g., a transport header, a ULP header, or a payload. [0097] mapping a full packet or partial packets (e.g., payload) to and from a set of P endpoints 906, where P is an integer, and the P endpoints 206 are capable of arbitrary packet processing and/or packet storage. [0098] mapping a full packet or partial packets (e.g. a transport header and a ULP header) to and from a set of N controlling hosts 904, where N is an integer, and the N controlling hosts 904 are capable of arbitrary packet processing or packet header processing”. Moreover, at least Fig. 9 illustrates network ingress/egress pipeline )
As per claim 9, Ring as modified discloses a system wherein the second one or more circuits comprise one or more of, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), network interface card (NIC), port logic circuit, serializer/deserializer (SerDes) circuit, and clock tree circuit. (Udhayan: Fig’s 6,8-9 ) & & (Ring: sram; Fig 6. Fpga ; col 16 lines 5-16) & (Aravinthan Fig. 9 illustrates an FPGA, ASIC ¶ [00116] )
As per claim 10, Ring as modified discloses a system wherein the second one or more circuits comprise a subset of the RAM. (Udhayan: DRAM 260 or cache; Fig 2) & , (Ring: sram; Fig 6)
As per claim 11, Ring as modified discloses a system wherein the second one or more circuits are control plane associated with egress packet processing. (Aravinthan: Fig. 9 illustrates network ingress/egress pipeline ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] ) & (Ring: (inter alia: Forward logic 620 “capable of processing” a number of packets; [Col 18 lines 44-67] Moreover, buffer manager may be responsible for the following: allocating and deallocating packets to buffers, create and delete buffers, identify available buffer(s) [Col 18 lines 44-67] )
As per claim 12, Ring as modified discloses a system wherein the one or more circuits comprise one or more of, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), network interface card (NIC), port logic circuit, serializer/deserializer (SerDes) circuit, and clock tree circuit. (Udhayan: at least NIC 530; Fig 5) & (fpga; ¶[0092]) (Ring: sram; Fig 6. Fpga ; col 16 lines 5-16) & (Aravinthan Fig. 9 illustrates an FPGA, ASIC ¶ [00116] )
Claim(s) 3, 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 11/307,773 (hereinafter, “Ring”) in view of U.S. Patent No. 11/921,558 (hereinafter “Udhayan”) and further view of U.S. Publication No. 2023/0254259 (hereinafter “Aravinthan”) and further view of U.S. Publication No. 2020/0073469 (hereinafter Sadowski).
As per claims 3, 14, Udhayan as modified does not distinctly discloses a system wherein the one or more circuits are further to: determine a first circuit of the second one or more circuits is inactive over a predetermined amount of time; and
in response to determining the first circuit of the second one or more circuits is inactive over the predetermined amount of time, disabling the first circuit.
However, Sadowski discloses the following:
a system wherein the one or more circuits are further to: determine a first circuit of the one or more circuits is inactive over a predetermined amount of time; and in response to determining the first circuit of the one or more circuits is inactive over the predetermined amount of time, disabling the first circuit. (a processor core in a CPU can be power gated if the processor core has been idle for more than a predetermined time interval ¶ [0001] A power management technique for power gating can “include an operating state, a halt state, a stopped clock state, a sleep state with all internal clocks stopped, a sleep state with reduced voltage, and a power down state “.¶ [0017]-[0019])
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ring as modified and Sadowski because both references are in the same field of endeavor. Sadowski’s teaching of transitioning a processing circuit to a different power state based on the operating condition would enhance Udhayan's system by limiting power consumption during idle times.
Response to Arguments
Applicant's arguments filed on 02-09-2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov