CTNF 18/433,460 CTNF 82751 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Vincent (US Publication No. 2025/0202097) . Regarding claim 1, Vincent discloses a semiconductor structure, comprising: a substrate (117) a redistribution layer, comprising: a dielectric stack (118/119) disposed on the substrate (117) a plurality of signal connections (131) penetrating through the dielectric stack a plurality of power/ground connections (136) extending through the dielectric stack (paragraph 19) a plurality of guard members (114/115) disposed in the dielectric stack (118/119) a plurality of solder bumps (138) disposed on the dielectric stack (118/119) and connected to the plurality of signal connections (131) and at least one of the plurality of power/ground connections, wherein each power/ground connection (136) is surrounded by one of the guard members (114/115) PNG media_image1.png 284 486 media_image1.png Greyscale Regarding claim 2, Vincent discloses the plurality of guard members (114/115) are encapsulated by the dielectric stack (118/119) and are in contact with the substrate (117). Regarding claim 3, Vincent discloses the plurality of guard members in the dielectric stack have a non-uniform diameter (Figure 1 shows 133, 129, 134 in 114/115 all have different diameters). Regarding claim 4, Vincent discloses the dielectric stack (118/119) comprises a first dielectric layer (118) disposed on the substrate (117) and a second dielectric layer (119) disposed on the first dielectric layer (118); and the plurality of guard members (114/115) comprise an upper conductive line (114) surrounded by the first dielectric layer (118) and a lower conductive line (115) connected (135) to the upper conductive line (114) and encapsulated by the second dielectric layer (119). Regarding claim 5, Vincent discloses the plurality of power/ground connections (136) comprise an upper conductive line (135), a middle conductive line (133), and a lower conductive line (128) sequentially stacked (elements above and connected to 136) on the substrate (117), the upper conductive lines (135) of the power/ground connections (136) are surrounded by the first dielectric layer (118) and electrically isolation from the upper conductive lines (114) of the guard members (114/1115), the middle conductive lines (133) and the lower conductive lines (128 connected to 136) of the power/ground connections (136) are surround by the second dielectric layer (119) and electrically isolated from the lower conductive lines (115) of the guard members (114/115), and the lower conductive lines (115) of the guard members (114/115) and the middle conductive lines (133) of the power/ground connections (136) are at a same horizontal level (within 119) (Figure 1). Regarding claim 6, Vincent discloses the plurality of signal connections (131) comprise an upper conductive line (135), a middle conductive line (133), and a lower conductive line (128 connected to 136) sequentially stacked on the substrate (117), the upper conductive lines (114) of the signal connections (131) are surrounded by the first dielectric layer (118) and electrically isolation from the upper conductive lines (135) of the guard members (114/115) and from the upper conductive lines (135) of the power/ground connections (136), the middle conductive lines (133) and the lower conductive lines (128) of the signal connections (131) are surround by the second dielectric layer (119) and electrically isolation from the lower conductive lines (128) of the guard members (114/115), the middle conductive lines (133) of the power/ground connections (136), and the lower conductive line (128) of the power/ground connections (136), and the lower conductive lines (128) of the guard members (114/115) and the middle conductive lines (133) of the signal connections (131) are at a same horizontal level (within 119) (Figure 1). Regarding claim 7, Vincent discloses the plurality of guard members (114/115) around the neighboring power/ground connections (136) are connected to each other, and the connected guard members have a shared segment (127) (paragraph 29). Regarding claim 8, Vincent discloses a semiconductor device, comprising: a substrate (117) a chip (180) disposed at a first side of the substrate (117) a plurality of signal conductive vias (131) extending through the substrate (117) a plurality of power/ground conductive vias (136) extending through the substrate (117) a plurality of guard conductive vias (below 127) extending through the substrate (117) a redistribution layer (110) disposed at a second side of the substrate, wherein the second side is opposite to the first side, and the redistribution layer comprises: a dielectric stack (118/119) placed on the substrate (117) a plurality of signal connections (131) penetrating through the dielectric stack, wherein the signal connections are connected to the plurality of signal conductive vias (132) a plurality of power/ground connections (136) extending through the dielectric stack, wherein the plurality of power/ground connections are connected to the power/ground conductive vias (135) a plurality of guard members (114/115) disposed in the dielectric stack and connected to the plurality of guard conductive vias (128), wherein the plurality of power/ground connections (136) are surrounded by the plurality of guard members, respectively (Figure 1) Regarding claim 9, Vincent discloses a plurality of solder bumps (138) attached to the plurality of signal connections (131) and at least one of the plurality of power/ground connections (136). Regarding claim 10, Vincent discloses one of the guard members (114) is coupled to at least two (above and below) of the guard conductive vias (128). Regarding claim 11, Vincent discloses the dielectric stack comprises a first dielectric layer (118) disposed on the substrate (117) and a second dielectric layer (119) disposed on the first dielectric layer (118). Regarding claim 12, Vincent discloses the plurality of guard members (114/115) comprise an upper conductive line (135) surrounded by the first dielectric layer (118) and a lower conductive line (134 above 128) connected to the upper conductive line and encapsulated by the second dielectric layer (119), and the upper conductive line (114) has a first diameter and the lower conductive line (134) has a second diameter greater than the first diameter (Figure 1). Regarding claim 13, Vincent discloses the plurality of signal connections (131) comprise an upper conductive line (135), a middle conductive lines (133), and a lower conductive line (128 connected to 136)sequentially stacked on the substrate (117), the upper conductive lines (135) of the guard members (114/115) and the upper conductive lines (114) of the signal connections (131) are at a first horizontal level, and the lower conductive lines of guard members and the middle conductive lines of the signal connections are at a second horizontal level (within 119) (Figure 1). Regarding claim 14, Vincent discloses the plurality of guard members have a polygonal shape (Figure 1; paragraph 52). Regarding claim 15, Vincent discloses each of the guard members (114/115) comprises a plurality of first segments in contact with the guard conductive vias (below 127), respectively, and a plurality of second segment connected to adjacent first segments, the first segments have a first width, and the second segments have a second width less than the first width (Figure 1). Regarding claim 16, Vincent discloses a bottom of each guard member is covered by the dielectric stack (Figure 1; paragraph 52). Regarding claim 17, Vincent discloses a method of a semiconductor device, comprising: depositing a first dielectric layer (118) on a substrate (117) forming a first conductive layer extending through the first dielectric layer (118), wherein the first conductive layer comprises an upper layer of a signal connection (131), a upper layer of a power/ground connection (136), and an upper layer of a guard member (114), wherein the upper layer of the signal connection, the upper layer of the power/ground connection, and the upper layer of the guard member are electrically isolated from each other (Figure 1) forming a second conductive layer (132/135 vias within 118) on the first conductive layer, wherein the second conductive layer comprises a middle layer of the signal connection connected to the upper layer of the signal connection (131), a middle layer of the power/ground connection connected to the upper layer of the power/ground connection (136), and a lower layer of the guard member connected to the upper layer of the guard member (Figure 1) depositing a second dielectric layer (119) to cover the first dielectric layer and the second conductive layer forming a third conductive layer (130/131/136) in the second dielectric layer, wherein the third conductive layer comprises a lower layer of the signal connection (131) connected to the middle layer of the signal connection and a lower layer of the power/ground connection (136) connected to the middle layer of the power/ground connection (Figure 10) Regarding claim 18, Vincent discloses forming a plurality of conductive vias (113) extending through the substrate (117) prior to the deposition of the first dielectric layer (118), wherein the upper layer of the signal connection, the upper layer of the power/ground connection (136), and the upper layer of the guard member (130) are in contact with the plurality of conductive vias (Figure 1). Regarding claim 19, Vincent discloses forming a plurality of bumps (138) attached to the third conductive layer (130). Regarding claim 20, Vincent discloses the formation of the second conductive layer comprises: depositing a layer of conductive material (129) on the first dielectric layer (118) and the first conductive layer (114); and performing an etching operation on the layer of the conductive material through a pattered mask layer to thereby form the middle layer of the signal connection (131), the middle layer of the power/ground connection (136), and the lower layer of the guard member (paragraphs 26-32) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al. (US Publication No. 2022/0108935) discloses guard members (223) surrounding interconnects (Figures 1A and 3A). Kim et al. (US Publication No. 2020/0402915) discloses ground via (141) and signal via (143) and shielding (210) surrounding the ground and signal vias (Figure 4). Fillion et al. (US Publication No. 2020/0111680) discloses signal, ground, and shielding below a chip (paragraph 97; Figure 12) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 4/23/2026Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/433,460 Page 2 Art Unit: 2897 Application/Control Number: 18/433,460 Page 3 Art Unit: 2897 Application/Control Number: 18/433,460 Page 4 Art Unit: 2897 Application/Control Number: 18/433,460 Page 5 Art Unit: 2897 Application/Control Number: 18/433,460 Page 6 Art Unit: 2897 Application/Control Number: 18/433,460 Page 7 Art Unit: 2897 Application/Control Number: 18/433,460 Page 8 Art Unit: 2897 Application/Control Number: 18/433,460 Page 9 Art Unit: 2897
