DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I in the reply filed on 05/26/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden for one reason being that both inventions are classified in the same field of search. This is not found persuasive because though both inventions have the same classification (which may contain thousands of inventions), they do not have the same field of search for the reasons that the different terms and limitations require different considerations and search strategies.
The requirement is still deemed proper and is therefore made FINAL.
Claims 28-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 05/26/2026.
Claims
Applicant’s Claims filed on 05/26/2026 regarding claims 1-30 is fully considered. Of the above claims, claims 28-30 have been withdrawn.
Claim Objections
Claim 7 is objected to because of the following informalities:
Regarding claim 7, the recitation of “at least one TSV” in line 2 refers to a previously recited limitation.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-10, 18-19 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2021/0190854 A1).
Regarding claim 1, Oh et al. teach a semiconductor device (semiconductor memory system 100; Figs 1-3) comprising:
a plurality of chiplets (core dies 112; Figs 1-3); and
at least one through silicon via, TSV, connecting two or more of the plurality of chiplets (through-silicon vias TSVs; Figs 1-3),
at least one of the plurality of chiplets comprising TSV monitoring circuitry configured to perform in-situ validation of the at least one TSV (the through-electrode scan circuits 23_1 to 23_4 may perform a down-scan and an up-scan on the through-electrodes TSV0X to TSV4X connected in the column direction among the through-electrodes; the error detection circuits 24_1 to 24_4 may detect whether the through-electrodes TSV0X to TSV4X have defects, based on the down-scan and the up-scan; [0060]; FIG. 3),
the TSV monitoring circuitry being configured to:
apply a stimulus input signal to the at least one TSV (the current source PM0 may provide a source current corresponding to a signal transmitted in the upward direction to the terminal NO0 of the through-electrode TSV0X in response to the up-scan signal UP_SCAN; [0063]; FIG. 3);
receive a stimulus output signal from the at least one TSV, in response to the stimulus input signal (the error detection circuits 24_0 to 24_4 of each die may store the down-scan result as the first value according to the down-scan signal DN_SCAN and the latch signal OS_LAT; [0067]; Figs 3-4); and
monitor one or more electrical characteristics of the at least one TSV based on the stimulus output signal and the stimulus input signal (the error detection circuits 24_1 to 24_4 then may combine the stored first and second values to generate a fail determination signal FAIL<X> indicating whether the through-electrodes TSV0X to TSV4X have defects; [0062]; FIG. 3).
Regarding claim 9, Oh et al. teach wherein the TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the at least one TSV in a stack comprising the plurality of chiplets (stacked memory device 110; FIG. 1).
Regarding claim 10, Oh et al. teach a method for validating a semiconductor device comprising two or more chiplets connected together by at least one through silicon via, TSV (semiconductor memory system 100; core dies 112; through-silicon vias TSVs; Figs 1-3; the through-electrode scan circuits 23_1 to 23_4 may perform a down-scan and an up-scan on the through-electrodes TSV0X to TSV4X connected in the column direction among the through-electrodes; the error detection circuits 24_1 to 24_4 may detect whether the through-electrodes TSV0X to TSV4X have defects, based on the down-scan and the up-scan; [0060]), the method comprising:
applying a stimulus input signal to the at least one TSV (the current source PM0 may provide a source current corresponding to a signal transmitted in the upward direction to the terminal NO0 of the through-electrode TSV0X in response to the up-scan signal UP_SCAN; [0063]; FIG. 3);
receiving a stimulus output signal from the at least one TSV, in response to the stimulus input signal (the error detection circuits 24_0 to 24_4 of each die may store the down-scan result as the first value according to the down-scan signal DN_SCAN and the latch signal OS_LAT; [0067]; Figs 3-4); and
monitoring one or more electrical characteristics of the at least one TSV based on the stimulus output signal and the stimulus input signal (the error detection circuits 24_1 to 24_4 then may combine the stored first and second values to generate a fail determination signal FAIL<X> indicating whether the through-electrodes TSV0X to TSV4X have defects; [0062]; FIG. 3).
Regarding claim 18, Oh et al. teach wherein monitoring the one or more electrical characteristics of the at least one TSV in a stack comprising the two or more chiplets (stacked memory device 110; FIG. 1).
Regarding claim 19, Oh et al. teach a semiconductor device comprising two or more chiplets connected together by at least one through silicon via, TSV (semiconductor memory system 100; core dies 112; through-silicon vias TSVs; Figs 1-3; the through-electrode scan circuits 23_1 to 23_4 may perform a down-scan and an up-scan on the through-electrodes TSV0X to TSV4X connected in the column direction among the through-electrodes; the error detection circuits 24_1 to 24_4 may detect whether the through-electrodes TSV0X to TSV4X have defects, based on the down-scan and the up-scan; [0060]), comprising:
means for applying a stimulus input signal into the at least one TSV (the current source PM0 may provide a source current corresponding to a signal transmitted in the upward direction to the terminal NO0 of the through-electrode TSV0X in response to the up-scan signal UP_SCAN; [0063]; FIG. 3);
means for receiving a stimulus output signal from the at least one TSV, in response to the stimulus input signal (the error detection circuits 24_0 to 24_4 of each die may store the down-scan result as the first value according to the down-scan signal DN_SCAN and the latch signal OS_LAT; [0067]; Figs 3-4); and
means for monitoring one or more electrical characteristics of the at least one TSV based on the stimulus output signal and the stimulus input signal (the error detection circuits 24_1 to 24_4 then may combine the stored first and second values to generate a fail determination signal FAIL<X> indicating whether the through-electrodes TSV0X to TSV4X have defects; [0062]; FIG. 3).
Regarding claim 27, Oh et al. teach means for monitoring the one or more electrical characteristics of the at least one TSV in a stack comprising the two or more chiplets (stacked memory device 110; FIG. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) in view of Su et al. (US 2012/0018723 A1).
Regarding claim 2, Oh et al. do not teach wherein the TSV monitoring circuitry comprises:
an alternating current AC signal path configured to perform AC signal validation of the at least one TSV based on the stimulus output signal; and
a direct current DC signal path configured to perform DC signal validation of the at least one TSV based on the stimulus output signal.
Further regarding claim 2, Su et al. teach a TSV monitoring circuitry comprises:
an alternating current AC signal path configured to perform AC signal validation of at least one TSV based on a stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A); and
a direct current DC signal path configured to perform DC signal validation of the at least one TSV based on the stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A) for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the TSV monitoring circuitry comprises: an alternating current AC signal path configured to perform AC signal validation of the at least one TSV based on the stimulus output signal; and a direct current DC signal path configured to perform DC signal validation of the at least one TSV based on the stimulus output signal, as taught by Su et al., into Oh et al. for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
Regarding claim 11, Oh et al. do not teach wherein the monitoring comprises:
performing AC signal validation of the at least one TSV based on the stimulus output signal; and
performing DC signal validation of the at least one TSV based on the stimulus output signal.
Further regarding claim 11, Su et al. teach a monitoring comprises:
performing AC signal validation of at least one TSV based on a stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A); and
performing DC signal validation of the at least one TSV based on the stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A) for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the monitoring comprises: performing AC signal validation of the at least one TSV based on the stimulus output signal; and performing DC signal validation of the at least one TSV based on the stimulus output signal, as taught by Su et al., into Oh et al. for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
Regarding claim 20, Oh et al. do not teach wherein the means for monitoring comprises:
means for performing AC signal validation of the at least one TSV based on the stimulus output signal; and
means for performing DC signal validation of the at least one TSV based on the stimulus output signal.
Further regarding claim 20, Su et al. teach a means for monitoring comprises:
means for performing AC signal validation of at least one TSV based on a stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A); and
means for performing DC signal validation of the at least one TSV based on the stimulus output signal (the test signal comprises a direct current component and an AC component; [0026]; FIG. 1A) for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the means for monitoring comprises: means for performing AC signal validation of the at least one TSV based on the stimulus output signal; and means for performing DC signal validation of the at least one TSV based on the stimulus output signal, as taught by Su et al., into Oh et al. for the purpose of monitoring both the resistive, capacitive and inductive characteristics of TSVs.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 2 above, and further in view of Yoko et al. (US 2011/0175639 A1).
Regarding claim 3, Oh et al. as modified by Su et al. do not teach wherein the AC signal path comprises at least one of:
current sensor circuitry configured to measure an electrical current corresponding to the stimulus output signal;
phase detector circuitry configured to compare a reference signal with the stimulus output signal to measure a phase of the stimulus output signal; or
filter circuitry configured to filter out or pass through one or more predetermined frequencies.
Further regarding claim 3, Yoko et al. teach an AC signal path (it is possible to verify time constants, AC characteristics, of a plurality of signal lines including a plurality of through silicon vias respectively connecting the interface chip and the core chips in a layered structure; [0022]; this alternate-current signal becomes the measurement signal described above; [0080]) comprises a phase detector circuitry configured to compare a reference signal with the stimulus output signal to measure a phase of the stimulus output signal (the determination circuit 102 generates a test result based on a phase difference of the measurement signal appearing at an end in the interface chip of each of the measurement-target signal line 130 and the reference signal line 131 and outputs the test result; [0075]; FIG. 5; the difference of the amount of the delay is detected by the operational amplifier 117, phase comparison circuit, as a phase difference; [0082]-[0083]) for the purpose of monitoring phase differences of the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the AC signal path comprises a phase detector circuitry configured to compare a reference signal with the stimulus output signal to measure a phase of the stimulus output signal, as taught by Yoko et al., into Oh et al. as modified by Su et al. for the purpose of monitoring phase differences of the TSVs.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 2 above, and further in view of Hargan et al. (US 2010/0013512 A1).
Regarding claim 4, Oh et al. as modified by Su et al. do not teach wherein the DC signal path comprises comparator circuitry configured to compare the stimulus output signal with a DC reference signal.
Further regarding claim 4, Hargan et al. a DC signal path (the arrangement shown in device 400 may allow testing of the three show TSV stacks using direct current and without need for a clock; [0030]) comprises comparator circuitry configured to compare the stimulus output signal with a DC reference signal (the high gain sense amp 408 then amplifies the difference between Vref and Vtsv and provides a reliable comparison measurement; [0032]; FIG. 4) for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the DC signal path comprises comparator circuitry configured to compare the stimulus output signal with a DC reference signal, as taught by Hargan et al., into Oh et al. as modified by Su et al. for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
Claim(s) 5, 14 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) in view of Yang et al. (US 2013/0294184 A1).
Regarding claim 5, Oh et al. do not teach wherein the TSV monitoring circuitry is configured to monitor the one or more electrical characteristics of the at least one TSV in at least one of:
a startup timeline of the semiconductor device; or
a runtime of the semiconductor device.
Further regarding claim 5, Yang et al. teach a TSV monitoring circuitry is configured to monitor one or more electrical characteristics of at least one TSV in a runtime of a semiconductor device (step 805 executed during runtime of a process for a stacked memory device; [0048]; FIG. 8) for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the TSV monitoring circuitry is configured to monitor the one or more electrical characteristics of the at least one TSV in a runtime of the semiconductor device, as taught by Yang et al., into Oh et al. for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
Regarding claim 14, Oh et al. do not teach monitoring the one or more electrical characteristics of the at least one TSV in at least one of:
a startup timeline of the semiconductor device before commencing a boot-up sequence of the two or more chiplets; or
a runtime of the semiconductor device.
Further regarding claim 14, Yang et al. teach monitoring one or more electrical characteristics of at least one TSV in a runtime of a semiconductor device (step 805 executed during runtime of a process for a stacked memory device; [0048]; FIG. 8) for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate monitoring the one or more electrical characteristics of the at least one TSV in a runtime of the semiconductor device, as taught by Yang et al., into Oh et al. for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
Regarding claim 23, Oh et al. do not teach means for monitoring the one or more electrical characteristics of the at least one TSV in at least one of:
a startup timeline of the semiconductor device before commencing a boot-up sequence of the two or more chiplets; or
a runtime of the semiconductor device.
Further regarding claim 23, Yang et al. teach means for monitoring one or more electrical characteristics of at least one TSV in a runtime of a semiconductor device (step 805 executed during runtime of a process for a stacked memory device; [0048]; FIG. 8) for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate means for monitoring the one or more electrical characteristics of the at least one TSV in a runtime of the semiconductor device, as taught by Yang et al., into Oh et al. for the purpose of monitoring the TSVs at the start of a runtime to determine whether to proceed with normal operation or repair operation.
Claim(s) 6, 15 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) in view of Whetsel et al. (US 2018/0106863 A1).
Regarding claim 6, Oh et al. teach wherein the at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 6, Oh et al. do not teach wherein the TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the plurality of TSVs concurrently.
Further regarding claim 6, Whetsel et al. teach a TSV monitoring circuitry is configured to monitor one or more electrical characteristics of a plurality of TSVs concurrently (multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time; Abstract; FIG. 5) for the purpose of reducing the execution time needed to monitoring the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the plurality of TSVs concurrently, as taught by Whetsel et al., into Oh et al. for the purpose of reducing the execution time needed to monitoring the TSVs.
Regarding claim 15, Oh et al. teach wherein the at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 15, Oh et al. do not teach monitoring the one or more electrical characteristics of the plurality of TSVs concurrently.
Further regarding claim 15, Whetsel et al. teach monitoring one or more electrical characteristics of a plurality of TSVs concurrently (multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time; Abstract; FIG. 5) for the purpose of reducing the execution time needed to monitoring the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate monitoring the one or more electrical characteristics of the plurality of TSVs concurrently, as taught by Whetsel et al., into Oh et al. for the purpose of reducing the execution time needed to monitoring the TSVs.
Regarding claim 24, Oh et al. teach wherein the at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 24, Oh et al. do not teach means for monitoring the one or more electrical characteristics of the plurality of TSVs concurrently.
Further regarding claim 24, Whetsel et al. teach means for monitoring one or more electrical characteristics of a plurality of TSVs concurrently (multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time; Abstract; FIG. 5) for the purpose of reducing the execution time needed to monitoring the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate means for monitoring the one or more electrical characteristics of the plurality of TSVs concurrently, as taught by Whetsel et al., into Oh et al. for the purpose of reducing the execution time needed to monitoring the TSVs.
Claim(s) 7, 16 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) in view of Choi et al. (US 2011/0102006 A1).
Regarding claim 7, Oh et al. teach wherein at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 7, Oh et al. do not teach wherein the TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the plurality of TSVs in sequence.
Further regarding claim 7, Choi et al. teach a TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the plurality of TSVs in sequence (the detecting unit 230 is sequentially connected to the first through third TSVs TSV1, TSV2 and TSV3 by the selecting unit 220; [0036]; FIG. 3) for the purpose of sharing one detecting unit among plural TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the TSV monitoring circuitry is further configured to monitor the one or more electrical characteristics of the plurality of TSVs in sequence, as taught by Choi et al., into Oh et al. for the purpose of sharing one detecting unit among plural TSVs.
Regarding claim 16, Oh et al. teach wherein at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 16, Oh et al. do not teach monitoring the one or more electrical characteristics of the plurality of TSVs in sequence.
Further regarding claim 16, Choi et al. teach monitoring the one or more electrical characteristics of the plurality of TSVs in sequence (the detecting unit 230 is sequentially connected to the first through third TSVs TSV1, TSV2 and TSV3 by the selecting unit 220; [0036]; FIG. 3) for the purpose of sharing one detecting unit among plural TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate monitoring the one or more electrical characteristics of the plurality of TSVs in sequence, as taught by Choi et al., into Oh et al. for the purpose of sharing one detecting unit among plural TSVs.
Regarding claim 25, Oh et al. teach wherein at least one TSV comprises a plurality of TSVs (through-silicon vias TSVs; Figs 1-3).
Further regarding claim 25, Oh et al. do not teach means for monitoring the one or more electrical characteristics of the plurality of TSVs in sequence.
Further regarding claim 25, Choi et al. teach means for monitoring the one or more electrical characteristics of the plurality of TSVs in sequence (the detecting unit 230 is sequentially connected to the first through third TSVs TSV1, TSV2 and TSV3 by the selecting unit 220; [0036]; FIG. 3) for the purpose of sharing one detecting unit among plural TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate means for monitoring the one or more electrical characteristics of the plurality of TSVs in sequence, as taught by Choi et al., into Oh et al. for the purpose of sharing one detecting unit among plural TSVs.
Claim(s) 8, 17 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) in view of Ide et al. (US 2012/0069685 A1).
Regarding claim 8, Oh et al. do not teach a data storage configured to store a test result of the at least one TSV, the test result indicating whether or not the at least one TSV is defective.
Further regarding claim 8, Ide et al. teach a data storage configured to store a test result of the at least one TSV, the test result indicating whether or not the at least one TSV is defective (the information to be stored in the electrical fuse circuit 83 includes at least information on defects of the through silicon vias TSV and information on defects of the memory cells in the core chips CC0 to CC7; [0069]; FIG. 9) for the purpose of saving information on the TSVs for future operations and/or repairs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a data storage configured to store a test result of the at least one TSV, the test result indicating whether or not the at least one TSV is defective, as taught by Ide et al., into Oh et al. for the purpose of saving information on the TSVs for future operations and/or repairs.
Regarding claim 17, Oh et al. do not teach storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective.
Further regarding claim 17, Ide et al. teach storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective (the information to be stored in the electrical fuse circuit 83 includes at least information on defects of the through silicon vias TSV and information on defects of the memory cells in the core chips CC0 to CC7; [0069]; FIG. 9) for the purpose of saving information on the TSVs for future operations and/or repairs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective, as taught by Ide et al., into Oh et al. for the purpose of saving information on the TSVs for future operations and/or repairs.
Regarding claim 26, Oh et al. do not teach means for storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective.
Further regarding claim 26, Ide et al. teach means for storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective (the information to be stored in the electrical fuse circuit 83 includes at least information on defects of the through silicon vias TSV and information on defects of the memory cells in the core chips CC0 to CC7; [0069]; FIG. 9) for the purpose of saving information on the TSVs for future operations and/or repairs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate means for storing a test result of the at least one TSV in a data storage, the test result indicating whether or not the at least one TSV is defective, as taught by Ide et al., into Oh et al. for the purpose of saving information on the TSVs for future operations and/or repairs.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 11 above, and further in view of Yoko et al. (US 2011/0175639 A1).
Regarding claim 12, Oh et al. as modified by Su et al. do not teach wherein the performing AC signal validation comprises at least one of:
measuring an electrical current corresponding to the stimulus output signal;
comparing a reference signal with the stimulus output signal to detect a phase of the stimulus output signal; or
filtering out or pass through one or more predetermined frequencies.
Further regarding claim 12, Yoko et al. teach performing AC signal validation (it is possible to verify time constants, AC characteristics, of a plurality of signal lines including a plurality of through silicon vias respectively connecting the interface chip and the core chips in a layered structure; [0022]; this alternate-current signal becomes the measurement signal described above; [0080]) comprises comparing a reference signal with the stimulus output signal to measure a phase of the stimulus output signal (the determination circuit 102 generates a test result based on a phase difference of the measurement signal appearing at an end in the interface chip of each of the measurement-target signal line 130 and the reference signal line 131 and outputs the test result; [0075]; FIG. 5; the difference of the amount of the delay is detected by the operational amplifier 117, phase comparison circuit, as a phase difference; [0082]-[0083]) for the purpose of monitoring phase differences of the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the performing AC signal validation comprises comparing a reference signal with the stimulus output signal to detect a phase of the stimulus output signal, as taught by Yoko et al., into Oh et al. as modified by Su et al. for the purpose of monitoring phase differences of the TSVs.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 11 above, and further in view of Hargan et al. (US 2010/0013512 A1).
Regarding claim 13, Oh et al. as modified by Su et al. do not teach wherein the performing DC signal validation comprises comparing the stimulus output signal with a DC reference signal.
Further regarding claim 13, Hargan et al. a performing DC signal validation (the arrangement shown in device 400 may allow testing of the three show TSV stacks using direct current and without need for a clock; [0030]) comprises comparing the stimulus output signal with a DC reference signal (the high gain sense amp 408 then amplifies the difference between Vref and Vtsv and provides a reliable comparison measurement; [0032]; FIG. 4) for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the performing DC signal validation comprises comparing the stimulus output signal with a DC reference signal, as taught by Hargan et al., into Oh et al. as modified by Su et al. for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 20 above, and further in view of Yoko et al. (US 2011/0175639 A1).
Regarding claim 21, Oh et al. as modified by Su et al. do not teach wherein the means for performing AC signal validation comprises at least one of:
means for measuring an electrical current corresponding to the stimulus output signal;
means for comparing a reference signal with the stimulus output signal to detect a phase of the stimulus output signal; or
means for filtering out or pass through one or more predetermined frequencies.
Further regarding claim 21, Yoko et al. teach means for performing AC signal validation (it is possible to verify time constants, AC characteristics, of a plurality of signal lines including a plurality of through silicon vias respectively connecting the interface chip and the core chips in a layered structure; [0022]; this alternate-current signal becomes the measurement signal described above; [0080]) comprises means for comparing a reference signal with the stimulus output signal to measure a phase of the stimulus output signal (the determination circuit 102 generates a test result based on a phase difference of the measurement signal appearing at an end in the interface chip of each of the measurement-target signal line 130 and the reference signal line 131 and outputs the test result; [0075]; FIG. 5; the difference of the amount of the delay is detected by the operational amplifier 117, phase comparison circuit, as a phase difference; [0082]-[0083]) for the purpose of monitoring phase differences of the TSVs.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the means for performing AC signal validation comprises means for comparing a reference signal with the stimulus output signal to detect a phase of the stimulus output signal, as taught by Yoko et al., into Oh et al. as modified by Su et al. for the purpose of monitoring phase differences of the TSVs.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2021/0190854 A1) as modified by Su et al. (US 2012/0018723 A1) as applied to claim 20 above, and further in view of Hargan et al. (US 2010/0013512 A1).
Regarding claim 22, Oh et al. as modified by Su et al. do not teach wherein the means for performing DC signal validation comprises means for comparing the stimulus output signal with a DC reference signal.
Further regarding claim 22, Hargan et al. a means for performing DC signal validation (the arrangement shown in device 400 may allow testing of the three show TSV stacks using direct current and without need for a clock; [0030]) comprises means comparing the stimulus output signal with a DC reference signal (the high gain sense amp 408 then amplifies the difference between Vref and Vtsv and provides a reliable comparison measurement; [0032]; FIG. 4) for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the means for performing DC signal validation comprises means for comparing the stimulus output signal with a DC reference signal, as taught by Hargan et al., into Oh et al. as modified by Su et al. for the purpose of monitoring the quality of the TSVs by comparing to a reference value.
Conclusion
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11 June 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853
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