Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Note: The claims recite detecting hardware tampering and recovery method which has practical utility and hence is patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi et al (US 20210042035), Fut and Walrath; Craig (US 20120023589), Wal.
Claim 1: Fut teaches an information processing system comprising: one or a plurality of processors configured to (Fig. 2): detect tampering of [hardware] that is mounted on an information processing apparatus and configured to execute first processing; ([026, 29] The detector is a module that detects tampering of CPU-A FW for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B).
in a case where second processing has not been executed or has not been scheduled to be executed by the information processing apparatus, restart the information processing apparatus to achieve recovery from the tampering; ([026] The detector is a module that detects tampering of firmware for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B. Note that the tampering of firmware for normal operation while the storage device is inactivated (i.e., process not executed) is detected by the foregoing secure boot function when the storage device is booted; [028] when the recovery determination module determines that the CPU-A can be recovered by recovering the CPU-A FW for normal operation, the recovery execution module overwrites the CPU-A FW for normal operation to the CPU-A FW for recovery and executes a process of rebooting the storage device to recover the storage device).
and in a case where the second processing has been executed or has been scheduled to be executed, when a predetermined condition is satisfied, restart the information processing apparatus to achieve recovery from the tampering. ([044-46, Fig. 3] Based on the determination result of the cause of the abnormal operation (i.e., second process), the recovery determination module determines whether the storage device can be recovered by updating the firmware for normal operation ... and if the recovery determination module determines that the storage device can be recovered by updating the firmware, the recovery execution module reads the firmware for recovery ... from the nonvolatile memory and stores it in the volatile memory. The recovery execution module verifies the reliability of the firmware for recovery using the security assurance data managed by the Security CPU (i.e., condition). If the verification is successful, the recovery execution module overwrites the firmware for normal operation on the nonvolatile memory to the firmware for recovery and reboots the storage device).
Fut teaches about the claimed concept but is not explicit about detecting tampered hardware.
But analogous art Wal teaches detecting tampered hardware. ([08, 17, Figs. 1A-B] the electronic device contains a recovery mechanism (in the form of hardware only ...) that is able to detect tampering of the electronic device).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fut to integrate the idea of detecting hardware tampering as taught by Wal so that a person who has stolen the electronic device or storage medium would not be able to view or have access the recovery code and at least some portion of the data [020].
Claim 8: Fut teaches an information processing method comprising (Fig. 2): detecting tampering of [hardware] that is mounted on an information processing apparatus and configured to execute first processing; in a case where second processing has not been executed or has not been scheduled to be executed by the information processing apparatus, restarting the information processing apparatus to achieve recovery from the tampering; and in a case where the second processing has been executed or has been scheduled to be executed, when a predetermined condition is satisfied, restarting the information processing apparatus to achieve recovery from the tampering. ([026, 29] The detector is a module that detects tampering of CPU-A FW for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B; [026] The detector is a module that detects tampering of firmware for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B. Note that the tampering of firmware for normal operation while the storage device is inactivated (i.e., second processing not executed) is detected by the foregoing secure boot function when the storage device is booted; [028] when the recovery determination module determines that the CPU-A can be recovered by recovering the CPU-A FW for normal operation, the recovery execution module overwrites the CPU-A FW for normal operation to the CPU-A FW for recovery and executes a process of rebooting the storage device to recover the storage device; [044-46, Fig. 3] Based on the determination result of the cause of the abnormal operation (i.e., second process), the recovery determination module determines whether the storage device can be recovered by updating the firmware for normal operation ... and if the recovery determination module determines that the storage device can be recovered by updating the firmware, the recovery execution module reads the firmware for recovery ... from the nonvolatile memory and stores it in the volatile memory. The recovery execution module verifies the reliability of the firmware for recovery using the security assurance data managed by the Security CPU (i.e., condition). If the verification is successful, the recovery execution module overwrites the firmware for normal operation on the nonvolatile memory to the firmware for recovery and reboots the storage device).
Fut teaches about the claimed concept but is not explicit about detecting tampered hardware.
But analogous art Wal teaches detecting tampered hardware. ([08, 17, Figs. 1A-B] the electronic device contains a recovery mechanism (in the form of hardware only ...) that is able to detect tampering of the electronic device).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fut to include the idea of detect hardware tampering as taught by Wal so that a person who has stolen the electronic device or storage medium would not be able to view or have access the recovery code and at least some portion of the data [020].
Claim 9: Fut teaches a non-transitory computer readable medium storing a program causing a computer to execute a process comprising (Fig. 2): detecting tampering of hardware that is mounted on an information processing apparatus and configured to execute first processing; in a case where second processing has not been executed or has not been scheduled to be executed by the information processing apparatus, restarting the information processing apparatus to achieve recovery from the tampering; and in a case where the second processing has been executed or has been scheduled to be executed, when a predetermined condition is satisfied, restarting the information processing apparatus to achieve recovery from the tampering. ([026, 29] The detector is a module that detects tampering of CPU-A FW for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B; [026] The detector is a module that detects tampering of firmware for normal operation during the operation of the storage device, and detects an abnormal operation of the storage device, more specifically, an abnormal operation of the Security CPU, CPU-A or CPU-B. Note that the tampering of firmware for normal operation while the storage device is inactivated (i.e., second processing not executed) is detected by the foregoing secure boot function when the storage device is booted; [028] when the recovery determination module determines that the CPU-A can be recovered by recovering the CPU-A FW for normal operation, the recovery execution module overwrites the CPU-A FW for normal operation to the CPU-A FW for recovery and executes a process of rebooting the storage device to recover the storage device; [044-46, Fig. 3] Based on the determination result of the cause of the abnormal operation (i.e., second process), the recovery determination module determines whether the storage device can be recovered by updating the firmware for normal operation ... and if the recovery determination module determines that the storage device can be recovered by updating the firmware, the recovery execution module reads the firmware for recovery ... from the nonvolatile memory and stores it in the volatile memory. The recovery execution module verifies the reliability of the firmware for recovery using the security assurance data managed by the Security CPU (i.e., condition). If the verification is successful, the recovery execution module overwrites the firmware for normal operation on the nonvolatile memory to the firmware for recovery and reboots the storage device).
Fut teaches about the claimed concept but is not explicit about detecting tampered hardware.
But analogous art Wal teaches detecting tampered hardware. ([08, 17, Figs. 1A-B] the electronic device contains a recovery mechanism (in the form of hardware only ...) that is able to detect tampering of the electronic device).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fut to include the idea of detect hardware tampering as taught by Wal so that a person who has stolen the electronic device or storage medium would not be able to view or have access the recovery code and at least some portion of the data [020].
Claim(s) 2 – 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fut and Wal as applied to independent claims above, and further in view of Suryanarayana et al (US 20230112947), Sur.
Claim 2: the combination of Fut and Wal teaches the information processing system according to claim 1, but analogous art Sur teaches wherein the one or the plurality of processors are configured to, when tampering of the hardware is detected, not turn OFF power of the hardware and not allow the hardware to execute the first processing until recovery from the tampering has been achieved. ([037] The EOS controls the high-efficiency processor core to execute EOS operations before booting an operating system, such as diagnostics, recovery, tampering, malware, reboot, and other functions; [06] performing the tasks within the EOS may be reduced by executing operations using a low-power core of an information handling system; [024] The high-performance core may determine to perform the hand-off in these examples based on a first attribute of the information handling system at the time the BIOS is booting. For example, the high-performance core may determine a battery charge level, and hand-off execution of the EOS operations (such as downloading a recovery image and/or executing a GPU diagnostics) to the high-efficiency core when the battery charge level is below a certain threshold. After all EOS operations are completed, the EOS may determine a boot device and begin loading an operating system from the boot device; [026] The high-performance processor core is disabled by the embedded operating system (EOS) and the uCode is not loaded for the CPU initialization).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined inventions of Fut and Wal to include the idea of operate at low-power mode as taught by Sur so that the EOS enables power-efficient operations to allow the recovery process to be completed efficiently to recover from tampering.
Claim 3: the combination of Fut and Wal teaches the information processing system according to claim 2, wherein the one or the plurality of processors are configured to: transmit, to a terminal of a user who remotely operates the information processing apparatus, information indicating that the hardware has been tampered with and information indicating that the information processing apparatus is capable of executing different processing that is different from the first processing by the hardware that has been tampered with; and cause the different processing to be executed in accordance with an instruction from the user. (Fut: [028] When the recovery determination module determines that the storage device cannot be recovered by recovering the firmware for normal operation, it may notify the host of an error. [040] the storage device may simply transmit, to the host, for example, a message indicating that the firmware needs to be updated, and thereafter, the firmware for normal operation may be updated under the initiative of the host).
Claim 4: the combination of Fut and Wal teaches the information processing system according to claim 3, but analogous art Sur teaches wherein the one or the plurality of processors are configured to, in a case where a plurality of pieces of hardware are mounted, cause a piece of hardware that is not tampered with, out of the plurality of pieces of hardware, to execute the first processing in accordance with the instruction from the user. ([06] such an information handling system may include a system on chip (SoC) having two configurations of processor cores referred to as “big” cores and “little” cores. The EOS may execute on one or both of a first processor core (e.g., high performance or “big” core) and second processor core (e.g., high efficiency or “small” core) of an information handling system, in which the first and second processor cores are configured differently. [0032] If, for example, the first attribute meets a first criteria, execution results in continuing to hand-off execution to the second processor core and execute the EOS operation on the second processor core. Execution of EOS operations may be performed in parallel on two or more second processor cores, such as two high-efficiency processor cores. If the criteria are not met, execution continues EOS operations on one of the other or one or more of the first and second processor cores. Execution of EOS operations may be performed in parallel on two or more processor cores from a combination of high-performance processor cores and high-efficiency processor cores available in the information handling system, such as on a combination of high-performance and high-efficiency processor cores; [035] The BIOSConnect module may present a user interface for performing recovery operations, such as by allowing a user to specify a network location accessible through NIC for loading a recovery image for booting the information handling system).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined inventions of Fut and Wal to include the idea of operating at non-tampered cores as taught by Sur so that the EOS enables power-efficient operations to allow the recovery process to be completed efficiently.
Claim 5: the combination of Fut and Wal teaches the information processing system according to claim 3, but analogous art Sur teaches wherein the one or the plurality of processors are configured to, when an instruction to restart the information processing apparatus is issued by the user who operates the terminal as the predetermined condition, restart the information processing apparatus to achieve recovery from the tampering. ([05] the EOS may provide a user interface and execute individual tasks of the BIOS as instructed by the user … [035] The F2 module may present a user interface for configuring the information handling system, such as by changing settings stored in NVRAM and/or CMOS. A BIOSConnect module may be integrated with the EOS through the network node that may be coupled to the network interface card (NIC). The BIOSConnect module may present a user interface for performing recovery operations, such as by allowing a user to specify a network location accessible through NIC for loading a recovery image for booting the information handling system; [037] The EOS controls the high-efficiency processor core to execute EOS operations before booting an operating system, such as diagnostics, recovery, updates, tampering, malware, reboot, and other functions; the pre-boot operations includes the F2, BIOSConnect, eDiags, and/or Recovery operation. The pre-boot modules integrated as a portion of the EOS).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined inventions of Fut and Wal to include the idea of operating cores based on a criterion to restart/reboot as taught by Sur so that the EOS enables power-efficient operations to allow the recovery process to be completed efficiently from tampering.
Claim 6: the combination of Fut and Wal teaches the information processing system according to claim 5, but analogous art Sur teaches wherein the one or the plurality of processors are configured to display on the terminal a user interface for issuing an instruction to restart the information processing apparatus. ([035] The BIOSConnect module may present a user interface for performing recovery operations, such as by allowing a user to specify a network location accessible through NIC for loading a recovery image for booting the information handling system).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined inventions of Fut and Wal to include the idea of operating at non-tampered cores as taught by Sur so that the EOS enables power-efficient operations to allow the recovery process to be completed efficiently.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fut, Wal and Sur as applied to claim 3 above, and further in view of Novoa et al (US ), Nov.
Claim 7: the combination of Fut, Wal and Sur teaches the information processing system according to claim 3, wherein the one or the plurality of processors are configured to: in a case where the second processing has been executed or has been scheduled to be executed, [set a schedule] to restart to achieve recovery from the tampering; and when the second processing is completed as the predetermined condition, restart the information processing apparatus to achieve recovery from the tampering. (Fut: [044-46, Fig. 3] Based on the determination result of the cause of the abnormal operation, the recovery determination module determines whether the storage device can be recovered by updating the firmware for normal operation ... and if the recovery determination module determines that the storage device can be recovered by updating the firmware, the recovery execution module reads the firmware for recovery ... from the nonvolatile memory and stores it in the volatile memory. The recovery execution module verifies the reliability of the firmware for recovery using the security assurance data managed by the Security CPU. If the verification is successful, the recovery execution module overwrites the firmware for normal operation on the nonvolatile memory to the firmware for recovery and reboots the storage device).
but analogous art Nov teaches set a schedule to restart.([04] If a WDT expires (e.g., due to a hardware fault, program error, intentional hardware reset initiation, or time expiration), a time out signal may be generated, a watchdog timer (WDT) flag may be set, and corrective action(s) may be taken (e.g., reboot the system, log the error event, run diagnostics, etc.) to recover from the error).
Therefore, it is prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined inventions of Fut, Wal and Sur to include the idea of set a schedule to restart as taught by Nov so that a critical or security sensitive application, service or driver would benefit from using a hardware-based watchdog timer (WDT) service to recover from information handling system malfunctions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Badri Champakesan whose telephone number is (571)270-3867. The examiner can normally be reached M-F: 8.30am-4.30pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/BADRINARAYANAN /Primary Examiner, Art Unit 2494.
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