Prosecution Insights
Last updated: April 19, 2026
Application No. 18/434,943

POWER METHOD FOR HIGHER CURRENT ASIC POWER DELIVERY

Non-Final OA §102
Filed
Feb 07, 2024
Examiner
PATEL, AMOL H
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cisco Technology Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
534 granted / 627 resolved
+17.2% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
17 currently pending
Career history
644
Total Applications
across all art units

Statute-Specific Performance

§103
49.7%
+9.7% vs TC avg
§102
38.6%
-1.4% vs TC avg
§112
7.1%
-32.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 627 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 6, 9-11, 16-17, 19, 21-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brunschwiler et al. (Pub. No. US 2015/0237729). As to claim 1, Brunschwiler discloses an apparatus 1 (fig. 1) comprising: a main printed circuit board 2 having a first side and a second side opposite the first side, the main printed circuit board having an open section; an integrated circuit 10 configured to attach to the first side of the main printed circuit board over the open section of the main printed circuit board; and a power block printed circuit board 3 sized and shaped to fit into the open section of the main printed circuit board, the power block printed circuit board having a first side that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit (¶0053-0054). As to claim 2, Brunschwiler discloses that the power block printed circuit board comprises multiple layers between the first side and the second side (figs. 2-3), and side planes around a periphery, the side planes configured to laterally contact and electrically connect with layers in the main printed circuit board to provide power into the main printed circuit board (fig. 7, see coupling element 14) As to claim 6, Brunschwiler discloses that the power block printed circuit board is secured to the main printed circuit board by sintering of a metallization paste (¶0069). As to claim 9, Brunschwiler discloses that the first side of the power block printed circuit board comprises a pin field or ball grid array that is configured to electrically connect to a pin field or ball grid array of the integrated circuit (fig. 6; ¶0054). As to claim 10, Brunschwiler discloses that the pin field or ball grid array on the first side of the power block printed circuit board is in a pattern that is configured to mate with the pin field or ball grid array on the integrated circuit to supply core power to the integrated circuit (fig. 6; ¶0054). As to claim 11, Brunschwiler discloses that the power block printed circuit board has a thickness that is greater than a thickness of the main printed circuit board and is secured to the main printed circuit board in the open section so that the first side of the power block printed circuit board is co-planar with the first side of the main printed circuit board, and the second side of the power block printed circuit board extends beyond the second side of the main printed circuit board (fig. 14). As to claim 16, Brunschwiler discloses an apparatus (fig. 1) comprising: a main printed circuit board 2 having a top and a bottom, the main printed circuit board having an open section over which an integrated circuit is configured to attach; and a power block printed circuit board 3 configured to fit into the open section of the main printed circuit board, the power block printed circuit board having a top that electrically connects to the integrated circuit to provide power to the integrated circuit from below (¶0053-0054). As to claim 17, Brunschwiler discloses that the power block printed circuit board comprises multiple layers between the top and bottom, and side planes around a periphery, the side planes configured to laterally contact and electrically connect with layers in the main printed circuit board to provide power into the main printed circuit board (fig. 7, see coupling element 14). As to claim 19, Brunschwiler discloses that the top of the power block printed circuit board comprises a pin field or ball grid array that is configured to electrically connect to a pin field or ball grid array of the integrated circuit, wherein the pin field or ball grid array on the top of the power block printed circuit board is in a pattern that is configured to mate with the pin field or ball grid array on the integrated circuit to supply core power to the integrated circuit (fig. 6; ¶0054). As to claim 21, Brunschwiler discloses a method comprising: providing a main printed circuit board 2 (fig. 1) having a top and a bottom, the main printed circuit board having an open section that extends between the top and bottom; mounting an integrated circuit 10 to a top of the main printed circuit board over the open section so that at least a portion of the bottom of the integrated circuit is exposed over the open section; and inserting a power block printed circuit board 3 into the open section of the main printed circuit board from below so that a top of the power block printed circuit board makes electrical contact to the bottom of the integrated circuit (¶0053-0054). As to claim 22, Brunschwiler discloses securing the power block printed circuit board to the main printed circuit board using a conductive paste and sintering process, and/or one engaging one or more spring clips (¶0069). Allowable Subject Matter Claims 3-5, 7-8, 12-13, 14-15, 18, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding dependent claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claims 1 and 2, a combination of limitations that discloses wherein the side planes around the periphery of the power block printed circuit board comprise a tooth pattern such that each tooth of the tooth pattern has at least two faces that supports power or ground side rails. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 7, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 1, a combination of limitations that discloses one or more spring clips to secure the power block printed circuit board to the second side of the main printed circuit board. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 8, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 1, a combination of limitations that discloses a frame that engages a second side of the power block printed circuit board; and a spring mechanism configured to bias the frame to apply pressure between the power block printed circuit board and the integrated circuit. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claims 1 and 11, a combination of limitations that discloses a cold plate having an open section configured to fit over a portion of the power block printed circuit board that extends beyond the second side of the main printed circuit board, wherein the cold plate is configured to dissipate heat from the power block printed circuit board. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 14, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 1, a combination of limitations that discloses a plurality of power block printed circuit boards that collectively fit into and fill the open section of the main printed circuit board, each of the plurality of power block printed circuit boards having a first side that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 18, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claims 16 and 18, a combination of limitations that discloses wherein the side planes around the periphery of the power block printed circuit board comprise a tooth pattern such that each tooth of the tooth pattern has at least two faces that supports power or ground side rails, and wherein the open section of the main printed circuit board is sized and shaped to accommodate the tooth pattern on the periphery of the power block printed circuit board. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 20, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 16, a combination of limitations that discloses a plurality of power block printed circuit boards that collectively fit into and fill the open section of the main printed circuit board, each of the plurality of power block printed circuit boards having a top that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit. None of the reference art of record discloses or renders obvious such a combination. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al. (Pub. No. US 2023/0363085) discloses a power regulator accommodated into an opening of a circuit board. Zhang et al. (Pub. No. US 2023/0078561) discloses a vertical power delivery packaging structure. Lee et al. (Pub. No. US 2016/0316557) discloses a connection board inserted into a circuit board. Huang et al. (Pub. No. US 2014/0177177) discloses a circuit board with a replaceable carrying portion. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY THOMPSON can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMOL H PATEL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Feb 07, 2024
Application Filed
Mar 29, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.5%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 627 resolved cases by this examiner. Grant probability derived from career allow rate.

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