DETAILED ACTION
This Notice is responsive to communication filed on 06/25/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 06/25/2026 under 37 C.F.R. 1.111 has been entered. Claims 1, 2, 4, 5, and 10 remain pending in the application. Claims 3 and 6-9 have been cancelled.
The claim objections set forth in the Non-Final Rejection dated 03/31/2026 have been overcome by the amendment filed on 06/25/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1, 2, 4, 5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shima et al. (US 20210020782 A1), and further in view of Huang et al. (US 20240222445).
Regarding claim 1, Shima teaches a semiconductor device comprising:
a first gate electrode Fig. 1B: 106;
a first insulating layer Fig. 1B: 103 on the first gate electrode Fig. 1B: 106;
an oxide semiconductor layer Fig. 1B: 108 on the first insulating layer Fig. 1B: 103;
a second insulating layer Fig. 1B: 110 on the oxide semiconductor layer Fig. 1B: 108; and
a second gate electrode Fig. 1B: 112 on the second insulating layer Fig. 1B: 110,
wherein the first insulating layer Fig. 1B: 103 includes a first layer Fig. 1B: 103a including silicon and nitrogen (para. 0078), a second layer Fig. 1B: 103b including silicon and oxygen (para. 0088), and a third layer Fig. 1B: 103c including aluminum and oxygen (para. 0084),
a thickness of the first layer Fig. 1B: 103a is 10 nm or more and 100 nm or less (para. 0097 teaches a range of 10nm-50nm that includes the range of the claimed first layer),
a thickness of the second layer Fig. 1B: 103b is 10 nm or more and 50 nm or less (para. 100 teaches a range of 20nm-350nm that includes the range of the claimed second layer),
a total thickness of the first layer Fig. 1B: 103a and the second layer Fig. 1B: 103b is 20 nm or more and 150nm or less (combining the ranges taught by para. 97 and 100 teaches a joint thickness which includes the range claimed by claim 1),
a thickness of the third layer Fig. 1B: 103c is 1 nm or more and 10 nm or less (para. 0098 teaches a range of 5nm-20nm that includes the range of the claimed third layer), and
a thickness of the second insulating layer is equal to or smaller than the total thickness of the first layer and the second layer.
Huang discloses the following claim limitations not explicitly disclosed by Shima:
a thickness of the second insulating layer Fig. 2: 107 is equal to the or smaller than the total thickness of the first layer and the second layer Fig. 2: 105 (para. 0067).
The specification of the present invention discloses a film thickness of the gate insulating layer 150, of SiO material, is 75nm, 100nm, 125nm, or 150nm (para. 0053). Huang discloses the thicknesses of the gate insulating film 62, of SiO material) is preferably in a range from 5nm to 400nm, and may be 100nm or 150nm (para. 0066-0067), therefore the claimed thickness is not novel as Huang teaches the disclosed range. Furthermore, according to MPEP § 2144.05, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ranges taught by Shima with the thickness of the range taught by Huang and use a gate insulating film with a thickness that is equal to or smaller than the total thickness of the first layer and the second layer.
Regarding claim 2, Shima teaches the semiconductor device according to claim 1, wherein the second layer Fig. 1B: 103b is arranged on the first layer Fig. 1B: 103a, and the third layer Fig. 1B: 103c is arranged on the second layer Fig. 1B: 103b (shown in Fig. 1B).
Regarding claim 4, Shima teaches the semiconductor device according to claim 2, wherein impurity concentration in a vicinity of an upper surface of the oxide semiconductor layer Fig. 1B: 108 is 1×1019/cm3 or more (para. 0194).
Regarding claim 5, Shima teaches the semiconductor device according to claim 4, wherein impurity concentration in a vicinity of an upper surface of the first layer Fig. 1B: 103a is 1×1019/cm3 or less.
In para. 0550-0552, Shima et al. show examples where the impurity concentrations of the first layer (para. 0552, silicon nitride oxide layer 103a) are shown to be 4.69x1013/cm3 (Fig. 27D), 3.55x1015/cm3 (Fig. 27E), and 9.47x1014/cm3 (Fig. 27F), which are all less than the claimed impurity concentration of 1x1019/cm3.
Regarding claim 10, semiconductor device according to claim 2, wherein a thickness of the second insulating layer is Fig. 1B: 110 is 10 nm or more and 100 nm or less.
Para. 0013 teaches the second insulating layer/film has a thickness greater than or equal to 50% and less than or equal to 95% of the total thickness of the first insulating layer. The ranges of the first insulating layer taught in paragraphs 0097, 0100, and 0098 can be totaled to teach the thickness of the second insulating layer of claim 8, i.e. a first layer thickness of 30nm, a second layer thickness of 20nm, and a third layer thickness of 20nm, total a first insulating layer of 70nm. A 50% - 95% range gives a thickness range of 35nm – 66.5nm which overlaps the range of claim 10.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In response to applicant's argument that the prior art Shina describes the thickness of insulating film 103, including layers 103a to 103c, however the ranges of the thickness are very broad, and the limited ranges as claimed are critical, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). The claimed thickness range of the second insulating layer/gate insulating layer 150 lacks novelty.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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