DETAILED ACTION
The response filed on April 19, 2026 is being examined.
Election/Restriction
Applicant’s election of Species A (figure 3) encompassing claims 1-7 and 9-16 in the reply filed on 04/09/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 8 is withdrawn from further consideration as being drawn to a nonelected subject matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 15, the limitation “the metal ball includes copper balls” is being indefinite for failing to particularly point out and distinctly claim the subject matter.
It appears to be copper ball instead of copper ball based on disclosure.
Therefore, proper clarification is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 7, 10 are rejected under 35 U.S.C.102(a)(1) or (a)(2) (whichever apply) as being anticipated by Yu et al. (CN103094464, herein referred as Yu).
Rejection of claim 1, Yu discloses a printed circuit board (fig. 6-7 of Yu) comprising:
an insulating layer (an insulating layer 21);
a through-hole penetrating through the insulating layer from an upper surface to a lower surface of the insulating layer and having an inclined wall surface (see inclined surface of the trough hole in the insulating layer 21) ;
a metal ball (a conductive ball 230 can be selected from the group consisting of copper) disposed within the through-hole on the inclined wall surface ;
the metal ball having a circular cross-section defined by a diameter that is greater than a minimum diameter of the through-hole and less than a maximum diameter of the through-hole (see the figures);
a metal via filling the through-hole and surrounding an upper surface and a lower surface of the metal ball, and disposed on the upper and lower surfaces of the insulating layer (wherein metal wiring having top metal wiring 231 and bottom metal wiring 231 filling though hole, surrounding of metal ball 230, and disposed on the upper and lower surfaces of the insulating layer 21).
Rejection of claim 2, Yu discloses the printed circuit board according to claim 1, wherein the through-hole is divided into an upper region and a lower region by the metal ball, and a cross-section area of the upper region and a cross-section area of the lower region are different (see figures of the Yu wherein area of the upper region and a cross-section area of the lower region are different).
Rejection of claim 4, Yu discloses the printed circuit board according to claim 1, wherein the metal via comprises further comprising: first and second metal wirings disposed on the upper surface and the lower surface of the insulating layer, respectively, and connected to each other through the metal ball (see the figure of Yu).
Rejection of claim 7, Yu discloses the printed circuit board according to claim 1, wherein the through-hole has a tapered shape so that a width of an upper end of the through-hole is wider than a width of a lower end of the through-hole on a cross-section (see figures of Yu).
Rejection of claim 10, Chen discloses the printed circuit board according to claim 1, wherein the metal ball includes a copper ball (230 which includes copper).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5-6 are rejected under 35 U.S.C.103 as being unpatentable over Yu in view of Takano et al. (US20110056740, herein referred to as Takano) or Uzoh et al. (US8785790, herein referred to as Uzoh).
Rejection of claim 3 and 5, Yu discloses the printed circuit board according to claim 2 (see figure 4 of Yu), wherein the first metal wiring comprises: a first seed metal layer disposed on the inclined wall surface in the upper region and also cover an upper portion of the metal ball (a first or top 231 in the though hole within the at top of 21 covering 230); wherein the second metal wiring comprises: a second seed metal layer disposed on the inclined wall surface in the lower region and also cover a lower portion of the metal ball (claim 3) (a second or bottom 231 in the though hole within the at top of 21 covering 230); the first metal wiring comprises the first seed metal layer disposed on the upper surface of the insulating layer and the second metal wiring comprises the second seed metal layer disposed on the lower surface of the insulating layer (see top and bottom 231 in the figures).
Yu fails to disclose a first metal layer disposed on the first seed metal layer to fill an exposed portion of the through-hole in the upper region; and a second metal layer disposed on the second seed metal layer to fill another portion of the through-hole in the lower region (claim 3); the first metal wiring comprises the first seed metal layer disposed on the upper surface of the insulating layer, and the first metal layer disposed on the first seed metal layer, and, and the second metal layer disposed on the second seed metal layer (claim 5).
Takano or Uzoh discloses a first metal layer made of copper disposed on the first seed metal layer made of copper and filling a first recess portion of the first seed layer as well as upper; and a second metal layer disposed on the second seed metal layer and filling a second recess portion of the second seed layer (see figure 2 of Takano and see paragraph 0006 of Takano wherein each made of Copper; Or see figures 10D, 11D of Uzoh).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Yu to have each metal layer in the respective seed layer as taught Takano or Uzoh so that it would provide flat pad or land portion on the through hole to efficiently connect adjacent components aw well it increase strength of the overall metal wiring layers, and able to increase capacity of current and/or heat from one side of the via to other side of the via. It is well known and old that use of seed layer with metal layer in the via hole as well as land portion of via hole which allows seed electroplating to work effectively even on small or complex via geometries, and the seed layer ensures the metal layer bonds well and deposits evenly, while metal layer provides the low-resistance path for signals and power, ensures mechanical strength and durability, and maintains electrical continuity between layers.
Rejection of claims 6, Yu in view of Takano disclose the printed circuit board according to claim 5, wherein each of the first and second seed metal layers includes copper, and each of the first and second metal layers includes copper (see seed layers and metal layers as explained in the rejection of claim 3 above).
Claim 9 is rejected under 35 U.S.C.103 as being unpateable over Yu in view of Fushie et al. (US20130075146, herein referred to as Fushie).
Rejection of claims 9, Yu discloses the printed circuit board according to claim 1, but fails to disclose the insulating layer includes a glass layer.
Fushie discloses the insulating layer includes a glass layer (glass substrate 2 in figures of Fushie).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Yu to have the insulating layer includes a glass layer as taught by Fushie because the glass substrate has good properties such as smoothness, hardness, insulation and workability; thus being suitable for a core substrate of the wiring substrate (paragraph 0041 of Fushie).
Claims 11-12 rejected under 35 U.S.C.103 as being unpateable over Yu in view of Chen et al. (US20220022316, herein referred to as Chen).
Rejection of claims 11-12, Yu discloses the printed circuit board according to claim 10, but fails to disclose wherein the metal ball further comprises a nickel layer covering a surface of the copper ball (claim 11); wherein the metal ball further includes a solder layer covering a surface of the nickel layer (claim 11).
Chen discloses the metal ball further comprises a nickel layer covering a surface of the copper ball (claim 11); wherein the metal ball further includes a solder layer covering a surface of the nickel layer (claim 11) (Chen has metal ball 110 which includes a nickel layer covering a surface of the copper ball and a solder layer covering a surface of the nickel layer, see specification ).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Yu to have metal ball as taught by Chen because the first metal layer as Nickel considered as a protective layer to protect the surface of the copper core, and having metal solder layer 116 so that the metal ball 110 are efficiently bonded to adjacent metal layer.
Claims 13-14 and 16 are rejected under 35 U.S.C.103 as being unpatentable over Yu in view of Takano or Uzoh (see rejection of claim 1, 3-6 above).
Claim 15 is rejected under 35 U.S.C.103 as being unpateable over Yu, Takano or Uzoh, and further in view of Fushie et al. (US20130075146, herein referred to as Fushie).
Rejection of claim 15, Yu in view of Takano or Uzoh disclose the printed circuit board according to claim 13, the metal ball includes copper ball(Yu discloses 230made of copper) each of the first and second seed metal layers includes copper, and each of the first and second metal layers includes copper (see the in rejection of claim 13 wherein seed and metal layers includes copper).
Yu in view of Takano or Uzoh fail to disclose the insulating layer includes a glass layer.
Fushie discloses the insulating layer includes a glass layer (glass substrate 2 in figures of Fushie).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Yu in view of Takano or Uzoh to have the insulating layer includes a glass layer as taught by Fushie because the glass substrate has good properties such as smoothness, hardness, insulation and workability; thus being suitable for a core substrate of the wiring substrate (paragraph 0041 of Fushie).
Claims 13-14 and 16 are rejected under 35 U.S.C.103 as being unpatentable over Fukase (US2009009552016) in view of Takano et al. (US20110056740, herein referred to as Takano).
Rejection of claim 13 and 16, Fukase discloses a printed circuit board (fig. 4 of Fukase) comprising:
an insulating layer (12b in figure 4);
a through-hole penetrating through the insulating layer from an upper surface to a lower surface of the insulating layer and having an inclined wall surface (see inclined surface of 12b in the insulating layer in figure 4) ;
a metal ball (insulated metal ball 22a-22b having inner portion 22a has a conductive made of copper) disposed on the through-hole on the inclined wall surface and in contact with the inclined wall surface (see the figures); and
a metal via filling the through-hole and surrounding an upper surface of the metal ball and lower surface of the metal ball, and disposed on the upper and lower surfaces of the insulating layer (12C filling though hole and surrounding of metal ball 22a);
wherein the first metal wiring comprises: a first seed metal layer disposed on the inclined wall surface in the upper region and also cover an upper portion of the metal ball (a first or top 12C with a first recess portion in the though hole within the at top of the 12a-b covering 22a-b); wherein the second metal wiring comprises: a second seed metal layer disposed on the inclined wall surface in the lower region and also cover a lower portion of the metal ball (a second or bottom 12C with a second recess portion in the though hole within the at bottom of the 12a-b covering 22a-b); the first metal wiring comprises the first seed metal layer disposed on the upper surface of the insulating layer and the second metal wiring comprises the second seed metal layer disposed on the lower surface of the insulating layer (see top and bottom 12C in the figures).
Fukase further discloses the two seed layers, a first copper seed layer 12C having a first recess portion in an upper region of the through-hole, and a second copper seed layer 12C having a second recess portion in a lower region of the through-hole in figures 4 of Fukase and see specification.
Fukase fails to disclose a first metal layer disposed on the first seed metal layer to fill an exposed portion of the through-hole in the upper region; and a second metal layer disposed on the second seed metal layer to fill another portion of the through-hole in the lower region (claim 3); the first metal wiring comprises the first seed metal layer disposed on the upper surface of the insulating layer, and the first metal layer disposed on the first seed metal layer, and, and the second metal layer disposed on the second seed metal layer (claim 5).
Takano discloses a first metal layer made of copper disposed on the first seed metal layer made of copper and filling a first recess portion of the first seed layer as well as upper ; and a second metal layer disposed on the second seed metal layer and filling a second recess portion of the second seed layer in figure 2 of Takano and see paragraph 0006 of Takano.
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Fukase to have each copper metal layer in the respective copper seed layer as taught Takano so that it would provide flat pad or land portion on the through hole to efficiently connect adjacent components aw well it increase strength of the overall metal wiring layers, and able to increase capacity of current from one side of the via to other side of the via. It is well known and old that use of seed layer with metal layer in the via hole as well as land portion of via hole which allows seed electroplating to work effectively even on small or complex via geometries, and the seed layer ensures the metal layer bonds well and deposits evenly, while metal layer provides the low-resistance path for signals and power, ensures mechanical strength and durability, and maintains electrical continuity between layers.
Rejection of claim 14, Fukase in view of Takano disclose the printed circuit board according to claim 13, wherein at least a portion of the wall surface of the through-hole has an inclined shape, and the metal ball is in contact with an inclined portion of the wall surface of the through-hole (see the figures of Yu).
Claim 15 is rejected under 35 U.S.C.103 as being unpateable over Fukase and Takano further in view of Fushie et al. (US20130075146, herein referred to as Fushie).
Rejection of claim 15, Fukase in view of Takano disclose the printed circuit board according to claim 13, the metal ball includes copper ball (Fukase discloses “a conductor ball 22 a (spherical copper particle)”), each of the first and second seed metal layers includes copper, and each of the first and second metal layers includes copper (see the in rejection of claim 13 wherein seed and metal layers includes copper).
Fukase in view of Takano fail to disclose the insulating layer includes a glass layer.
Fushie discloses the insulating layer includes a glass layer (glass substrate 2 in figures of Fushie).
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the printed circuit board of Fukase to have the insulating layer includes a glass layer as taught by Fushie because the glass substrate has good properties such as smoothness, hardness, insulation and workability; thus being suitable for a core substrate of the wiring substrate (paragraph 0041 of Fushie).
Pertinent Prior Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent art in the present case, all of which disclose various circuit boards.
Response to Arguments
The Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection in view of Yu does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Response to applicant arguments of claim 13 (Fukase in view of Takano), note that It is well known and old that use of seed layer with metal layer in the via hole as well as land portion of via hole which allows seed electroplating to work effectively even on small or complex via geometries, and the seed layer ensures the metal layer bonds well and deposits evenly, while metal layer provides the low-resistance path for signals and power, ensures mechanical strength and durability, and maintains electrical continuity between layers. Therefore, It is obvious to ordinary skill in the art to combine Fukase in view of Takano so the given reason.
Therefore, applicants argument is not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday.
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/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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