DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-14) in the reply filed on 6/22/2026 is acknowledged.
Claims 15-20 have been withdrawn from consideration as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Application Publication to Santori 2018/0106967US.
In terms of Claim 1, Santori teaches a photonic circuit (Figures 1, 6a, and 6c), comprising: a first photonic gate (Figure 6c: teaches a circuit having multiple optical gate circuits positioned in an array from 691-1 to 691-N) having a first set of one or more inputs (Figure 1: 100 illustrate an example of an optical gate [0046] having one or more inputs 101-103, the gate 100 is an example of an optical gate at 691-1 as shown in Figure 6c) and a first set of one or more outputs (Figure 1: 141/142), the first set of one or more inputs (Figure 1: 101-103) configured to receive one or more photonic input signals (Figure 1: 101-103), the first photonic gate configured to generate (Figure 1: 100 [0046]; and Figure 6c: 691-1), based at least in part on the one or more photonic input signals (Figure 1: output from 100 at location of 141/142 is based on input signal 101-103), one or more first photonic intermediate output signals (Figure 1: 124/125 function as output coupler for an output signal exiting resonator 120 and into 137 [0032] and towards 141/142) at the first set of one or more outputs (Figure 1: 125/124. 137 and 141/142); and a first nonlinear photonic circuit (Figure 6c: wherein each optical gate circuit contain nonlinear resonator 692-2, the 2nd optical gate i.e. 691-2 in the array shown in Figure 6c is considered the nonlinear circuit wherein the nonlinear component is located in the second resonator 692-2 within the 2nd optical gate 691-2) having one or more first inputs (Figure 1: illustrates inputs 101-103 for the optical gate, Figure 6c shows multiple optical gate coupling together to each other, thus the inputs of 101-103 can be considered the inputs of the second optical gate 691-2 as well) and one or more first outputs (Figure 1: outputs on 691-2 similar to output 141/142; examples of two optical gates being coupled to each other is shown in Figure 6b wherein one gate is coupled to another gate circuit in a 2nd resonator), the one or more first inputs coupled to the first set of one or more outputs (141/142 located in the second gate) and configured to receive the one or more first photonic intermediate output signals (Figure 1: 124/125 function as output coupler for an output signal exiting resonator 120 and into 137 [0032] and towards 141/142 located in the 2nd optical gate 691-2 shown in Figure 6c), the first nonlinear photonic circuit (Figure 6c: 2nd optical gate 691-2 in the array having nonlinear element 692-2 in the array) configured to generate one or more first photonic output signals (Figure 1: at 125/124 towards 137, 141/142) at the one or more first outputs (141/142) by applying a first nonlinear transfer function of the first nonlinear photonic circuit (Figure 1: at 120 [0029]) to the one or more first photonic intermediate output signals (at 125/124).
As for Claim 2, Santori teaches the device of Claim 1, wherein the first photonic gate (Figure 6c: 691-1) comprises: a first photonic combiner (Figure 1: wherein branch 102/103 intersect wherein branch 112 meets 101 at 115) having a first input configured to receive a first photonic input signal (101) of the one or more photonic inputs signals (101-103) and a second input (102) configured to receive a second photonic input signal of the one or more photonic inputs signals (Figure 1: 101/102); a first phase shifter coupled to an output of the first photonic combiner (Santori indicates 2 structures such as 105 [0045], and weak couplers such as 540/115/135 [0051], are capable of performing phase shifting [0045] and [0051]. Figure 1: 135 is the 1st phase shifter, is coupled to 115 via 117 and 125 and 120) ;a second phase shifter (Figure 1: 105) having an input coupled to an input of the first set of one or more inputs (Figure 1: phase shifter 105 is can be coupled to the inputs of 102/103 [0045]) and configured to receive a bias signal having an amplitude value that is constant over time [0021]; and a second photonic combiner (Figure 1: 120 which combines the top portion to the lower portion) having a first input ( 124) coupled to an output of the first phase shifter (124 is coupled to output of 135 via 125) and a second input coupled (122) to an output of the second phase shifter (122 is coupled to output 105 via 110/112 and 117), an output of the second photonic combiner representing an output of the first set of one or more outputs (light output via 124 is then sent to the first set of one or more outputs 141/142).
PNG
media_image1.png
526
692
media_image1.png
Greyscale
As for Claim 3, Santori teaches the device of Claim 2, wherein a logical function of a cascading connection of the first photonic gate and the first nonlinear photonic circuit depends on a first phase shift applied by the first phase shifter, a second phase shift applied by the second phase shifter, and the amplitude value of the bias signal (See Figure 6a: wherein two optical circuits coupled to each other similar to Figure 6c wherein each gate has its only ring resonator, the phase shift at any of the weak coupler from Figure 1 or from 105 is feed into a second circuit via a continuous path and then output at output 1-4, as shown in Figure 6c there maybe even more gates that are coupled to each other in order to achieve more complex logic functions between the gates).
As for Claim 4, Santori teaches the device of Claim 1, wherein the photonic circuit is part of a photonic processor (Figure 6c: 690 is considered a processor by the examiner because it contains multiple optical gates that capable of processing logic functions such AND or OR [0040]) comprising the photonic circuit and a set of one or more other photonic circuits (Figure 6c: 691-1 to 691-N on 690), one or more inputs (Figure 1: 100 contains inputs 101-103) of the set of one or more other photonic circuits coupled to the one or more first outputs (141/142) of the first nonlinear photonic circuit (Figure 6c: each gate 691-1 or 691-2 contains nonlinear component in a ring resonator 692-1, the 2nd optical gate 691-2 is considered by the examiner as the nonlinear circuit).
As for Claim 5, Santori teaches the device of Claim 1, further comprising: a second photonic gate having a second set of one or more inputs and a second set of one or more outputs (Figure 6c: 3rd optical gate 691-3 in the array 691-N), a second set of one or more outputs (Figure 1: 141/142 in 3rd optical gate 691-3), the second set of one or more inputs (Figure 1: 101-103) configured to receive one or more photonic input signals (Figure 1: 101-103), the second photonic gate configured to generate (Figure 1: 100 [0046]; and Figure 6c: 691-3), based at least in part on the one or more photonic input signals (Figure 1: output from 100 at location of 141/142 is based on input signal 101-103), one or more second photonic intermediate output signals (Figure 1: 124/125 function as output coupler for an output signal exiting resonator 120 and into 137 [0032] and towards 141/142) at the second set of one or more outputs (Figure 1: 125/124. 137 and 141/142); and a second nonlinear photonic circuit (Figure 6c: wherein each optical gate circuit contain nonlinear resonator 692-4, the 4th optical gate i.e. 691-4 in the array shown in Figure 6c is considered the nonlinear circuit wherein the nonlinear component is located in the second resonator 692-4 within the 4th optical gate 691-4) having one or more second inputs (Figure 1: illustrates inputs 101-103 for the optical gate, Figure 6c shows multiple optical gate coupling together to each other, thus the inputs of 101-103 can be considered the inputs of the 4th optical gate 691-4 as well) and one or more second outputs (Figure 1: outputs on 691-4 similar to output 141/142; examples of two optical gates being coupled to each other is shown in Figure 6b wherein one gate is coupled to another gate circuit in a 4th resonator), the one or more second inputs coupled to the second set of one or more outputs (141/142 located in the 4th gate 691-4) and configured to receive the one or more second photonic intermediate output signals (Figure 1: 124/125 function as output coupler for an output signal exiting resonator 120 and into 137 [0032] and towards 141/142 located in the 4th optical gate 691-3 shown in Figure 6c), the second nonlinear photonic circuit (Figure 6c: 2nd optical gate 691-4 in the array having nonlinear element 692-4 in the array) configured to generate one or more second photonic output signals (Figure 1: at 125/124 towards 137, 141/142) at the one or more second outputs (141/142) by applying a second nonlinear transfer function of the first nonlinear photonic circuit (Figure 1: at 120 [0029]) to the one or more second photonic intermediate output signals (at 125/124).
As for Claim 6, Santori teaches the device of Claim 5, wherein a logical function of a cascading connection of the first photonic gate and the first nonlinear photonic circuit depends on a first phase shift applied by the first phase shifter (Figure 6a and 6c), a second phase shift applied by the second phase shifter, and the amplitude value of the bias signal (See Figure 6a: wherein two optical circuits coupled to each other similar to Figure 6c wherein each gate has its only ring resonator, the phase shift at any of the weak coupler from Figure 1 or from 105 is feed into a second circuit via a continuous path and then output at output 1-4, as shown in Figure 6c there maybe even more gates that are coupled to each other in order to achieve more complex logic functions between the gates).
As for Claim 7, Santori teaches the device of Claim 5, wherein the second photonic gate (Figure 6c: gate 691-4 is considered the 2nd photonic gate) comprises: a phase shifter (Figure 1: phase shifters made of weaker couplers such as 105/135) coupled to an output of the one or more first outputs (Figure 1: 135 is coupled to outputs 141/142) of the first nonlinear photonic circuit (Figure 6a: illustrate a optical gate pair wherein the top portion corresponds to the gate similar to one shown in Figure 1, the bottom portions corresponds to nonlinear circuit since it contains a resonator which produces nonlinear effects. Figure 6c: illustrate a plurality of gates going up to 691-N and 692-N. Base on drawings of Figure 6a we can continue to sequence by adding more gates with resonators structure of a 2nd optical gate and 2nd nonlinear circuits producing a circuits with 4 optical gates total wherein 4th gates corresponds to nonlinear circuit); and a photonic combiner (Figure 1 above: 2nd combiner) having a first input coupled to an output of the phase shifter (Figure 1: 105) and a second input (103) configured to receive a bias signal having an amplitude value that is constant over time [0021] and Figure 10: 1015), an output of the photonic combiner coupled to an input of the one or more second inputs of the second nonlinear photonic circuit (Figure 6a: illustrates to the input of top gate is routed into the bottom circuits having a resonator to produce nonlinear effects as shown in Figure 6c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Santori 2018/0106967US in view of US Patent Application Publication to Nazarathy 2010/0097677US.
In regard to Claims 8-11, Santori teaches the device of Claim 5. Santori does not teach wherein the first nonlinear photonic circuit comprises a semiconductor optical amplifier (SOA) based amplitude thresholder and the second nonlinear photonic circuit comprises a saturable absorber.
Nazarathy does teach an optical gate wherein the first nonlinear photonic circuit comprises a semiconductor optical amplifier (SOA) based amplitude thresholder and the second nonlinear photonic circuit comprises a saturable absorber (Figure 5: PE). As for the limitations of Claim 9-11: “wherein the saturable absorber operates in a first operating regime defined by a first portion of a cumulative nonlinear transfer function of the first and second nonlinear photonic circuits or in a second operating regime defined by a second portion of the cumulative nonlinear transfer function, and the SOA based amplitude thresholder operates in a third operating regime defined by a third portion of the cumulative nonlinear transfer function” as recited in claim 9.
Claim 10, wherein the SOA based amplitude thresholder is configured to operate in the third operating regime based on one or more first amplitudes of the one or more first photonic intermediate output signals generated by the first photonic gate, and the saturable absorber is configured to operate in the first operating regime or the second operating regime based on one or more second amplitudes of the one or more second photonic intermediate output signals generated by the second photonic gate.
Claim 11, wherein: the saturable absorber is configured to apply a transfer gain of the second nonlinear transfer function to one or more second amplitudes of the one or more second photonic intermediate output signals, when the saturable absorber operates in the second operating regime; the saturable absorber is configured to saturate the one or more second amplitudes of the one or more second photonic intermediate output signals to a first amplitude level, when the saturable absorber operates in the first operating regime; and the SOA based amplitude thresholder is configured to saturate one or more first amplitudes of the one or more first photonic intermediate output signals to a second amplitude level greater than the first amplitude level, when the SOA-based amplitude thresholder operates in the third operating regime.
The examiner considers these functionalities (claim 9 through claim 11) as functional operations of which the PE circuit having SOA or Saturable absorbers to be capable of performing the function. The functionality itself does not impart any structural differences from the structure shown in Figure 5: PE once it has been modified to the nonlinear structures of 2nd and 4th gate circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 2nd gate which correspond to the 1st nonlinear circuit, and the 4th gate which correspond to the 2nd nonlinear circuit as shown by Santori in Figure 6c to replace the resonator structure that produce nonlinear effects with the SOA or Saturable absorber as shown by Nazarathy Figure 5 for because SOA as a nonlinear element is known to produce better power efficiency (Nazarathy’s [0002]). Further the SOA functions as an amplifier to produce nonlinear effects while Saturable absorber absorbs gain to produce nonlinear effects. One would be motivated to use SOA 1st nonlinear circuit then Saturable absorber in 2nd nonlinear circuit because the saturable absorber can absorb the amplified energy produce by the SOA to achieve the same nonlinear effects. This will optimize further the power usage of the device.
As for Claim 12, Santori / Nazarathy teaches the device of Claim 5, wherein Santori teaches the photonic circuit is part of a photonic processor (Figure 6c: 690 is considered a processor by the examiner because it contains multiple optical gates that capable of processing logic functions such AND or OR [0040]) comprising the photonic circuit and a set of one or more other photonic circuits (Figure 6c: 691-1 to 691-N on 690), one or more inputs (Figure 1: 100 contains inputs 101-103) of the set of one or more other photonic circuits coupled to the one or more first outputs (141/142) of the first nonlinear photonic circuit (Figure 6c: each gate 691-1 or 691-2 contains nonlinear component in a ring resonator 692-1, the 2nd optical gate 691-2 is considered by the examiner as the nonlinear circuit).
In regard to Claims 13 and 14, Santori teaches the device of Claim 1. Santori does not teach wherein the first nonlinear photonic circuit comprises a semiconductor optical amplifier (SOA) based amplitude thresholder and the second nonlinear photonic circuit comprises a saturable absorber; wherein the first nonlinear photonic circuit comprises one or more amplitude thresholders configured to apply the first nonlinear transfer function by saturating one or more amplitudes of the one or more first photonic intermediate output signals to one or more defined amplitude levels when generating the one or more first photonic output signals; and wherein the first nonlinear photonic circuit comprises a cascading connection of one or more saturable absorbers and one or more semiconductor optical amplifier-based amplitude thresholders.
Nazarathy does teach an optical gate wherein the first nonlinear photonic circuit comprises a semiconductor optical amplifier (SOA) based amplitude thresholder and the second nonlinear photonic circuit comprises a saturable absorber (Figure 5: PE); wherein the first nonlinear photonic circuit comprises one or more amplitude thresholders (Figure 5: SOA or Saturablae absorber) configured to apply the first nonlinear transfer function by saturating one or more amplitudes of the one or more first photonic intermediate output signals to one or more defined amplitude levels when generating the one or more first photonic output signals (Figure 5: PE can be used to effect the output signal to flip the gate to perform other logic operations as shown in Figure 7); and wherein the first nonlinear photonic circuit comprises a cascading connection of one or more saturable absorbers and one or more semiconductor optical amplifier-based amplitude thresholders (Figure 7: PE is cascading from top to bottom to change different outputs to perform different logic operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 2nd gate which correspond to the 1st nonlinear circuit, and the 4th gate which correspond to the 2nd nonlinear circuit as shown by Santori in Figure 6c to replace the resonator structure that produce nonlinear effects with the SOA or Saturable absorber as shown by Nazarathy Figure 5 for because SOA as a nonlinear element is known to produce better power efficiency (Nazarathy’s [0002]). Further the SOA functions as an amplifier to produce nonlinear effects while Saturable absorber absorbs gain to produce nonlinear effects. One would be motivated to use SOA 1st nonlinear circuit then Saturable absorber in 2nd nonlinear circuit because the saturable absorber can absorb the amplified energy produce by the SOA to achieve the same nonlinear effects. This will optimize further the power usage of the device. Further the cascading operations allow the logic gate to perform different logic operations thus reducing the need to have so many optical gates for each functionality.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Patent Application Publication Mower 2015/0354938US teaches cascading optical gates having nonlinear effects to control logic attributes pertaining to 1 and 0 within a logic gate and photonic processor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 5712722397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HOANG Q TRAN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
Prosecution Insights