DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/04/2026 has been entered.
Response to Amendment
This Office Action is in response to the Request for Continued Examination filed on 06/04/2026.
Status of the Claims:
Claim(s) 1, 6, 14 and 19-20 has/have been amended.
Claim(s) 2 and 15 was/were previously canceled.
Claim(s) 1, 3-14 and 16-20 is/are pending in this Office Action.
Response to Arguments
Applicant’s arguments are deemed moot since they are directed to the newly added claim limitations, not previously presented and not against the previous rejected limitations. Newly added limitations are addressed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 9-10, 12-14, 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over IDS provided reference US 2015/0207975 to NGUYEN et al. (hereinafter NGUYEN) in view of US 2017/0168755 to Lo (hereinafter Lo).
Regarding independent claim 1, NGUYEN teaches a device for image processing (computer system 100, see Fig. 1), the device comprising:
an image sensor configured to capture a first set of image frames (camera comprising an image sensor 310, see Fig. 3. The camera may be coupled to the camera processor, see Fig. 1 and par. [0025]);
a buffer integrated within the image sensor and configured to store information indicative of luminance of each image frame of the first set of image frames … (In various embodiments, GPU 112 may be integrated with one or more of the other elements of FIG. 1 to form a single hardware block. For example, GPU 112 may be integrated with the display controller 111, camera processor 120, video encoder/decoder, audio device 126, and/or other connection circuitry included in the computer system 100, see pars. [0027-0028]. Fig. 3 show the flicker detection and correction engine implemented by camera processor 120 of Fig. 1. Fig. 3 also shows interface with internal memory 106, hence the integration of various components of Fig. 1 is contemplated as disclosed. The flicker detection unit 320 stores frames of luminance data over multiple input image frames, see par. [0045]); and processing circuitry (flicker detection and correction engine 300, see par. [0042]) configured to:
determine a flicker correction parameter based on the luminance across each of the first set of image frames (determine the flicker correction as flicker band frequencies from the frame of luminance data, see pars. [0046-0053]); and
generate additional image frames that are for display based on the flicker correction parameter (the flicker correction unit 330 corrects flicker bands in the input image frames based on the visibility, confidence, and flicker band frequencies, see pars. [0053, 0095]).
But NGUYEN fails to clearly specify “…configured to store…the first set of image frames in contiguous addresses of the buffer,
retrieve, with a single read command that includes an address range for the contiguous addresses of the buffer, the information indicative of luminance of each image frame of the first set of image frames, the address range including the contiguous addresses of the buffer for the information indicative of luminance for each image frame of the first set of image frames”.
However, Lo teaches a processing circuit configured to “…configured to store…the first set of image frames in contiguous addresses of the buffer (The method 300 further includes generating 308 addresses based on the state of the write pointer 212 and the number of write requests received 302. As noted above, where the current value of the pointer is C prior to receiving 302 the write requests and updating 306 the write pointer 212 and N write requests were received, then the addresses generated may then be C, C+1, ... C+N-1, where C points to the next address to write to. Where C points to the most recently written address, then the addresses generated then be C+1, C+2, ... C+N. The addresses may be generated in the form of a range, e.g. a data pair <C, N-1> or <C+l,N>, where one value is the start address and the other value is an offset from the start address. See Lo par. [0052], note that the addresses are contiguous (emphasis added).),
retrieve, with a single read command that includes an address range for the contiguous addresses of the buffer, the information indicative of luminance of each image frame of the first set of image frames, the address range including the contiguous addresses of the buffer for the information indicative of luminance for each image frame of the first set of image frames (The method 312 may further include outputting 322 to the memory subsystem 204 one or more read commands including the addresses generated at step 308 (see above that the addresses are contiguous, Lo par. [0052]), the read commands effective to invoke retrieval of data at the addresses in the one or more write commands from one of the memory devices 104 and return this data to the processing device 102. As noted above, N read commands may be output 322 for each read request received 302 and each including one of the addresses generated at step 308. Alternatively, a single read command may be output 322 that specifies all N addresses generated at step 308 or a range of addresses (e.g., start address and offset) spanning all N addresses. The read commands are then executed by the memory device 104 to which they are addressed and the method ends. See Lo par. [0058] (emphasis added))”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to retrieving with a single read command that includes an address range for addresses of the buffer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above device as taught by NGUYEN, by incorporating the teachings of Lo.
One of ordinary skill in the art would have been motivated to do this modification in order to use a single read command may be output that specifies all N addresses generated or a range of addresses as suggested by Lo (see par. [0058]).
Regarding claim 3, NGUYEN in view of Lo teaches the device of claim 1, wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames utilizing a rolling shutter (camera 310 may use rolling shutter, see par. [0043]).
Regarding claim 4, NGUYEN in view of Lo teaches the device of claim 1, wherein the information indicative of luminance of each image frame of the first set of image frames comprises information indicative of an average luminance of each image frame of the first set of image frames (the flicker detection unit 320 could perform the sum, scaled sum, or average function on the downscaled image frames first, see par. [0046]).
Regarding claim 5, NGUYEN in view of Lo teaches the device of claim 1, wherein the buffer is a dedicated buffer of the image sensor (DRAM 220 within the system memory 104 may be used to store frame data, see par. [0031]).
Regarding claim 6, NGUYEN in view of Lo teaches the device of claim 1, wherein the image sensor is configured to capture the first set of image frames during a boot-up period of a camera session, and the processing circuitry is configured to determine the flicker correction parameter before any image frames are displayed for that camera session (in step 702 image frame from camera are received, see Fig. 7, NGUYEN discloses in par. [0031] the final pixel data, hence flicker corrected frames are delivered for display, no indication of other display instances are disclosed).
Regarding claim 9, NGUYEN in view of Lo teaches the device of claim 1, wherein the image sensor is configured to capture the first set of image frames at a first resolution (the flicker detection unit 320 only uses one channel, it also can downscale the first set of images to reduce processing time, hence it uses lower resolution, see NGUYEN pars. [0044-0045]), and wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames at a second resolution, wherein the first resolution is less than the second resolution (captures the final images at the normal resolution, hence higher than the first, see NGUYEN par. [0095]).
Regarding claim 10, NGUYEN in view of Lo teaches the device of claim 1, wherein the processing circuitry is configured to output the additional image frames for display as part of a preview mode (the final pixel data, hence flicker corrected frames are delivered for display, see NGUYEN par. [0031]).
Regarding claim 12, NGUYEN in view of Lo teaches the device of claim 1, wherein the processing circuitry is configured to determine a lighting frequency based on the luminance across each of the first set of image frames (see the flicker band frequencies detection procedure in pars. [0044-0052]), and
wherein to determine the flicker correction parameter, the processing circuitry is configured to determine the flicker correction parameter based on the lighting frequency (the flicker correction unit 330 corrects flicker bands in the input image frames based on the visibility, confidence, and flicker band frequencies, see par. [0053]).
Regarding claim 13, NGUYEN in view of Lo teaches the device of claim 1, wherein to determine the flicker correction parameter, the processing circuitry is configured to determine an exposure time of the image sensor (see adjustment of the exposure time for flicker correction in Fig. 4B and pars. [0063-0065]).
Regarding independent claim(s) 14 and dependent claims 16-18, claim(s) is/are drawn to the method used by the corresponding apparatus in claim(s) 1, 3-4, 6 and is/are rejected for the same reasons used above.
Regarding independent claim(s) 20, claim(s) is/are drawn to the non-transitory computer-readable storage medium used by the corresponding apparatus in claim(s) 1 and is/are rejected for the same reasons used above.
Claim(s) 7-8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over NGUYEN in view of Lo as applied to claim 1 and 14 above, and further in view of IDS provided reference US 2015/0172529 to AOTA (hereinafter AOTA).
Regarding claim 7, NGUYEN in view of Lo teaches the device of claim 1.
But NGUYEN in view of Lo fails to clearly specify “wherein the image sensor is configured to capture the first set of image frames at a first capture rate, and wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames at a second capture rate, wherein the first capture rate is greater than the second capture rate”.
However, AOTA teaches an imaging device that corrects flicker “wherein the image sensor is configured to capture the first set of image frames at a first capture rate, and capture the additional image frames at a second capture rate, wherein the first capture rate is greater than the second capture rate (surface flicker detection occurs at a high frame rate capture, see par. [0041] and correction of surface flicker is achieved using the flicker frequency as the frame rate, hence lower frame rate, see par. [0044])”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to flicker detection and correction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above system as taught by NGUYEN, by incorporating the teachings as taught by AOTA.
One of ordinary skill in the art would have been motivated to do this modification in order to cancel flicker in high-speed camera mode as suggested by AOTA (see par. [0020]).
Regarding claim 8, NGUYEN in view of AOTA teaches the device of claim 7, wherein the first capture rate is at least 240 frames per second (240fps drive, see AOTA Fig. 3 (d)).
Regarding claim 19, claim(s) is/are drawn to the method used by the corresponding apparatus in claim(s) 7 and 9 and is/are rejected for the same reasons used above.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over NGUYEN in view of Lo as applied to claim 1 above, and further in view of IDS provided reference US 2015/0002694 to Hasegawa (hereinafter Hasegawa).
Regarding claim 11, NGUYEN teaches the device of claim 10.
But NGUYEN fails to clearly specify “wherein the processing circuitry is configured to update the flicker correction parameter based on the additional image frames that are displayed as part of the preview mode”.
However, Hasegawa teaches “wherein the processing circuitry is configured to update the flicker correction parameter based on the additional image frames that are displayed as part of the preview mode (displaying in the preview mode with an indicator of presence of flicker with icon 802 in Fig. 7B and displays an image with flicker correction and an image without flicker correction in Figs. 8A-8C)”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to flicker correction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above system as taught by NGUYEN, by incorporating the teachings by Hasegawa.
One of ordinary skill in the art would have been motivated to do this modification in order to provide information for a user to determine whether control to suppress an influence of a flicker should be performed as suggested by Hasegawa (see par. [0008]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGEL L GARCES-RIVERA whose telephone number is (571)270-7268. The examiner can normally be reached Mon-Fri 9AM-5PM ET.
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/ANGEL L GARCES-RIVERA/Examiner, Art Unit 2637
/SINH TRAN/Supervisory Patent Examiner, Art Unit 2637
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