DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the Amendment filed on 11/24/2025.
Status of the Claims:
Claim(s) 1, 3, 7, 9, 14, 16 and 19-20 has/have been amended.
Claim(s) 2 and 15 has/have been canceled.
Claim(s) 1, 3-14 and 16-20 is/are pending in this Office Action.
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 14 and 20 have been considered but are moot in view of the new ground(s) of rejection necessitated by amendments.
Regarding claim 4 and claim 17, Applicant argues “In claims 4 and 17, the information indicative of luminance of each image frame is what is retrieved from the buffer, where that information is an average luminance. In paragraph [0046], Nguyen is describing accessing the image frame, and performing sum, scaled sum, or average function, to then subtract the results from selected image frames. Nothing in such disclosure relates to the information that is retrieved from the buffer and is indicative of a luminance of image frames being an average luminance, as set forth in claim 4, and similar features of claim 17”.
Examiner respectfully disagrees, NGUYEN states in paragraph [0046] that “Alternatively, the flicker detection unit 320 could perform the sum, scaled sum, or average function on the downscaled image frames first, generating a 1 x 64 array for each stored image frame”. That generated data has to be stored for later processing. However further processing does not negate the fact that the average luminance data was generated for each frame and hence “the information indicative of luminance of each image frame of the first set of image frames comprises information indicative of an average luminance of each image frame of the first set of image frame” as claimed. Therefore, the rejection is maintained.
Regarding claim 5, Applicant argues "While DRAM 220 may be used to store frame data, nothing in Nguyen discloses that DRAM 220 is a dedicated buffer of an image sensor. DRAM 220 of Nguyen is shared across different components. For instance, Nguyen, in paragraph [0031], states that "[w]hen processing graphics data, one or more DRAMs 220 within system memory 104 can be used as graphics memory that stores one or more conventional frame buffers and, if needed, one or more other render targets as well" (emphasis added). Clearly in Nguyen, DRAM 220 is shared and therefore cannot be considered as "a dedicated buffer of the image sensor," as set forth in claim 5.
Examiner respectfully disagrees, NGUYEN discloses in par. [0037] for example that DRAM 220s are partitioned, “Each partition unit 215 is coupled to the one or more dynamic random access memories (DRAMs) 220 residing within system memory 104. In one embodiment, the number of partition units 215 equals the number of DRAMs 220, and each partition unit 215 is coupled to a different DRAM 220. being dedicated to the image sensor”. As cited the GPU can use one or more DRAMs 220, the CPU as well can use one or more DRAMs (see par. [0040]), hence each using their dedicated buffer, and hence the image sensor can have a dedicated buffer. Therefore, the rejection is maintained.
Regarding claims 6 and 18, Applicant argues “While step 702, in Nguyen, states "receive image frame from camera," nothing in Nguyen relates to any boot-up period, as set forth in claims 6 and 18. Moreover, step 708, in Nguyen, states "subtract downsampled image frame from prior image frame for processing." Hence, in Nguyen there is a "prior image frame" that will be displayed but for which exposure time parameters, like those in step 724 of Nguyen are not determined. Therefore, in Nguyen there are image frames that will be displayed before exposure time is calculated. This in direct contrast to the features of claims 6 and 18 that "the processing circuitry is configured to determine the flicker correction parameter before any image frames are displayed for that camera session."
Examiner respectfully disagrees, nothing in NGUYEN state that a prior image frame is displayed in the flicker detection and correction method 700 as stated, however in par. [0092] it is sated the method is “for detecting and correcting flicker in image frames captured with a rolling shutter” (emphasis added). Hence, the method does imply to capture various frames in order to perform the method. The camera being set up to perform the method, at startup will perform the method and hence “capture the first set of images during a boot-up period of the camera session” as claimed. Therefore, the rejection is maintained.
Regarding claims 7-8, 11 and 19, Applicant argues “Claims 7, 8, 11, and 19 recite novel and non-obvious features at least by virtue of dependency upon respective independent claims but recite novel and non-obvious features for additional reasons as well. AOTA and Hasegawa have not been shown to disclose the features of the independent claims.
Furthermore, claim 7 recites "wherein the image sensor is configured to capture the first set of image frames at a first capture rate, and wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames at a second capture rate, wherein the first capture rate is greater than the second capture rate." Claim 19 recites similar features.
In support of the rejection, the Office Action noted that Nguyen does not disclose the features of claim 7, but cited paragraphs [0041] and [0044] of AOTA. In particular, on page 8, the Office Action stated that "surface flicker detection occurs at a high frame rate capture, see par. [0041] and correction of surface flicker is achieved using the flicker frequency as the frame rate, hence lower frame rate, per par. [0044]."
Again, in claims 7 and 19, the first set of images, whose luminance is used to determine the flicker correction parameter, are captured at a higher rate than the additional images that are for display. Nothing in cited portions of AOTA relates disclosing such features of claims 7 and 19. Rather, the cited portions of AOTA relate to surface flicker detection and correction of surface flicker. However, nothing in such disclosure relates to rates at which images are captured, much less in the manner set forth in claims 7 and 19.
For at least these reasons, claims 7, 8, 11, and 19 recite novel and non-obvious features. Applicant respectfully requests withdrawal of the rejection under 35 U.S.C. § 103 of claims 7, 8, 11, and 19.”
Examiner respectfully disagrees, AOTA "surface flicker detection occurs at a high frame rate capture, see par. [0041] (clearly AOTA states capturing at a high frame rate that are used for flicker detection) and correction of surface flicker is achieved using the flicker frequency as the frame rate, hence lower frame rate (clearly AOTA captures the additional frames for display as the surface flicker correction), per par. [0044] (emphasis added)". Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 112
The rejections of claims 3, 7, 9, 16 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention is hereby withdrawn due to the amendments presented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 9-10, 12-14, 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over IDS provided reference US 2015/0207975 to NGUYEN et al. (hereinafter NGUYEN) in view of US 2017/0168755 to Lo (hereinafter Lo).
Regarding independent claim 1, NGUYEN teaches a device for image processing (computer system 100, see Fig. 1), the device comprising:
an image sensor configured to capture a first set of image frames (camera comprising an image sensor 310, see Fig. 3. The camera may be coupled to the camera processor, see Fig. 1 and par. [0025]);
a buffer configured to store information indicative of luminance of each image frame of the first set of image frames (the flicker detection unit 320 stores frames of luminance data over multiple input image frames, see par. [0045]); and
processing circuitry (flicker detection and correction engine 300, see par. [0042]) configured to:
determine a flicker correction parameter based on the luminance across each of the first set of image frames (determine the flicker correction as flicker band frequencies from the frame of luminance data, see pars. [0046-0053]); and
generate additional image frames that are for display based on the flicker correction parameter (the flicker correction unit 330 corrects flicker bands in the input image frames based on the visibility, confidence, and flicker band frequencies, see pars. [0053, 0095]).
But NGUYEN fails to clearly specify “retrieve, with a single read command that includes an address range for addresses of the buffer, the information indicative of luminance of each image frame of the first set of image frames, the address range including addresses for the information indicative of luminance for each image frame of the first set of image frames”.
However, Lo teaches a processing circuit configured to “retrieve, with a single read command that includes an address range for addresses of the buffer, the information indicative of luminance of each image frame of the first set of image frames, the address range including addresses for the information indicative of luminance for each image frame of the first set of image frames (The method 312 may further include outputting 322 to the memory subsystem 204 one or more read commands including the addresses generated at step 308, the read commands effective to invoke retrieval of data at the addresses in the one or more write commands from one of the memory devices 104 and return this data to the processing device 102. As noted above, N read commands may be output 322 for each read request received 302 and each including one of the addresses generated at step 308. Alternatively, a single read command may be output 322 that specifies all N addresses generated at step 308 or a range of addresses (e.g., start address and offset) spanning all N addresses. The read commands are then executed by the memory device 104 to which they are addressed and the method ends. See par. [0058] (emphasis added))”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to retrieving with a single read command that includes an address range for addresses of the buffer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above device as taught by NGUYEN, by incorporating the teachings of Lo.
One of ordinary skill in the art would have been motivated to do this modification in order to use a single read command may be output that specifies all N addresses generated or a range of addresses as suggested by Lo (see par. [0058]).
Regarding claim 3, NGUYEN in view of Lo teaches the device of claim 1, wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames utilizing a rolling shutter (camera 310 may use rolling shutter, see par. [0043]).
Regarding claim 4, NGUYEN in view of Lo teaches the device of claim 1, wherein the information indicative of luminance of each image frame of the first set of image frames comprises information indicative of an average luminance of each image frame of the first set of image frames (the flicker detection unit 320 could perform the sum, scaled sum, or average function on the downscaled image frames first, see par. [0046]).
Regarding claim 5, NGUYEN in view of Lo teaches the device of claim 1, wherein the buffer is a dedicated buffer of the image sensor (DRAM 220 within the system memory 104 may be used to store frame data, see par. [0031]).
Regarding claim 6, NGUYEN in view of Lo teaches the device of claim 1, wherein the image sensor is configured to capture the first set of images during a boot-up period of a camera session, and the processing circuitry is configured to determine the flicker correction parameter before any image frames are displayed for that camera session (in step 702 image frame from camera are received, see Fig. 7, NGUYEN discloses in par. [0031] the final pixel data, hence flicker corrected frames are delivered for display, no indication of other display instances are disclosed).
Regarding claim 9, NGUYEN in view of Lo teaches the device of claim 1, wherein the image sensor is configured to capture the first set of image frames at a first resolution (the flicker detection unit 320 only uses one channel, it also can downscale the first set of images to reduce processing time, hence it uses lower resolution, see NGUYEN pars. [0044-0045]), and wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames at a second resolution, wherein the first resolution is less than the second resolution (captures the final images at the normal resolution, hence higher than the first, see NGUYEN par. [0095]).
Regarding claim 10, NGUYEN in view of Lo teaches the device of claim 1, wherein the processing circuitry is configured to output the additional image frames for display as part of a preview mode (the final pixel data, hence flicker corrected frames are delivered for display, see NGUYEN par. [0031]).
Regarding claim 12, NGUYEN in view of Lo teaches the device of claim 1, wherein the processing circuitry is configured to determine a lighting frequency based on the luminance across each of the first set of image frames (see the flicker band frequencies detection procedure in pars. [0044-0052]), and
wherein to determine the flicker correction parameter, the processing circuitry is configured to determine the flicker correction parameter based on the lighting frequency (the flicker correction unit 330 corrects flicker bands in the input image frames based on the visibility, confidence, and flicker band frequencies, see par. [0053]).
Regarding claim 13, NGUYEN in view of Lo teaches the device of claim 1, wherein to determine the flicker correction parameter, the processing circuitry is configured to determine an exposure time of the image sensor (see adjustment of the exposure time for flicker correction in Fig. 4B and pars. [0063-0065]).
Regarding independent claim(s) 14 and dependent claims 16-18, claim(s) is/are drawn to the method used by the corresponding apparatus in claim(s) 1, 3-4, 6 and is/are rejected for the same reasons used above.
Regarding independent claim(s) 20, claim(s) is/are drawn to the non-transitory computer-readable storage medium used by the corresponding apparatus in claim(s) 1 and is/are rejected for the same reasons used above.
Claim(s) 7-8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over NGUYEN in view of Lo as applied to claim 1 and 14 above, and further in view of IDS provided reference US 2015/0172529 to AOTA (hereinafter AOTA).
Regarding claim 7, NGUYEN in view of Lo teaches the device of claim 1.
But NGUYEN in view of Lo fails to clearly specify “wherein the image sensor is configured to capture the first set of image frames at a first capture rate, and wherein to generate the additional image frames, the processing circuitry is configured to cause the image sensor to capture the additional image frames at a second capture rate, wherein the first capture rate is greater than the second capture rate”.
However, AOTA teaches an imaging device that corrects flicker “wherein the image sensor is configured to capture the first set of image frames at a first capture rate, and capture the additional image frames at a second capture rate, wherein the first capture rate is greater than the second capture rate (surface flicker detection occurs at a high frame rate capture, see par. [0041] and correction of surface flicker is achieved using the flicker frequency as the frame rate, hence lower frame rate, see par. [0044])”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to flicker detection and correction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above system as taught by NGUYEN, by incorporating the teachings as taught by AOTA.
One of ordinary skill in the art would have been motivated to do this modification in order to cancel flicker in high-speed camera mode as suggested by AOTA (see par. [0020]).
Regarding claim 8, NGUYEN in view of AOTA teaches the device of claim 7, wherein the first capture rate is at least 240 frames per second (240fps drive, see AOTA Fig. 3 (d)).
Regarding claim 19, claim(s) is/are drawn to the method used by the corresponding apparatus in claim(s) 7 and 9 and is/are rejected for the same reasons used above.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over NGUYEN in view of Lo as applied to claim 1 above, and further in view of IDS provided reference US 2015/0002694 to Hasegawa (hereinafter Hasegawa).
Regarding claim 11, NGUYEN teaches the device of claim 10.
But NGUYEN fails to clearly specify “wherein the processing circuitry is configured to update the flicker correction parameter based on the additional image frames that are displayed as part of the preview mode”.
However, Hasegawa teaches “wherein the processing circuitry is configured to update the flicker correction parameter based on the additional image frames that are displayed as part of the preview mode (displaying in the preview mode with an indicator of presence of flicker with icon 802 in Fig. 7B and displays an image with flicker correction and an image without flicker correction in Figs. 8A-8C)”.
References are analogous art because they are from the same field of endeavor and/or are reasonably pertinent to the particular problem with which the applicant was concerned because they relate to flicker correction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above system as taught by NGUYEN, by incorporating the teachings by Hasegawa.
One of ordinary skill in the art would have been motivated to do this modification in order to provide information for a user to determine whether control to suppress an influence of a flicker should be performed as suggested by Hasegawa (see par. [0008]).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0308784 to Schmidt discloses a method includes receiving, at a dynamic random access memory (DRAM) device, a single READ-THEN-CLEAR command. The single READ-THEN-CLEAR command has a column address of a column in an array of memory cells. Particular data content is stored in memory cells associated with the column address. The method also includes, in response to receiving the single READ-THEN-CLEAR command, reading the particular data content and clearing the particular data content after reading the particular data content.
US 2014/0176586 to Gruber et al. discloses techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGEL L GARCES-RIVERA whose telephone number is (571)270-7268. The examiner can normally be reached Mon-Fri 9AM-5PM ET.
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/ANGEL L GARCES-RIVERA/Examiner, Art Unit 2637
/SINH TRAN/Supervisory Patent Examiner, Art Unit 2637